JPH046868A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH046868A JPH046868A JP2107849A JP10784990A JPH046868A JP H046868 A JPH046868 A JP H046868A JP 2107849 A JP2107849 A JP 2107849A JP 10784990 A JP10784990 A JP 10784990A JP H046868 A JPH046868 A JP H046868A
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- Prior art keywords
- circuit
- power supply
- voltage
- output
- input
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000007257 malfunction Effects 0.000 abstract description 24
- 238000010586 diagram Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 2
- 206010042135 Stomatitis necrotising Diseases 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 201000008585 noma Diseases 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- Static Random-Access Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の概要］
チップ内に流れる大電流による誤動作を防止するように
した半導体集積回路に関し、
小電流回路と該回路の出力を受ける大電流回路の各電源
配線を別にしても、小電流、大電流各回路とも誤動作が
生じないようにすることを目的とし、
半導体チップ内に独立した電源配線を複数個有する半導
体集積回路において、該複数個の電源配線間を、電圧リ
ミッタ素子または電圧リミッタ回路で接続するよう構成
する。[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor integrated circuit designed to prevent malfunctions caused by large currents flowing within a chip, each power supply wiring for a small current circuit and a large current circuit receiving the output of the circuit is separated. In semiconductor integrated circuits that have multiple independent power supply wirings within a semiconductor chip, the purpose is to prevent malfunctions in both small and large current circuits even when the power supply wiring It is configured to be connected by a voltage limiter element or a voltage limiter circuit.
本発明は、チップ内に流れる大電流による誤動作を防止
するようにした半導体集積回路に関する。The present invention relates to a semiconductor integrated circuit that prevents malfunctions caused by large currents flowing within the chip.
近年ＬＳＩが発展し、たとえばメモリ（ＤＲＡＭ。In recent years, LSI has developed, such as memory (DRAM).
ＳＲＡＭ ）ではバンド幅の広いＸ１６ビ・ント並列出
力をもつものち必要になっており、論理ＬＳＩでは３２
ビツトの並列出力をもつものもある。ところがこのよう
に多ビットの出力が同時に駆動されるとＬＳＩチップに
は瞬時に大電流が流れる。これは、かってはＬＳＩの動
作速度がそれ程高速でなかったこともあって、ＬＳＩの
誤動作の原因ではなかったが、近年のようにＬＳＩの高
速化により出力信号も同様に高速で変化させる必要が生
じてくると、これは誤動作の原因になる。たとえば出力
端子は１００ＦＦ程度の負荷容量を駆動するが、出力電
圧変化を１Ｑｎｓで行うとき、論理振幅を４■とすると
並列１６ビツト出力では１００ＰＦｘ４Ｖｘ１６／１０
ｘｌＯ−ｑＳ＝０．６４アンペアの平均電流が過度的に
流れる。この電流の時間変化が激しいと、配線系のイン
ダクタンス成分によって接地電圧が不安定に動き、チ・
ンプ内で論理レベル“０”の状態が“１”と誤って判定
されてチップが誤動作する。本発明はこのような誤動作
の防止対策を施した半導体集積回路に係るものである。In SRAM), it is necessary to have wide-bandwidth X16 bit parallel output, and in logic LSI, 32 bit parallel output is required.
Some have bit parallel outputs. However, when multi-bit outputs are simultaneously driven in this way, a large current instantly flows through the LSI chip. This was not a cause of LSI malfunctions in the past, partly because the operating speed of LSIs was not that high, but as LSIs have become faster in recent years, it is now necessary to change the output signal at a similar high speed. If this occurs, this can cause malfunctions. For example, the output terminal drives a load capacitance of about 100FF, but when the output voltage changes in 1Qns and the logic amplitude is 4■, the parallel 16-bit output is 100PF x 4V x 16/10
An average current of xlO-qS=0.64 amperes flows transiently. If this current changes rapidly over time, the ground voltage will fluctuate unstablely due to the inductance component of the wiring system, leading to
A logic level "0" state is mistakenly determined to be "1" within the amplifier, causing the chip to malfunction. The present invention relates to a semiconductor integrated circuit that takes measures to prevent such malfunctions.
［従来の技術］
第５図は従来のＬＳＩの電源配線を示す。回路ｌはたと
えばメモリではデータ入力回路、アドレス入力回路（ア
ドレスバッファと称する）、メモリセルアレー等を含む
ブロックであり、回路２はデータ出力ハッファ等を含む
。図では省いているが出力ハッファの端子（パッド）
Ｄｏｕｔは１つとは限らず、そして複数の場合により事
態が深刻になる。[Prior Art] FIG. 5 shows the power supply wiring of a conventional LSI. For example, in a memory, the circuit 1 is a block including a data input circuit, an address input circuit (referred to as an address buffer), a memory cell array, etc., and the circuit 2 includes a data output huffer and the like. Although omitted in the diagram, the output huffer terminal (pad)
There is not only one Dout, and the situation becomes more serious when there are multiple Douts.
チップのボンディング端子（パッド）からパッケージの
ピン、ボード上の配線には寄生インダクタンスＬ、−Ｌ
４の発生は不可避である。チップＤｏｕｔ端子から高速
で信号出力を行うと、配線寄生容量ＣＬと配線インダク
タンスＬ２によって、本来接地電圧であるべきＶ ｓｉ
端子に図中に示すような過渡応答（リンギング）が生じ
る。このようにチップの接地電圧が振動したとき、回路
ｌの接地Ｖ １１１も同様に変化してしまうので、入力
端子ＤＩＮに与えられていた入力信号ＶＩＮが一定でも
、回路１の入力としては、入力端子り１、と接地■３８
．の間の値■、７′のように過渡変化する。たとえばＶ
ｉ ｎがＯボルトであっても■１１．側の振動によっ
て閾値■７を越える部分では、データ“ｌ”に対する信
号と同等に見做されるため回路１が誤動作する。There are parasitic inductances L and -L from the bonding terminals (pads) of the chip to the pins of the package and the wiring on the board.
The occurrence of 4 is inevitable. When a signal is output from the chip Dout terminal at high speed, the wiring parasitic capacitance CL and the wiring inductance L2 cause V si to be
A transient response (ringing) as shown in the figure occurs at the terminal. When the ground voltage of the chip oscillates in this way, the ground voltage V111 of circuit 1 also changes, so even if the input signal VIN applied to the input terminal DIN is constant, the input signal V111 of circuit 1 is Terminal 1, and ground ■38
．． There is a transient change between the values ■ and 7'. For example, V
Even if in is O volts ■11. In the portion where the threshold value (7) is exceeded due to side vibration, the circuit 1 malfunctions because it is regarded as being equivalent to a signal for data "1".
なお、この図のＥは例えば５■であるＮｆｌ、 Ｌ＋は
電源高電位（Ｖｃｃ）側配線の寄生インダクタンス、Ｌ
、は同低電位（Ｖ、、）側配線の寄生インダクタンスで
ある。Note that E in this figure is Nfl, which is, for example, 5■, L+ is the parasitic inductance of the power supply high potential (Vcc) side wiring, and L
, is the parasitic inductance of the wiring on the low potential (V, , ) side.
第５図では電源パッドｖＣＣ＋ Ｖａｔは１つで、こ
れを回路１．２が共用している。回路ｌの入力電圧に上
記の問題が生じるのは■１３パッドを共用していること
に依る。そこで第６図は回路１と回路２の電源系を別に
して前記雑音の波及を抑制しようとしたものであるが、
これでも不十分である。In FIG. 5, there is one power supply pad vCC+Vat, which is shared by the circuit 1.2. The reason why the above-mentioned problem occurs in the input voltage of the circuit 1 is that the 13 pads are shared. Therefore, Fig. 6 is an attempt to suppress the spread of the noise by separating the power supply systems of circuit 1 and circuit 2.
Even this is not enough.
なぜなら回路２が動作したときにＶ ｓｔｌが過渡応答
するので、接地配線を別にする回路ｌと回路２の接地レ
ベルが過渡的に異なってくる。この結果、接地雑音の乗
らない回路１と雑音でＶ ｓｏｌが振動している回路２
の接続部分のチップ内で回路２の入力電圧Ｖ＝、／ｌ＝
■、□−■よ−が図示のように振動する。この結果入力
が閾値■７を越える部分でＬをＨと判定する誤動作が生
じる。チップ内の回路のノイズマージン設定によるが、
入力回路部分のノイズマージンよりも回路内の方がノイ
ズマージンを大きく設定しやすい場合が多く、このため
第６図の方式は第５図よりも出力回路のスイッチングに
よる誤動作の率は低くできるが、とくにこれを意識した
設計をしないとかえって第６図の方式の方が誤動作しや
すいこともある。This is because when circuit 2 operates, V stl responds transiently, so that the ground levels of circuit 1 and circuit 2, which have separate ground wiring, become different transiently. As a result, circuit 1 has no ground noise and circuit 2 has Vsol oscillating due to noise.
The input voltage of circuit 2 within the chip at the connection part of V=, /l=
■, □-■yo- vibrate as shown. As a result, a malfunction occurs in which L is determined to be H at a portion where the input exceeds the threshold value (7). It depends on the noise margin setting of the circuit inside the chip.
It is often easier to set a larger noise margin within the circuit than the noise margin of the input circuit, and for this reason, the method shown in Figure 6 can lower the rate of malfunctions caused by switching in the output circuit than the method shown in Figure 5, but Unless the system is designed with this in mind, the system shown in Figure 6 may be more likely to malfunction.
なおこの図でＶＣＣＡ ＋ ＶＣＣＩ＋は回路１．２
の電源高電圧側端子、■ＳＳＡ ＋ ｖｓｓｗは回路
１．２の電源低電圧側端子である。■ｃｃＡ＋ Ｖｓｓ
Ａも電源Ｅへ接続されるが、これは図示しないパッケー
ジの端子ピンまたはこのＬＳＩを搭載するプリント板の
配線により行なわれる。電源電流が大きい集積回路では
電源パッドを複数個にして、１パッド当りの電源値を小
にする及び／又はパッド分散配置で電源配線の電圧降下
を小にする、ものがあるが、これは電源配線は１つで、
パッドのみ複数であり、独立した複数の電源配線を持つ
ものではない。In this diagram, VCCA + VCCI+ is circuit 1.2
The power supply high voltage side terminal, ■SSA + vssw is the power supply low voltage side terminal of circuit 1.2. ■ccA+Vss
A is also connected to a power source E, but this is done by terminal pins of a package (not shown) or wiring on a printed board on which this LSI is mounted. Some integrated circuits with large power supply currents have multiple power supply pads to reduce the power supply value per pad and/or have distributed pads to reduce the voltage drop in the power supply wiring. There is only one wire,
There are only multiple pads, and there are no independent power supply wirings.
［発明が解決しようとする課題］
このように、ＬＳＩの出力回路などの大電流回路と、入
力回路などの小電流回路の各電源配線の端子を共通にす
ると、出力回路が大電流を流したとき電源■□端子に生
じるリンギングが入力回路の入力を入力信号とは異なる
ものにして入力回路を誤動作させるという問題がある。[Problem to be solved by the invention] In this way, when the power supply wiring terminals of a large current circuit such as an LSI output circuit and a small current circuit such as an input circuit are made common, the output circuit causes a large current to flow. There is a problem in that the ringing that occurs at the power supply ■□ terminal causes the input of the input circuit to be different from the input signal, causing the input circuit to malfunction.
そこで出力回路の電源配線と入力回路の電源配線を別に
すると、入力回路の出力を受ける出力回路の入力が該入
力回路の出力とは異なったものになり、出力回路が誤動
作する。Therefore, if the power supply wiring for the output circuit and the power supply wiring for the input circuit are separated, the input of the output circuit that receives the output of the input circuit will be different from the output of the input circuit, causing the output circuit to malfunction.
本発明はか＼る点を改善し、小電流回路と該回路の出力
を受ける大電流回路の各電源配線を別にしても、小電流
、大電流各回路とも誤動作が生じないようにすることを
目的とするものである。The present invention improves these points and prevents malfunctions in both the small current circuit and the large current circuit, even if the power wiring for the small current circuit and the large current circuit that receives the output of the circuit are separated. The purpose is to
〔課題を解決するための手段］
第１図（ａ）に示すように本発明では、チップ上に独立
した（電源パッドが異なる）電源配線を複数本例では！
１と１．、ｌ、と１４の２個有する半導体集積回路の該
電源配線間を、電圧リミッタ素子または回路３，４で接
続する。[Means for Solving the Problems] As shown in FIG. 1(a), in the present invention, a plurality of independent power supply wirings (with different power supply pads) are provided on a chip!
1 and 1. , l, and 14, the power supply wirings of the semiconductor integrated circuit are connected by voltage limiter elements or circuits 3 and 4.
この電圧リミッタ素子または回路３，４は具体的には逆
並列接続のダイオードまたはダイオード接続したバイポ
ーラまたはＭＯＳトランジスタであり、電源配線！、と
１３．ｉ□と２４の電位差が所定値（ＶＦまたはＶｍｔ
）になるまでは両配線！１とｌｓ、ｌｚと！４を電気的
に分離しており、該所定値以上で両配線！１とｉ、、ｉ
ｔ ｔＬを電気的に接続する。■１または■１は０．６
〜０．８Ｖ程度の値であるが、上記所定値を大きくした
い場合は、該素子を２個、３個、・・・直列にして使用
すればよい。素子複数個直列の他に、これらを抵抗等と
組合せて回路構成にしてもよい。Specifically, the voltage limiter elements or circuits 3 and 4 are anti-parallel connected diodes or diode-connected bipolar or MOS transistors, and the power supply wiring! , and 13. The potential difference between i□ and 24 is a predetermined value (VF or Vmt
) until it becomes both wiring! 1 and ls, lz and! 4 is electrically separated, and both wires are connected above the specified value! 1 and i,,i
Connect t tL electrically. ■1 or ■1 is 0.6
Although the value is approximately 0.8 V, if it is desired to increase the above predetermined value, it is sufficient to use two, three, . . . elements in series. In addition to connecting a plurality of elements in series, these may be combined with a resistor or the like to form a circuit configuration.
独立した電源配線ｆ、と１．、Ｉ！、と１４は第１図（
ａ）では入力回路１．出力回路２のそれであるが、第１
図（ｂ）では電源配線！１と１２は回路１ａ。independent power supply wiring f, and 1. , I! , and 14 are shown in Figure 1 (
In a), input circuit 1. That of the output circuit 2, but the first
In figure (b), power supply wiring! 1 and 12 are circuits 1a.
ｌｂ、ｌｃのそれである。回路１ａは外部入力信号Ｖ
ｉｎを受け、回路１ｂは回路１ａの出力を受け、回路１
ｃは回路１ｂの出力を受け、この回路１ｃの出力を回路
２が受ける。This is that of lb and lc. Circuit 1a is an external input signal V
in, circuit 1b receives the output of circuit 1a, and circuit 1b receives the output of circuit 1a.
c receives the output of circuit 1b, and circuit 2 receives the output of circuit 1c.
第１図（Ｃ）では、回路１ａ、ｌｂ、ｌｃはそれぞれ独
立した電源配線１１とｆ２．ｆ、とｌｂ、ｌｔと２８で
給電される。従って本例ではチップ上に独立電源配線が
４個あり、各々が電圧リミッタ素子または回路３と４，
３ａと４ａ、３ｂと４ｂにより接続される。大電流を流
すのは回路２だけでなく、回路１ｂなどもそうである場
合は第１図（Ｃ）の構成が好ましい。大電流を流すこと
による電源配線の電位変化は、低電位Ｖ ｓｓ側だけで
なく、高電位■。、側でも発生する。この電位変化が問
題になるのは電源具なる系統の入力部であり、該入力部
の入力信号が入力端と電源低電位側との電位差として作
用する（このケースが一般的）場合は、電圧リミッタ素
子は電源低電位側だけに挿入すればよい。しかし該入力
部の入力信号が入力端と電源高電位側との電位差として
作用する場合（ＰＮＰトランジスタなどはこのケース）
は、電圧リミッタ素子を電源高電位側に挿入する必要が
ある。In FIG. 1(C), circuits 1a, lb, and lc each have independent power supply wiring 11 and f2. Power is supplied by f, lb, lt and 28. Therefore, in this example, there are four independent power supply wirings on the chip, each with voltage limiter elements or circuits 3 and 4,
They are connected by 3a and 4a, and 3b and 4b. If a large current flows not only in the circuit 2 but also in the circuit 1b, the configuration shown in FIG. 1(C) is preferable. The potential change in the power supply wiring due to the flow of a large current is not only on the low potential Vss side but also on the high potential ■. , also occurs on the side. This potential change becomes a problem at the input section of the power supply system, and if the input signal at the input section acts as a potential difference between the input terminal and the low potential side of the power supply (this is the case in general), the voltage The limiter element only needs to be inserted on the low potential side of the power supply. However, if the input signal of the input section acts as a potential difference between the input terminal and the high potential side of the power supply (this is the case for PNP transistors, etc.)
requires a voltage limiter element to be inserted on the high potential side of the power supply.
電源配線は詳しくはＲ，Ｌ、Ｃの分布定数回路として扱
うべきであり、また大電流による電位変動が問題になる
のは、異なる電源配線の２回路（一方の出力を他方が入
力する２回路）間であるから、電圧リミッタはこの部分
（一方の出力部と他方の入力部の各電源配線間）に挿入
するのが合理的である。In detail, power supply wiring should be treated as a distributed constant circuit of R, L, and C, and potential fluctuations due to large currents are a problem when two circuits with different power supply wiring (one output is input to the other circuit) ), it is reasonable to insert a voltage limiter in this part (between each power supply wiring of one output part and the other input part).
〔作用］
このように独立した電源配線間に電圧リミッタを挿入す
ると、該リミッタがオンする迄は各々は独立しており、
一方の回路（回路２とする）が流す大電流による電源配
線の電位変動を他方の回路（回路１とする）が受けない
という利点が得られる。勿論、この場合他方の回路ｌの
出力を受ける一方の回路２の入力は該電位変動を含むこ
とになるが、これは許容できる程度である（を圧リミッ
夕のターンオン値はこのように選ぶ）。許容できない大
きな電位変動では該電圧リミッタがオンし、両電源配線
を接続するので、上記一方の回路２０入力が含む上記電
位変動は許容値内に制限される。[Operation] When a voltage limiter is inserted between independent power supply wirings in this way, each one is independent until the limiter is turned on.
There is an advantage that the other circuit (referred to as circuit 1) is not affected by potential fluctuations in the power supply wiring due to the large current flowing through one circuit (referred to as circuit 2). Of course, in this case, the input of one circuit 2 that receives the output of the other circuit 1 will include this potential fluctuation, but this is tolerable (the turn-on value of the pressure limiter is selected in this way). . In the case of an unacceptably large potential variation, the voltage limiter turns on and connects both power supply lines, so that the potential variation included in one input of the circuit 20 is limited to within an allowable value.
電圧リミッタがオンすると、上記他方の回路ｌの入力信
号は該回路の電源配線の電位変動を含むことになるが、
これは一方の回路２の電源配線の電位変動より電圧リミ
ッタのターンオン値だけ小さく、許容値内に収まること
が期待できる。When the voltage limiter is turned on, the input signal of the other circuit l will include potential fluctuations of the power supply wiring of the circuit, but
This is smaller than the potential fluctuation of the power supply wiring of one circuit 2 by the turn-on value of the voltage limiter, and can be expected to fall within the allowable value.
こうして独立した電源配線を有する半導体集積回路で、
入力回路部も、また出力回路部も、回路が流した大電流
による電源配線の電位変動による誤動作を受けない又は
受けにくくすることが可能になる。In this way, in a semiconductor integrated circuit with independent power wiring,
Both the input circuit section and the output circuit section can be made immune to or less susceptible to malfunctions due to potential fluctuations in the power supply wiring due to large currents flowing through the circuits.
高速かつ多ビット並列Ｄｏｕｔ出力の瞬時大電流による
チップ内接地配線への雑音の混入は、配線のインダクタ
ンスによって引き起されかつインダクタンスは本質的に
ゼロにできないので、雑音発生を抑えることはせず、こ
の雑音があっても誤動作しないようにチップ内の信号レ
ベルを変えることで解決するのが本発明である。Noise intrusion into the in-chip ground wiring due to the instantaneous large current of the high-speed, multi-bit parallel Dout output is caused by the inductance of the wiring, and since inductance cannot essentially be reduced to zero, noise generation is not suppressed. The present invention solves the problem by changing the signal level within the chip so that it does not malfunction even in the presence of this noise.
第１図（ａ）では回路１は比較的瞬時電流の発生が少い
部分、回路２は出力バッファ回路等瞬時大電流の発生が
ある回路としており、接地系の配線は回路ｌと回路２で
分け、それぞれ■ＳＳＡ＋ ■ＳＳおの外部接続端子
をもつ。Ｖ ＳＥＡと■５８．の間には電圧リミッタ回
路３が入れられ、もしＶ ＳＳＡとＶｉｓａの間に電圧
差が生じたとき、電圧リミッタが動作する電圧ＶＬＩＭ
以内の電圧差ではｖ ｓｓａ側に生じた電圧はＶ ＳＥ
Ａ側に影響をもたない。しかしＶＬＩＭ以上の電圧がＶ
３３１に発生するとＶ ＳＥＡ側には発生振幅よりＶ
ＬＩＮだけ低い電圧が生じる。In Figure 1(a), circuit 1 is a part where a relatively small amount of instantaneous current is generated, and circuit 2 is a circuit where a large instantaneous current is generated, such as an output buffer circuit, and the grounding system wiring is between circuit 1 and circuit 2. Separated, each has external connection terminals for ■SSA+ and ■SS. V SEA and ■58. A voltage limiter circuit 3 is inserted between them, and if a voltage difference occurs between V SSA and Visa, the voltage limiter operates at a voltage VLIM.
If the voltage difference is within the range, the voltage generated on the v ssa side is V SE
It has no effect on the A side. However, if the voltage higher than VLIM is V
If it occurs at 331, the V SEA side will have V
A lower voltage is generated by LIN.
たとえばＤｏｕｔ端子に出力信号が出ると負荷容量から
ｖ ｓｓｍへ電流が流れ、ｖ ｓｓｍ電圧は第２図（ａ
）に示すように寄生インダクタンスと容量成分で瞬間的
に正方向、次に負方向へ向う。絶対的接地レベルに対し
て回路２の入力信号■１□は低レベルつまり絶対的接地
レベルに等しいとする。回路２の入力信号の相対値はＶ
ＩＺ ＶＳＳＩ＋であるから、これは第２図（ｂ）に
示すようにｖｓｓｌｌと逆相の信号となる。ここで破線
は従来の場合であるが、実線は電圧リミッタ回路３の効
果で、リミッタが働く電圧ＶＬＩＭまではＶ１□−Ｖ
３３！＋は変動するが、それ以上の電圧Ｖ ＳＥＡ側に
伝わる。このため第２図（Ｃ）の実線のようにＶ ＳＳ
ｋは■５．に対してＶＬＩＭだけ減少した電圧となる。For example, when an output signal is output to the Dout terminal, current flows from the load capacitance to v ssm, and the v ssm voltage is shown in Figure 2 (a
), it momentarily moves in the positive direction and then in the negative direction due to the parasitic inductance and capacitance components. It is assumed that the input signal 1□ of the circuit 2 is at a low level with respect to the absolute ground level, that is, equal to the absolute ground level. The relative value of the input signal of circuit 2 is V
Since it is IZ VSSI+, this becomes a signal with the opposite phase to vssll as shown in FIG. 2(b). Here, the broken line is the conventional case, but the solid line is the effect of the voltage limiter circuit 3, and the voltage up to the voltage VLIM at which the limiter works is V1□-V
33! + varies, but a higher voltage VS is transmitted to the SEA side. Therefore, as shown by the solid line in Figure 2 (C), V SS
k is ■5. The voltage is decreased by VLIM.
回路２の入力しきい値（°“０”レベルが“ｌ“レベル
と判定される電圧）を■１とすると、電圧リミッタがな
ければ第２図（ト））に示すように■７以上の電圧部分
Ｐで回路２は誤動作するが、本発明ではｖＬＩＭ〈■ア
と設定しであるので誤動作の恐れがない。If the input threshold of circuit 2 (the voltage at which the "0" level is determined to be the "l" level) is ■1, then if there is no voltage limiter, the input threshold value of Although the circuit 2 malfunctions at the voltage portion P, in the present invention, since vLIM<■A is set, there is no risk of malfunction.
回路１の入力電圧Ｖ ｉｌｌの相対値は■ｉＲｖｓｓＡ
でありこれは第２図（ｄ）に示すようにＶ ＳＳＡの逆
相である。回路１の入力しきい値は必ずしも回路２と同
一ではないが、はぼ等しい値でありＶｉａ ＶＳＳＡ
の振幅は（ｄ） ４こ示すようにＶ↑以下となるため誤
動作の恐れがない。The relative value of the input voltage Vill of circuit 1 is ■iRvssA
This is the opposite phase of V SSA as shown in FIG. 2(d). Although the input threshold of circuit 1 is not necessarily the same as that of circuit 2, it is approximately the same value, and Via VSSA
As the amplitude of (d)4 is below V↑, there is no risk of malfunction.
もちろんｖ ｓｓａに生しる雑音があまりに大きいと、
回路２例の入力部分はＶＬＩＭ以上の雑音にしかならな
いので誤動作はしないが、Ｖ ＳＥＡ側に伝わる雑音振
幅が増え、回路１の誤動作の可能性は出てくる。しかし
リミッタ回路が無い場合に比べれば振幅は減っているの
で誤動作の可能性は激減する。Of course, if the noise generated in v ssa is too large,
Since the input portion of the second example circuit has only noise higher than VLIM, it will not malfunction, but the noise amplitude transmitted to the VSEA side will increase, making it possible for circuit 1 to malfunction. However, since the amplitude is reduced compared to the case without a limiter circuit, the possibility of malfunction is drastically reduced.
第３図は本発明の実施例である。回路２はいわゆるデー
タ出力バッファアンプ系回路で、実際には４組〜１６組
の並列同時データ出力ができるように複数個置かれる。FIG. 3 shows an embodiment of the invention. The circuit 2 is a so-called data output buffer amplifier system circuit, and in reality, a plurality of circuits are provided so as to output data in parallel and simultaneously in 4 to 16 sets.
リミッタ回路３はＭＯＳトランジスタをダイオード接続
したものを逆並列（逆方向で並列）にし、ｖ ｓｓｍの
上昇、下降の両方に対応する。通常このリミッタ電圧は
０．７Ｖ〜１■である。またＶＣＣ側にも同様にリミッ
タ４を入れている。ただＶＣＣ側の電圧変動はＶ ｓｓ
側に比べると影響が小さいので（■５．側は接地電位と
して回路内各所で電圧の基準にされるため変動は影響が
大）、Ｖｃｅ側のリミツタ４は省くこともできる。この
回路の入力はＲＡ Ｓ （Ｒｏｓｙ Ａｄｄｒｅｓｓ
Ｓｔｒ。The limiter circuit 3 includes diode-connected MOS transistors arranged in antiparallel (parallel in opposite directions), and corresponds to both rise and fall of v ssm. Usually, this limiter voltage is 0.7V to 1V. Also, a limiter 4 is similarly installed on the VCC side. However, the voltage fluctuation on the VCC side is Vss
Since the influence is smaller than that on the Vce side (■5. side has a large influence because it is used as a ground potential and the voltage reference in various parts of the circuit), the limiter 4 on the Vce side can be omitted. The input of this circuit is RA S (Rosy Address
Str.
ｂｅ Ｂａｒ）である。be Bar).
第４図は別の実施例である。ここではＢ１ＣＭＯＳタイ
プの論理回路を例にしている。出力は並列ｎビットであ
る。電圧リミ・ンタ３，４はダイオード（ダイオード接
続した）＼イボーラトランジスタ）を用いているので、
ここでの降下電圧は約０，６５■である。FIG. 4 shows another embodiment. Here, a B1CMOS type logic circuit is taken as an example. The output is n bits in parallel. Voltage limiters 3 and 4 use diodes (diode-connected \Ibora transistors), so
The voltage drop here is approximately 0.65 cm.
以上説明したように、本発明によって出力ノマ・ノファ
回路が高速動作したときに接地配線（ＬＳＩチップから
ボンディングワイヤを介しプリント板上の配線を含む）
に乗る雑音電圧が生じてもＬＳＩは誤動作しにくくなっ
た。このため、出力波形の立上りを鈍（する等の方法で
瞬時電流変化分を少なくしていたが、この必要が減った
。もしこのような対策を行うとしても従来よりも流し得
る電流出力は大きくできる。As explained above, according to the present invention, when the output noma-nofa circuit operates at high speed, the ground wiring (including the wiring on the printed board from the LSI chip via the bonding wire)
LSIs are less likely to malfunction even if noise voltages occur. For this reason, the instantaneous current change was reduced by methods such as making the rise of the output waveform blunt, but this is no longer necessary. Even if such measures were taken, the current output that could be passed would be larger than before. can.
このため、出力波形の立上り立下りが速くなりメモリで
はアクセス時間が速（なるのに等しシ）、。Therefore, the rising and falling edges of the output waveform become faster, and the memory access time becomes faster.
論理回路では出力波形を最大限高速化できるので動作ク
ロック周波数を高くすることができる。In logic circuits, the output waveform can be made as fast as possible, so the operating clock frequency can be increased.
第１図は本発明の原理図、
第２図は動作説明用の波形図、
第３図および第４図は本発明の実施例１，２を示すブロ
ック図、
第５図および第６図は従来例１．２の説明図である。
第１図で！、とｌｘ、１２３と１４は独立した電源配線
、３．４は電圧リミッタ素子または回路である。Fig. 1 is a principle diagram of the present invention, Fig. 2 is a waveform diagram for explaining operation, Figs. 3 and 4 are block diagrams showing embodiments 1 and 2 of the present invention, Figs. 5 and 6 are FIG. 2 is an explanatory diagram of conventional example 1.2. In Figure 1! , and lx, 123 and 14 are independent power supply wirings, and 3.4 is a voltage limiter element or circuit.
Claims (1)
半導体集積回路において、 該複数個の電源配線（ｌ＿１、ｌ＿３）間を、電圧リミ
ッタ素子または電圧リミッタ回路（３）で接続したこと
を特徴とする半導体集積回路。 ２、外部から信号を受取る回路を主として含む第１の回
路ブロック（１）と、外部へ信号を出力する回路を主と
して含む第２の回路ブロック（２）の各電源配線（ｌ＿
１とｌ＿２、ｌ＿３とｌ＿４）を、半導体チップ上では
独立した外部からの給電部分（Ｖ＿Ｓ＿Ｓ＿ＡとＶ＿Ｃ
＿Ｃ＿Ａ、Ｖ＿Ｓ＿Ｓ＿Ｂ、とＶ＿Ｃ＿Ｃ＿Ｂ）を有す
る独立配線とした半導体集積回路において、 該独立した配線間を、電圧リミッタ素子又は電圧リミッ
タ回路（３、４）で接続したことを特徴とする半導体集
積回路。 ３、電圧リミッタ素子が、逆並列接続のダイオードある
いはダイオード接続したバイポーラまたはＭＯＳトラン
ジスタであることを特徴とする請求項１または２記載の
半導体集積回路。[Claims] 1. In a semiconductor integrated circuit having a plurality of independent power supply wirings in a semiconductor chip, a voltage limiter element or a voltage limiter circuit (3) is connected between the plurality of power supply wirings (l_1, l_3). A semiconductor integrated circuit characterized by being connected. 2. Each power supply wiring (l_
1 and l_2, l_3 and l_4) are connected to independent external power supply parts (V_S_S_A and V_C
_C_A, V_S_S_B, and V_C_C_B), wherein the independent wirings are connected by a voltage limiter element or a voltage limiter circuit (3, 4). 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the voltage limiter element is an anti-parallel connected diode or a diode-connected bipolar or MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2107849A JPH046868A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2107849A JPH046868A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046868A true JPH046868A (en) | 1992-01-10 |
Family
ID=14469621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2107849A Pending JPH046868A (en) | 1990-04-24 | 1990-04-24 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046868A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004193475A (en) * | 2002-12-13 | 2004-07-08 | Ricoh Co Ltd | Power supply ic and communication apparatus employing power supply ic |
| JP2009124672A (en) * | 2007-11-12 | 2009-06-04 | Hynix Semiconductor Inc | Semiconductor integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239877A (en) * | 1988-03-18 | 1989-09-25 | Sharp Corp | Structure for electrostatic measure of integrated circuit |
-
1990
- 1990-04-24 JP JP2107849A patent/JPH046868A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239877A (en) * | 1988-03-18 | 1989-09-25 | Sharp Corp | Structure for electrostatic measure of integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004193475A (en) * | 2002-12-13 | 2004-07-08 | Ricoh Co Ltd | Power supply ic and communication apparatus employing power supply ic |
| JP4499985B2 (en) * | 2002-12-13 | 2010-07-14 | 株式会社リコー | Power supply IC and communication device using the power supply IC |
| US7856253B2 (en) | 2002-12-13 | 2010-12-21 | Ricoh Company, Ltd. | Power supply IC having switching regulator and series regulator |
| JP2009124672A (en) * | 2007-11-12 | 2009-06-04 | Hynix Semiconductor Inc | Semiconductor integrated circuit |
| JP2013066232A (en) * | 2007-11-12 | 2013-04-11 | Sk Hynix Inc | Semiconductor integrated circuit |
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