JPH046857A - Ultraviolet-erasable memory integrated circuit and manufacture thereof - Google Patents
Ultraviolet-erasable memory integrated circuit and manufacture thereofInfo
- Publication number
- JPH046857A JPH046857A JP2108381A JP10838190A JPH046857A JP H046857 A JPH046857 A JP H046857A JP 2108381 A JP2108381 A JP 2108381A JP 10838190 A JP10838190 A JP 10838190A JP H046857 A JPH046857 A JP H046857A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- cap
- point glass
- high melting
- alumina
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000011521 glass Substances 0.000 claims abstract description 63
- 238000002844 melting Methods 0.000 claims abstract description 61
- 230000008018 melting Effects 0.000 claims abstract description 58
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000919 ceramic Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 7
- 238000010304 firing Methods 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 3
- 238000002834 transmittance Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はメモリ素子（以下、ＩＣチップという）が透光
性アルミナキャップにより封止されたメモリカード及び
Ｉ Ｃ（Ｉｎｔｅｇｒａｔｅｄ Ｃ１ｒｃｕｉｔ）カー
ド等の薄型メモリ集積回路に好適の紫外線消去型メモリ
集積回路及びその製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to thin devices such as memory cards and IC (Integrated C1Rcuit) cards in which a memory element (hereinafter referred to as an IC chip) is sealed with a translucent alumina cap. The present invention relates to an ultraviolet erasable memory integrated circuit suitable for memory integrated circuits and a method for manufacturing the same.
［従来の技術］
第３図は従来の紫外線消去型メモリ集積回路を示す断面
図である。[Prior Art] FIG. 3 is a sectional view showing a conventional ultraviolet erasable memory integrated circuit.
セラミック基板１２にはその上面中央部に凹所が設けら
れており、■ｃチップ１１は電極形成面を上方に向けて
ポリイミド樹脂等の固着部１３によりこの凹所に固着さ
れている。A recess is provided in the center of the upper surface of the ceramic substrate 12, and the chip 11 is fixed in this recess with an adhesive part 13 made of polyimide resin or the like with the electrode forming surface facing upward.
セラミック基板１２の上面縁部にはリードフレーム１５
が低融点硝子部１７により固着されている。このリード
フレーム１５の前記凹所側の先端部にはボンディングワ
イヤ１４が接合されており、リードフレーム１５はこの
ボンディングワイヤ１４を介してＩＣチップ１１上の電
極に電気的に接続されている。また、リードフレーム１
５の他方の端部側はセラミック基板１２の側方に導出し
ており、先端部がセラミック基板１２の下面と路間−面
上に位置するように折り曲げられている・セラミック基
板１２の上方には透光性アルミナキャップ１６が配置さ
れており、このアルミナキャップ１６は低融点硝子部１
７によりセラミック基板１２に接合されている。A lead frame 15 is attached to the upper edge of the ceramic substrate 12.
is fixed by a low melting point glass portion 17. A bonding wire 14 is bonded to the tip of the lead frame 15 on the recess side, and the lead frame 15 is electrically connected to an electrode on the IC chip 11 via the bonding wire 14. Also, lead frame 1
The other end side of 5 is led out to the side of the ceramic substrate 12, and is bent so that the tip is located on the lower surface of the ceramic substrate 12 and the surface between the paths. A translucent alumina cap 16 is arranged, and this alumina cap 16 is connected to the low melting point glass part 1.
7 to the ceramic substrate 12.
このようにして、ＩＣチップ１１はセラミック基板１２
及び透光性アルミナキャップ１６と低融点硝子部１７と
により気密的に封止されている。In this way, the IC chip 11 is attached to the ceramic substrate 12.
It is hermetically sealed by a translucent alumina cap 16 and a low melting point glass part 17.
紫外線消去型メモリ集積回路においては、キャップ１２
を介して紫外線をＩＣチップ１１に照射することにより
、ＩＣチップ１１に記憶させたデータを消去することが
できる。In the ultraviolet erasable memory integrated circuit, the cap 12
The data stored in the IC chip 11 can be erased by irradiating the IC chip 11 with ultraviolet rays through the UV light.
［発明が解決しようとする課題］
しかしながら、上述した従来の紫外線消去型メモリ集積
回路においては、透光性アルミナキャップ１６が低融点
硝子部１７との封止界面から剥離しやすいという欠点が
ある。つまり、透光性アルミナキャップ１６は紫外線を
透過させる必要上、上面及び下面が平滑に形成されてい
るため、低融点硝子部１７との密着性が低く、剥離しや
すい。[Problems to be Solved by the Invention] However, the conventional ultraviolet erasable memory integrated circuit described above has a drawback in that the light-transmitting alumina cap 16 easily peels off from the sealing interface with the low melting point glass portion 17. That is, since the translucent alumina cap 16 needs to transmit ultraviolet rays and has a smooth upper and lower surface, its adhesion to the low melting point glass portion 17 is low and it is easily peeled off.
アルミナキャップ１６と低融点硝子部１７との密着性を
向上させるために、アルミナキャップ１６の表面全体を
粗面化することも考えられるが、そうすると紫外線がキ
ャップ表面で散乱又は屈折するため、アルミナキャップ
１６の紫外線透過率が著しく減少する。これにより、Ｉ
Ｃチップ１１に記憶させたデータを消去することができ
なくなったり、又は消去時間が長くなるという新たな問
題点が発生する。In order to improve the adhesion between the alumina cap 16 and the low-melting point glass part 17, it is possible to roughen the entire surface of the alumina cap 16, but if this is done, ultraviolet rays will be scattered or refracted on the cap surface, so the alumina cap The UV transmittance of No. 16 is significantly reduced. This allows I
A new problem occurs in that the data stored in the C chip 11 cannot be erased or the erasing time becomes longer.
本発明はかかる問題点に鑑みてなされたものであって、
アルミナキャップの剥離を回避することができると共に
、アルミナキャップの紫外線透過率が高く、信頼性が高
い紫外線消去型メモリ集積回路及びその製造方法を提供
することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an ultraviolet erasable memory integrated circuit that can avoid peeling of an alumina cap, has a high ultraviolet transmittance of the alumina cap, and is highly reliable, and a method for manufacturing the same.
［課題を解決するための手段］
本発明に係る紫外線消去型メモリ集積回路は、メモリ素
子と、このメモリ素子が搭載されたセラミック基板と、
透光性アルミナキャップと、このキャップを前記基板に
接着する低融点硝子部と、この低融点硝子部と前記キャ
ップとの間に介在する高融点硝子層とを有することを特
徴とする。[Means for Solving the Problems] An ultraviolet erasable memory integrated circuit according to the present invention includes a memory element, a ceramic substrate on which the memory element is mounted,
It is characterized by comprising a translucent alumina cap, a low melting point glass portion that adheres the cap to the substrate, and a high melting point glass layer interposed between the low melting point glass portion and the cap.
本発明に係る紫外線消去型メモリ集積回路の製造方法は
、透光性アルミナキャップの一方の面の縁部に沿って高
融点硝子を付着させる工程と、この高融点硝子を焼成す
ることにより高融点硝子層を形成する工程と、メモリ素
子が搭載されたセラミック基板に前記キャップを前記高
融点硝子層の所定部分とセラミック基板との間に低融点
硝子を介在させて接合する工程とを有することを特徴と
する。The method of manufacturing an ultraviolet erasable memory integrated circuit according to the present invention includes the steps of attaching high melting point glass along the edge of one side of a translucent alumina cap, and baking the high melting point glass to obtain a high melting point glass. A step of forming a glass layer; and a step of bonding the cap to a ceramic substrate on which a memory element is mounted by interposing a low melting point glass between a predetermined portion of the high melting point glass layer and the ceramic substrate. Features.
［作用コ
本発明においては、透光性アルミナキャップとセラミッ
ク基板とが低融点硝子部及び高融点硝子層により接合さ
れている。高融点硝子は透光性アルミナに高温で接合す
ることにより、強固な接着性が得られる。また、高融点
硝子と低融点硝子とは硝子同士であるため、良好な接着
性が得られる。[Function] In the present invention, the translucent alumina cap and the ceramic substrate are joined by a low melting point glass portion and a high melting point glass layer. High melting point glass can be bonded to translucent alumina at high temperatures to provide strong adhesion. Further, since the high melting point glass and the low melting point glass are glasses, good adhesion can be obtained.
従って、本発明においては、透光性アルミナキャップを
セラミック基板に低融点硝子で接合する場合に、透光性
アルミナキャップと低融点硝子部との間に高融点硝子層
を介在させる。これにより、アルミナキャップと基板と
の密着が従来に比して著しく向上し、キャップの剥離を
回避することができる。この場合に、アルミナキャップ
の面は平滑で良いため、紫外線透光率が高い。Therefore, in the present invention, when a translucent alumina cap is bonded to a ceramic substrate using a low melting point glass, a high melting point glass layer is interposed between the translucent alumina cap and the low melting point glass portion. As a result, the adhesion between the alumina cap and the substrate is significantly improved compared to the conventional method, and peeling of the cap can be avoided. In this case, the surface of the alumina cap can be smooth and has high ultraviolet transmittance.
また、本発明方法においては、予め透光性アルミナキャ
ップの一方の面の縁部に高融点硝子を付着させ、焼成す
ることにより高融点硝子層を形成する。そして、この高
融点硝子層を有するアルミナキャップをメモリ素子が搭
載されているセラミック基板に低融点硝子で接合する。Further, in the method of the present invention, a high melting point glass layer is formed by attaching high melting point glass to the edge of one side of the translucent alumina cap in advance and firing it. Then, the alumina cap having the high melting point glass layer is bonded to the ceramic substrate on which the memory element is mounted using low melting point glass.
従って、メモリ素子を高温に曝す必要がなく、アルミナ
キャップと基板とを強固に接合させることができる。Therefore, there is no need to expose the memory element to high temperatures, and the alumina cap and the substrate can be firmly bonded.
［実施例コ
次に、本発明の実施例について添付の図面を参照して説
明する。[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の第１の実施例に係る紫外線消去型メモ
リ集積回路を示す断面図である。FIG. 1 is a sectional view showing an ultraviolet erasable memory integrated circuit according to a first embodiment of the present invention.
本実施例が従来と異なる点はアルミナキャップ１６と低
融点硝子部１７との間に高融点硝子層１９が設けられて
いることにあり、その他の構造は基本的には従来と同様
であるので、第１図において第３図と同一物には同一符
号を付してその部分の詳しい説明は省略する。This embodiment differs from the conventional one in that a high melting point glass layer 19 is provided between the alumina cap 16 and the low melting point glass part 17, and the other structure is basically the same as the conventional one. , Components in FIG. 1 that are the same as those in FIG. 3 are given the same reference numerals, and detailed explanations of those portions will be omitted.
本実施例においては、上述の如く、低融点硝子部１７と
透光性アルミナキャ・ツブ１６との間に高融点硝子層１
９が形成されている。高融点硝子は透光性アルミナキャ
ップ１６に高温で接合するため、低融点硝子に比して透
光性アルミナとの接合力が高いと共に、同種の低融点硝
子に対しても高い接合力を有している。このため、アル
ミナキャップ１６の剥離を防止することができる。また
、アルミナキャップ１６に粗面化等の処理を施す必要が
ないため、アルミナキャップ１６の紫外線透光率は、従
来と同様に高い。In this embodiment, as described above, a high melting point glass layer 1 is provided between the low melting point glass portion 17 and the translucent alumina cap 16.
9 is formed. Since high melting point glass is bonded to the translucent alumina cap 16 at high temperature, it has a higher bonding strength with translucent alumina than low melting point glass, and also has a higher bonding strength with the same type of low melting point glass. are doing. Therefore, peeling of the alumina cap 16 can be prevented. Further, since it is not necessary to perform surface roughening or other treatment on the alumina cap 16, the ultraviolet transmittance of the alumina cap 16 is as high as in the conventional case.
次に、本実施例に係る紫外線消去型メモリ集積回路の製
造方法について説明する。Next, a method of manufacturing the ultraviolet erasable memory integrated circuit according to this embodiment will be explained.
先ず、ポリイミド樹脂等の固着部１３により、セラミッ
ク基板１２の上面の凹所にＩＣチ・ツブ１１を固着する
。その後、セラミ、ンク基板１２の上面縁部に、低融点
硝子によりリードフレーム１５を固着する。そして、こ
のリードフレーム１５の凹所側先端部とＩＣチップ１１
上に形成された電極とをボンディングワイヤ１４により
電気的に接続する。First, the IC chip 11 is fixed in a recess on the upper surface of the ceramic substrate 12 using the fixing part 13 made of polyimide resin or the like. Thereafter, the lead frame 15 is fixed to the upper edge of the ceramic substrate 12 using low melting point glass. Then, the leading end of the lead frame 15 on the recess side and the IC chip 11 are connected to each other.
The electrode formed above is electrically connected by a bonding wire 14.
一方、透光性アルミナキャップ１６の下面縁部にスクリ
ーン印刷により高融点硝子を被着し、その後高温で焼成
して高融点硝子層１９を形成する。On the other hand, high melting point glass is applied to the lower edge of the translucent alumina cap 16 by screen printing, and then fired at a high temperature to form a high melting point glass layer 19.
次いで、このアルミナキャップ１６をセラミ・ツク基板
１２上に低融点硝子により接合する。これにより、上述
の実施例に係る紫外線消去型メモリ集積回路を製造でき
る。Next, this alumina cap 16 is bonded onto the ceramic substrate 12 using low melting point glass. Thereby, the ultraviolet erasable memory integrated circuit according to the above embodiment can be manufactured.
第２図は本発明の第２の実施例に係る紫外線消去型メモ
リ集積回路を示す断面図である。FIG. 2 is a sectional view showing an ultraviolet erasable memory integrated circuit according to a second embodiment of the present invention.
本実施例が第１の実施例と異なる点はＩＣチップ１１の
直上域を除くアルミナキャップ１６の底面全体に高融点
硝子層１９ａが設けられていることにあり、その他の構
造は基本的には第１の実施例と同様であるので、第２図
において第１図と同一物には同一符号を付してその詳し
い説明は省略する。This embodiment differs from the first embodiment in that a high melting point glass layer 19a is provided on the entire bottom surface of the alumina cap 16 except for the area directly above the IC chip 11, and the other structure is basically the same. Since it is similar to the first embodiment, the same components in FIG. 2 as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.
本実施例においては、アルミナキャップ１６の下面のＩ
Ｃチップ１１の直上域を除く領域に、広く高融点硝子層
１９ａが形成されている。このため、第１の実施例と同
様の効果を得ることができるのに加えて、アルミナキャ
ップ接合時に低融点硝子部１７の封止幅にバラツキが発
生しても透光性アルミナキャップ１６の接合強度を確保
することができ、ＩＣチップ１１を確実に封止すること
ができる。In this embodiment, the I of the lower surface of the alumina cap 16 is
A high melting point glass layer 19a is widely formed in the area excluding the area immediately above the C chip 11. Therefore, in addition to being able to obtain the same effect as in the first embodiment, even if variations occur in the sealing width of the low melting point glass portion 17 when bonding the alumina cap, the translucent alumina cap 16 can be bonded. Strength can be ensured, and the IC chip 11 can be reliably sealed.
［発明の効果］
以上説明したように本発明によれば、透光性アルミナキ
ャップとセラミック基板とが高融点硝子層及び低融点硝
子部を介して接合されているから、本発明に係る紫外線
消去型メモリ集積回路はアルミナキャップと基板との接
合が強固であり、アルミナキャップの剥離を防止でき、
信頼性が高い。[Effects of the Invention] As explained above, according to the present invention, since the translucent alumina cap and the ceramic substrate are bonded via the high melting point glass layer and the low melting point glass portion, the ultraviolet ray erasure according to the present invention type memory integrated circuit has a strong bond between the alumina cap and the substrate, which prevents the alumina cap from peeling off.
Highly reliable.
そして、アルミナキャップの面は平滑でよいため、紫外
線透光率も高い。Furthermore, since the surface of the alumina cap may be smooth, it has a high ultraviolet transmittance.
また、本発明方法によれば、予め透光性アルミナキャッ
プに高融点硝子層を形成しておき、このアルミナキャッ
プをメモリ素子が搭載されている基板に低融点硝子で接
合するから、メモリ素子を高温に曝す必要がなく、上述
の信頼性が高い紫外線消去型メモリ集積回路を容易に製
造することができる。Furthermore, according to the method of the present invention, a high melting point glass layer is formed on a translucent alumina cap in advance, and this alumina cap is bonded to a substrate on which a memory element is mounted using a low melting point glass. There is no need to expose to high temperatures, and the highly reliable ultraviolet erasable memory integrated circuit described above can be easily manufactured.
第１図は本発明の第１の実施例に係る紫外線消去型メモ
リ集積回路を示す断面図、第２図は本発明の第２の実施
例に係る紫外線消去型メモリ集積回路を示す断面図、第
３図は従来の紫外線消去型メモリ集積回路を示す断面図
である。
１１；ＩＣチップ、１２；セラミック基板、１３；固着
部、１４；ボンディングワイヤ、１５；リードフレーム
、１６；アルミナキャップ、１７；低融点硝子部、１９
，１９ａ；高融点硝子層比願人 日本電気株式会社FIG. 1 is a cross-sectional view showing an ultraviolet-erasable memory integrated circuit according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an ultraviolet-erasable memory integrated circuit according to a second embodiment of the present invention. FIG. 3 is a sectional view showing a conventional ultraviolet erasable memory integrated circuit. 11; IC chip, 12; ceramic substrate, 13; fixed part, 14; bonding wire, 15; lead frame, 16; alumina cap, 17; low melting point glass part, 19
, 19a; High melting point glass layer applicant NEC Corporation
Claims (2)
ミック基板と、透光性アルミナキャップと、このキャッ
プを前記基板に接着する低融点硝子部と、この低融点硝
子部と前記キャップとの間に介在する高融点硝子層とを
有することを特徴とする紫外線消去型メモリ集積回路。(1) A memory element, a ceramic substrate on which the memory element is mounted, a translucent alumina cap, a low-melting glass part that adheres the cap to the substrate, and a space between the low-melting glass part and the cap. and a high melting point glass layer interposed therein.
て高融点硝子を付着させる工程と、この高融点硝子を焼
成することにより高融点硝子層を形成する工程と、メモ
リ素子が搭載されたセラミック基板に前記キャップを前
記高融点硝子層の所定部分とセラミック基板との間に低
融点硝子を介在させて接合する工程とを有することを特
徴とする紫外線消去型メモリ集積回路の製造方法。(2) The process of attaching high melting point glass along the edge of one side of the translucent alumina cap, the process of forming a high melting point glass layer by firing this high melting point glass, and mounting the memory element. A method for manufacturing an ultraviolet erasable memory integrated circuit, comprising the step of: bonding the cap to the ceramic substrate with a low melting point glass interposed between a predetermined portion of the high melting point glass layer and the ceramic substrate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108381A JPH046857A (en) | 1990-04-24 | 1990-04-24 | Ultraviolet-erasable memory integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108381A JPH046857A (en) | 1990-04-24 | 1990-04-24 | Ultraviolet-erasable memory integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046857A true JPH046857A (en) | 1992-01-10 |
Family
ID=14483331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2108381A Pending JPH046857A (en) | 1990-04-24 | 1990-04-24 | Ultraviolet-erasable memory integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046857A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302852A (en) * | 1992-02-27 | 1994-04-12 | Nec Corporation | Semiconductor device package having a low profile structure and high strength |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61168247A (en) * | 1985-01-19 | 1986-07-29 | Nec Kansai Ltd | Ceramic package |
| JPH01130548A (en) * | 1987-11-17 | 1989-05-23 | Mitsubishi Electric Corp | Semiconductor device |
-
1990
- 1990-04-24 JP JP2108381A patent/JPH046857A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61168247A (en) * | 1985-01-19 | 1986-07-29 | Nec Kansai Ltd | Ceramic package |
| JPH01130548A (en) * | 1987-11-17 | 1989-05-23 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302852A (en) * | 1992-02-27 | 1994-04-12 | Nec Corporation | Semiconductor device package having a low profile structure and high strength |
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