JPH0466816U - - Google Patents

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案クロツク遷移検出回路の一つの
実施例を示す回路図、第２図は第１図に示すクロ
ツク遷移検出回路の動作を示すタイムチヤート、
第３図はクロツク遷移検出回路が使用される回路
の一例である同期型メモリの回路ブロツク図、第
４図はクロツク遷移検出回路の従来例を示す回路
図、第５図は第４図に示すクロツク遷移検出回路
の動作を示すタイムチヤートである。 符号の説明、１……遅延回路、２ａ……論理ゲ
ート（ＥＸ−ＮＯＲ）、３……分周回路。 FIG. 1 is a circuit diagram showing one embodiment of the clock transition detection circuit of the present invention, and FIG. 2 is a time chart showing the operation of the clock transition detection circuit shown in FIG. 1.
Figure 3 is a circuit block diagram of a synchronous memory which is an example of a circuit in which a clock transition detection circuit is used, Figure 4 is a circuit diagram showing a conventional example of a clock transition detection circuit, and Figure 5 is shown in Figure 4. 3 is a time chart showing the operation of a clock transition detection circuit. Explanation of symbols: 1... Delay circuit, 2a... Logic gate (EX-NOR), 3... Frequency divider circuit.

Claims (1)

【実用新案登録請求の範囲】 被検出クロツクパルスを1/2分周する分周回路
を設け、該分周回路の出力パルスの遅延量を異な
らせた２つのパルスを１つの論理ゲートに入力し
て該論理ゲートから検出パルスを得るようにした ことを特徴とするクロツク遷移検出回路。[Claims for Utility Model Registration] A frequency dividing circuit that divides the frequency of the detected clock pulse by 1/2 is provided, and two pulses with different delay amounts of the output pulses of the frequency dividing circuit are input to one logic gate. A clock transition detection circuit characterized in that a detection pulse is obtained from the logic gate.