JPH0463628B2 - - Google Patents

Info

Publication number
JPH0463628B2
JPH0463628B2 JP57132365A JP13236582A JPH0463628B2 JP H0463628 B2 JPH0463628 B2 JP H0463628B2 JP 57132365 A JP57132365 A JP 57132365A JP 13236582 A JP13236582 A JP 13236582A JP H0463628 B2 JPH0463628 B2 JP H0463628B2
Authority
JP
Japan
Prior art keywords
winding
shielding layer
primary
electrostatic shielding
primary winding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57132365A
Other languages
Japanese (ja)
Other versions
JPS5925579A (en
Inventor
Seiichi Yamano
Haruo Ogiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13236582A priority Critical patent/JPS5925579A/en
Priority to US06/515,754 priority patent/US4507721A/en
Priority to DE8383107388T priority patent/DE3374745D1/en
Priority to EP83107388A priority patent/EP0100098B1/en
Publication of JPS5925579A publication Critical patent/JPS5925579A/en
Publication of JPH0463628B2 publication Critical patent/JPH0463628B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 この発明は直流電力をスイツチングしてトラン
スの１次巻線へ供給し、そのトランスの２次巻線
の出力を整流平滑して直流出力を得るDC−DC変
換回路に関し、特に入出力間を高インピーダンス
で分離し、しかも同相モードスイツチング雑音の
発生が少ない回路に係わる。[Detailed Description of the Invention] This invention relates to a DC-DC conversion circuit that switches DC power and supplies it to the primary winding of a transformer, rectifies and smoothes the output of the secondary winding of the transformer, and obtains a DC output. In particular, it relates to a circuit that separates input and output with high impedance and generates little common-mode switching noise.

＜背景＞ この種のDC−DC変換回路は例えばデイジタル
加入者線伝送方式における加入者宅内側に設置さ
れるデイジタル回線終端装置の電源として用いら
れる。即ち第１図に示すように、加入者宅内側に
設置されるデイジタル回線終端装置１１は一般に
局からの遠方給電によつて動作するように構成さ
れ、デイジタル回線終端装置１１に接続された平
衡形ケーブルの加入者線１２上には、デイジタル
信号と給電直流電流とが重畳されてある。加入者
線１２の他端は局内に引き込まれ、局内側のデイ
ジタル回線終端装置（図示せず）に接続される。
加入者線１２上のデイジタル信号は装置１１との
接続点１３、トランス１４を介してパルス伝送回
路１５に入力される。パルス伝送回路１５は等化
増幅回路、パルス送信回路などから構成される。
加入者線１２上の給電直流電流は接続点１３、電
力分離フイルタ１６ａ，１６ｂを介してDC−DC
変換回路１７の１次側１８ａ，１８ｂ間に入力さ
れ、これら１次側１８ａ，１８ｂ間には例えば直
流電圧30Vが印加される。DC−DC変換回路１７
ではDC−DC変換を行い、DC−DC回路１７の２
次側１９ａ，１９ｂ間には、例えば直流電圧5V
を発生する。デイジタル回線終端装置１１の主要
部あるいは全体はDC−DC変換回路１７の２次側
１９ａ，１９ｂの出力によつて動作する。接続点
１３及びフイルタ１６ａ，１６ｂの接続点とトラ
ンス１４との間に挿入された直流阻止コンデンサ
２１はトランス１４に給電直流電流を流さないた
めに設けている。電力分離フイルタ１６ａ，１６
ｂは、直流低インピーダンス、交流高インピーダ
ンスとなるように例えばコイルで構成されてい
る。これはDC−DC変換回路１７の１次側１８
ａ，１８ｂ間の交流インピーダンスが低いため、
デイジタル信号を短絡することを避けるためであ
る。<Background> This type of DC-DC conversion circuit is used, for example, as a power source for a digital line termination device installed inside a subscriber's premises in a digital subscriber line transmission system. That is, as shown in FIG. 1, the digital line termination device 11 installed inside the subscriber's premises is generally configured to operate by distant power supply from the station, and the balanced type connected to the digital line termination device 11 is On the subscriber line 12 of the cable, a digital signal and a feeding direct current are superimposed. The other end of the subscriber line 12 is led into the office and connected to a digital line termination device (not shown) inside the office.
A digital signal on the subscriber line 12 is input to a pulse transmission circuit 15 via a connection point 13 with the device 11 and a transformer 14. The pulse transmission circuit 15 includes an equalization amplifier circuit, a pulse transmission circuit, and the like.
The feed DC current on the subscriber line 12 is DC-DC through the connection point 13 and the power separation filters 16a, 16b.
The voltage is input between the primary sides 18a and 18b of the conversion circuit 17, and a DC voltage of 30 V, for example, is applied between the primary sides 18a and 18b. DC-DC conversion circuit 17
Now perform DC-DC conversion and convert DC-DC circuit 17, 2.
For example, a DC voltage of 5V is applied between the next side 19a and 19b.
occurs. The main part or the whole of the digital line termination device 11 is operated by the outputs of the secondary sides 19a and 19b of the DC-DC conversion circuit 17. A DC blocking capacitor 21 inserted between the connection point 13 and the connection point between the filters 16a and 16b and the transformer 14 is provided to prevent the supply DC current from flowing through the transformer 14. Power separation filter 16a, 16
b is composed of, for example, a coil so as to have low DC impedance and high AC impedance. This is the primary side 18 of the DC-DC conversion circuit 17.
Since the AC impedance between a and 18b is low,
This is to avoid short-circuiting digital signals.

さて、以上の構成のデイジタル回線終端装置１
１の電源であるDC−DC変換回路１７に、従来構
成のDC−DC変換回路を適用する場合、以下の欠
点が生じる。 Now, the digital line termination device 1 with the above configuration.
When a conventionally configured DC-DC converter circuit is applied to the DC-DC converter circuit 17, which is the power source of No. 1, the following drawbacks occur.

(a) DC−DC変換回路１７の１次側と２次側との
間、すなわち、１次側１８ａ及び２次側１９ａ
間、或は１次側１８ｂ及び２次側１９ｂ間に
DC−DC変換回路１７のスイツチングにともな
うスイツチング雑音v1、いわゆる同相モードス
イツチング雑音が発生する。この同相モードス
イツチング雑音は、加入者線１２及びデイジタ
ル回線終端装置１１などによつて決まる不平衡
減衰量に応じて差動モード雑音に変換され、ト
ランス１４の２次側２２ａ，２２ｂ間に廻り込
み、デイジタル信号の符号誤りの原因となる。
このため同相モードスイツチング雑音の発生を
充分に小さくする必要があるが、従来のDC−
DC変換回路ではこれを満足させることができ
なかつた。(a) Between the primary side and the secondary side of the DC-DC conversion circuit 17, that is, the primary side 18a and the secondary side 19a
or between the primary side 18b and the secondary side 19b.
Switching noise v 1 , so-called common mode switching noise, occurs as the DC-DC conversion circuit 17 switches. This common mode switching noise is converted into differential mode noise according to the amount of unbalanced attenuation determined by the subscriber line 12, digital line termination device 11, etc. This can cause code errors in digital signals.
For this reason, it is necessary to sufficiently reduce the generation of common-mode switching noise, but conventional DC-
It was not possible to satisfy this requirement with a DC conversion circuit.

(b) 加入者線１２上には、アナログ電話回線から
のインパルス性雑音等の各種縦雑音が誘導さ
れ、デイジタル信号の符号誤りの原因となるた
め、デイジタル回線終端装置１１の不平衡減衰
量は充分に高くする必要がある。前記(a)項に記
載した欠点を除去するため、第２図に示すよう
にDC−DC変換回路１７のスイツチング周波数
で充分に低インピーダンスの外付コンデンサ２
３を、１次側１８ａ及び２次側１９ａ間（ある
いは１次側１８ｂ及び２次側１９ｂ間）に接続
することにより前記同相モードスイツチング雑
音を抑圧しているものがある。しかし、このよ
うな構成とし、かつDC−DC変換回路１７の２
次側１９あるいは１９ｂを低インピーダンスで
アースに接続する場合、電力分離フイルタ１６
ａ（あるいは１６ｂ）用のコイルと外付コンデ
ンサ２３とから縦回路に共振点を形成し、この
共振点においてデイジタル回線終端回路１１の
不平衡減衰量が極度に劣化し符号誤りを生じ
る。このため前記共振点をパルス伝送帯帯域よ
り充分に高い周波数とする必要があり、これに
は外付コンデンサ２３を除去し、DC−DC変換
回路１７の１次側１８ａ，１８ｂと２次側１９
ａ，１９ｂとをトランス１４のストレー容量程
度の高インピーダンスで分離することが必要で
ある。しかし、このようにすると従来の回路構
成では前記(a)項に記載した欠点が生じる。(b) Various types of vertical noise such as impulsive noise from the analog telephone line are induced on the subscriber line 12 and cause code errors in the digital signal, so the unbalanced attenuation of the digital line termination device 11 is It needs to be high enough. In order to eliminate the drawback described in the above item (a), as shown in FIG.
Some devices suppress the common-mode switching noise by connecting 3 between the primary side 18a and the secondary side 19a (or between the primary side 18b and the secondary side 19b). However, with such a configuration and the second part of the DC-DC conversion circuit 17.
If the next side 19 or 19b is connected to earth with low impedance, the power isolation filter 16
A resonance point is formed in the vertical circuit by the coil for a (or 16b) and the external capacitor 23, and at this resonance point, the unbalanced attenuation of the digital line termination circuit 11 is extremely degraded, causing a code error. For this reason, it is necessary to set the resonance point to a frequency sufficiently higher than the pulse transmission band, and for this purpose, the external capacitor 23 is removed and the primary sides 18a, 18b and secondary side 19 of the DC-DC conversion circuit 17 are
a and 19b must be separated by a high impedance comparable to the stray capacitance of the transformer 14. However, in this case, the conventional circuit configuration suffers from the drawbacks described in item (a) above.

以下これらの点について更に詳細に説明する。
第３図に従来のDC−DC変換回路の基本構成を示
す。直流電源２４から１次側１８ａ，１８ｂを通
じて入力された直流入力電圧E1はスイツチ素子
２５のオン／オフの繰返し動作（以下スイツチン
グと呼ぶ）により交番電圧（以下スイツチング電
圧と呼ぶ）に変換され、トランス２６の１次巻線
２７の両端２９，３１間にはスイツチング電圧e1
が生じる。このためトランス２６の２次巻線２８
の両端３２，３３間にはスイツチング電圧e2が誘
起される。このスイツチング電圧e2はダイオード
３４で半波整流され、出力コンデンサ３５で平滑
され、直流出力電圧E2が得られ、この直流出力
は２次側１９ａ，１９ｂを通じて負荷３６へ供給
される。なお１次巻線２７の両端２９，３１間に
誘起されるスイツチング電圧e1と、２次巻線２８
の両端３２，３３間に誘起されるスイツチング電
圧e2との比は、１次巻線２７と２次巻線２８との
巻線比により定まる。直流電源２４の両端間に入
力コンデンサ３７が接続され、またスイツチ素子
２５は例えばトランジスタであつて、このトラン
ジスタ２５は１次巻線２７と直列に挿入され、ト
ランジスタ２５のベース、エミツタ間に駆動回路
３８が接続されている。 These points will be explained in more detail below.
FIG. 3 shows the basic configuration of a conventional DC-DC conversion circuit. The DC input voltage E1 input from the DC power supply 24 through the primary sides 18a and 18b is converted into an alternating voltage (hereinafter referred to as switching voltage) by the repeated on/off operation (hereinafter referred to as switching) of the switch element 25, A switching voltage e 1 is applied between both ends 29 and 31 of the primary winding 27 of the transformer 26.
occurs. Therefore, the secondary winding 28 of the transformer 26
A switching voltage e 2 is induced between both ends 32 and 33 of . This switching voltage e2 is half-wave rectified by a diode 34 and smoothed by an output capacitor 35 to obtain a DC output voltage E2 , which is supplied to a load 36 through the secondary sides 19a and 19b. Note that the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 and the secondary winding 28
The ratio of the switching voltage e 2 induced between both ends 32 and 33 of 2 is determined by the winding ratio between the primary winding 27 and the secondary winding 28. An input capacitor 37 is connected between both ends of the DC power supply 24, and the switch element 25 is, for example, a transistor, this transistor 25 is inserted in series with the primary winding 27, and a drive circuit is connected between the base and emitter of the transistor 25. 38 are connected.

この第３図に示した従来のDC−DC変換回路で
は１次側−２次側間、すなわち１次側１８ａ、２
次側１９間に大きなスイツチング電圧が発生する
欠点があつた。これを同相モードスイツチング雑
音と呼び、以下第４図を用いて説明する。第４図
は第３図に示したDC−DC変換回路において、同
相モードスイツチング雑音の発生機構を交流成分
に着目して示したものである。第４図中の記号は
第３図に順じ、e1，e2，v1及びv2は任意の時点で
の各端子間のスイツチング電圧を、また矢印は各
電圧極性の相互関係を示す。スイツチ素子２５と
電源２４との接続点を１次側１８ｂ、ダイオード
３４と出力コンデンサ３５との接続点を２次側１
９ｂとしている。巻線端２９，３２間のコンデン
サ４２、巻線端３１，３３間のコンデンサ４３は
それぞれ１次巻線２７と２次巻線２８との間に分
布するストレー容量を集中定数回路で表わしたも
のである。スイツチ要素２５、１次巻線２７、入
力コンデンサ３７よりなる閉回路を閉路と名付
け、１次巻線２７、２次巻線２８、コンデンサ４
２，４３よりなる閉回路を閉路と、２次巻線２
８、ダイオード３４、出力コンデンサ３５よりな
る閉回路を閉路とそれぞれ呼ぶ。 In the conventional DC-DC conversion circuit shown in FIG. 3, between the primary side and the secondary side, that is, the primary side 18a,
There was a drawback that a large switching voltage was generated between the following sides 19. This is called common mode switching noise, and will be explained below using FIG. 4. FIG. 4 shows the generation mechanism of common mode switching noise in the DC-DC conversion circuit shown in FIG. 3, focusing on the alternating current component. The symbols in Figure 4 are the same as in Figure 3, e 1 , e 2 , v 1 and v 2 indicate the switching voltage between each terminal at any given time, and the arrows indicate the mutual relationship of each voltage polarity. . The connection point between the switch element 25 and the power supply 24 is the primary side 18b, and the connection point between the diode 34 and the output capacitor 35 is the secondary side 18b.
It is set as 9b. A capacitor 42 between the winding ends 29 and 32 and a capacitor 43 between the winding ends 31 and 33 represent the stray capacitance distributed between the primary winding 27 and the secondary winding 28 using lumped constant circuits. It is. A closed circuit consisting of the switch element 25, the primary winding 27, and the input capacitor 37 is called a closed circuit.
The closed circuit consisting of 2 and 43 is called a closed circuit, and the secondary winding 2
8, the diode 34, and the output capacitor 35 are each called a closed circuit.

第４図において、まず閉路に着目する。入力
コンデンサ３７はスイツチング周波数成分に対し
ては短絡（充分に低インピーダンス）であるから
その両端にはスイツチング電圧は発生しない。従
つてキルヒホツフの電圧側からスイツチ素子２５
の両端には１次巻線２７の両端２９，３１間に誘
起されるスイツチング電圧e1に等しい振幅のスイ
ツチング電圧が逆位相で発生する。次に閉路に
着目する。出力コンデンサ３５はスイツチング周
波数成分に対しては短絡であるから、その両端に
はスイツチング電圧は発生しない。したがつて、
キルヒホツフの電圧側からダイオード３４の両端
には、２次巻線２８の両端３２，３３間に誘起さ
れるスイツチング電圧e2に等しい振幅のスイツチ
ング電圧が逆位相で発生する。 In FIG. 4, first focus on the closed circuit. Since the input capacitor 37 is short-circuited (sufficiently low impedance) for the switching frequency component, no switching voltage is generated across it. Therefore, from the Kirchoff voltage side, the switch element 25
A switching voltage with an amplitude equal to the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 is generated at both ends of the primary winding 27 in opposite phases. Next, we will focus on closed circuits. Since the output capacitor 35 is short-circuited for the switching frequency component, no switching voltage is generated across it. Therefore,
A switching voltage with an amplitude equal to the switching voltage e 2 induced between the ends 32 and 33 of the secondary winding 28 is generated in opposite phase across the diode 34 from the Kirchoff voltage side.

次に閉路に着目する。通常コンデンサ４２，
４３の容量値はともに小さく、スイツチング周波
数を含む高周波域に亘り充分に高いインピーダン
スとなる。さて閉路において、コンデンサ４
２，４３の両端に発生するスイツチング電圧を
各々v1，v2とすると、キルヒホツフの電圧側か
ら、v1＋v2＝e1−e2となる関係を満たす。また電
圧v1とv2の比は各々のコンデンサ４２，４３の容
量値に反比例する。コンデンサ４２の両端に発生
するスイツチング電圧v1は同相モードスイツチン
グ雑音である。以下閉路部分の拡大図である第
５図を用いて説明する。第５図中の記号は第４図
に順ずる。コンデンサ４２，４３の容量値をC1，
C2とする。第５図から同相モードスイツチング
雑音の振幅値v1は v1＝C2／C1＋C2（e2−e1） ……(1) となり、１次巻線２７の両端に生じるスイツチン
グ電圧e1と、２次巻線２８の両端に誘起されるス
イツチング電圧e2との双方の影響から発生する。
通常のDC−DC変換回路においてはe1≠e2であ
る。このため１次側１８ａ，１８ｂ−２次側１９
ａ，１９ｂ間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生を少なくする
ためにはコンデンサ４３の容量値C2をコンデン
サ４２の容量値C1に対して充分に小さくする必
要がある。しかしコンデンサ４３の容量値C2は
トランスの１次巻線２７、２次巻線２８及びコア
の形状によつて定まり、容量値C2はあまり小さ
くできない。一方、コンデンサ４２の容量値C1
を大きくすると（例えばコンデンサの外付によ
り）、同相モードスイツチング雑音は小さくなる
が、１次側１８ａ，１８ｂ−２次側１９ａ，１９
ｂ間が低インピーダンスとなる。以上から１次側
１８ａ，１８ｂ−２次側１９ａ，１９ｂ間を高イ
ンピーダンスで分離し、かつ同相モードスイツチ
ング雑音を低減化させることは従来技術では困難
であつた。一例として第３図に示した構成で直流
入力電圧E1＝30V、直流出力電圧E2＝5V、出力
電力1W程度のDC−DC変換回路においては、同
相モードスイツチング雑音はリツプル成分で約
10Vpp程度生じる。但し、１次、２次巻線の構成
によりこの雑音値は微妙に異なつてくる。 Next, we will focus on closed circuits. Normal capacitor 42,
The capacitance values of 43 are both small, and the impedance is sufficiently high over a high frequency range including the switching frequency. Now, in a closed circuit, capacitor 4
Letting the switching voltages generated across the terminals 2 and 43 be v 1 and v 2 respectively, the following relationship is satisfied from the Kirchhoff voltage side: v 1 +v 2 =e 1 -e 2 . Further, the ratio between voltages v 1 and v 2 is inversely proportional to the capacitance value of each capacitor 42, 43. The switching voltage v 1 generated across capacitor 42 is common mode switching noise. The following description will be made with reference to FIG. 5, which is an enlarged view of the closed circuit portion. The symbols in FIG. 5 correspond to those in FIG. 4. The capacitance values of capacitors 42 and 43 are C 1 ,
Let it be C 2 . From FIG. 5, the amplitude value v 1 of the common mode switching noise is v 1 = C 2 /C 1 +C 2 (e 2 - e 1 )...(1), and the switching voltage generated across the primary winding 27 is e 1 and the switching voltage e 2 induced across the secondary winding 28.
In a normal DC-DC conversion circuit, e 1 ≠ e 2 . Therefore, the primary side 18a, 18b - the secondary side 19
In order to isolate between a and 19b with high impedance and to reduce the occurrence of common mode switching noise, the capacitance value C2 of the capacitor 43 must be made sufficiently smaller than the capacitance value C1 of the capacitor 42. . However, the capacitance value C 2 of the capacitor 43 is determined by the shapes of the primary winding 27, secondary winding 28 and core of the transformer, and the capacitance value C 2 cannot be made very small. On the other hand, the capacitance value C 1 of the capacitor 42
If the switching noise is increased (for example, by adding an external capacitor), the common mode switching noise will be reduced;
There is a low impedance between b. From the above, it has been difficult with the prior art to isolate the primary sides 18a, 18b and the secondary sides 19a, 19b with high impedance and to reduce common mode switching noise. As an example, in a DC-DC converter circuit with the configuration shown in Figure 3, with a DC input voltage E 1 = 30V, a DC output voltage E 2 = 5V, and an output power of about 1W, the common-mode switching noise is a ripple component and is approximately
Approximately 10Vpp is generated. However, this noise value differs slightly depending on the configuration of the primary and secondary windings.

＜発明の目的＞ この発明の目的は、直流及びスイツチング周波
数を含む高周波域に亘り１次側及び２次側間を高
インピーダンスで分離し、しかも同相モードスイ
ツチング雑音の発生が少ないDC−DC変換回路を
提供することにある。<Object of the Invention> The object of the invention is to provide a DC-DC conversion system that separates the primary side and the secondary side with high impedance over a high frequency range including DC and switching frequencies, and that generates less common mode switching noise. The purpose is to provide circuits.

＜発明の構成＞ 本発明によれば、第１、第２直流電源入力端子
の間に、入力コンデンサ及びトランスの１次巻線
が接続され、その１次巻線の中点に、オンオフ制
御されるスイツチ素子が挿入され、前記トランス
の２次巻線に誘起されたスイツチング電圧を整流
平滑して出力するDC−DC変換回路において、 前記１次巻線と２次巻線との間に、その２次巻
線の静止端に接続された静電遮へい層が設けら
れ、 前記中点で分離された１次巻線の２つの半巻線
を静電遮へい層上にバイフアイラ巻きし、 前記各半巻線の巻き始めから前記各半巻線の中
点までの巻線と前記静電遮へい層との距離と、前
記各半巻線の巻き終わりから前記各半巻線の中点
までの巻線と静電遮へい層との距離と、を等しく
している。<Structure of the Invention> According to the present invention, the input capacitor and the primary winding of the transformer are connected between the first and second DC power input terminals, and the on/off control is performed at the midpoint of the primary winding. In the DC-DC conversion circuit, a switching element is inserted between the primary winding and the secondary winding of the transformer to rectify and smooth the switching voltage induced in the secondary winding of the transformer. an electrostatic shielding layer connected to the stationary end of the secondary winding; bifilar winding two half-turns of the primary winding separated at said midpoint onto the electrostatic shielding layer; The distance between the winding and the electrostatic shielding layer from the start of winding to the midpoint of each half-winding, and the winding from the end of each half-winding to the midpoint of each half-winding. and the distance to the electrostatic shielding layer are made equal.

また次のように変形することもできる。即ち第
１、第２直流電源入力端子の間に入力コンデンサ
及びトランスの１次巻線が接続され、その１次巻
線の両端と前記第１、第２直流電源入力端子との
間に、共通にオンオフ制御されるスイツチ素子が
それぞれ挿入され、前記トランスの２次巻線に誘
起されたスイツチング電圧を整流平滑して出力す
るDC−DC変換回路において、 前記１次巻線と２次巻線との間に、その２次巻
線の静止端に接続された静電遮へい層が設けら
れ、 前記１次巻線を前記静電遮へい層上に巻き、 前記１次巻線の巻き始めから前記１次巻線の中
点までの巻線と前記静電遮へい層との距離と、前
記１次巻線の巻き終わりから前記１次巻線の中点
までの巻線と静電遮へい層との距離と、を等しく
している。 It can also be modified as follows. That is, the input capacitor and the primary winding of the transformer are connected between the first and second DC power input terminals, and the common voltage is connected between both ends of the primary winding and the first and second DC power input terminals. In the DC-DC conversion circuit, a switching element that is controlled to turn on and off is inserted into each of the transformers, and the switching voltage induced in the secondary winding of the transformer is rectified, smoothed, and output. an electrostatic shielding layer connected to the stationary end of the secondary winding is provided between, the primary winding is wound on the electrostatic shielding layer, and the first The distance between the winding and the electrostatic shielding layer from the middle point of the next winding, and the distance between the winding and the electrostatic shielding layer from the end of the primary winding to the middle point of the primary winding. and are made equal.

＜第１実施例＞ 第６図はこの発明の第１実施例を示し、第３図
と対応する部分に同一符号を付けてある。この実
施例では１次巻線２７はその中が開放され、その
開放端４４，４５間にスイツチ素子２５が接続さ
れる。従つて１次巻線２７は巻線２７ａ，２７ｂ
に分割される。１次巻線２７と２次巻線２８との
間には静電遮へい層４６が介在され、この静電遮
へい層４６は、２次巻線２８の交流的な零電位点
（以下静止端と呼ぶ）である２次側１９ａに接続
されている。２次側１９ｂも静止端であり、静電
遮へい層４６を２次側１９ｂに接続しても効果は
同一である。１次巻線２７ａの端子２９側（端子
４４側）と１次巻線２７ｂの端子４５側（端子３
１側）とを対として、１次巻線２７ａ及び２７ｂ
は静電遮へい層上にバイフアラ巻きとされ、かつ
１次巻線２７ａの巻き始め、すなわち、端子２９
側から巻線２７ａの中点までの巻線と静電遮へい
層との距離と、１次巻線２７ａの巻き終わり、す
なわち、端子４４側から巻線２７ａの中点までの
巻線と静電遮へい層との距離と、を等しくしてい
る。同様に、１次巻線２７ｂの巻き始め、すなわ
ち、端子４５側から巻線２７ｂの中点までの巻線
と静電遮へい層との距離と、１次巻線２７ｂの巻
き終わり、すなわち、端子３１側から巻線２７ｂ
の中点までの巻線と静電遮へい層との距離と、を
等しくしている。このような構造をしているから
以下に説明するように１次側１８ａ−２次側１９
ａ間に発生するスイツチング電圧、すなわち同相
モードスイツチング雑音を低減化する作用があ
る。<First Embodiment> FIG. 6 shows a first embodiment of the present invention, in which parts corresponding to those in FIG. 3 are given the same reference numerals. In this embodiment, the primary winding 27 is open-circuited, and the switch element 25 is connected between the open ends 44 and 45 thereof. Therefore, the primary winding 27 is the winding 27a, 27b.
divided into An electrostatic shielding layer 46 is interposed between the primary winding 27 and the secondary winding 28. The secondary side 19a is connected to the secondary side 19a. The secondary side 19b is also a stationary end, and the effect is the same even if the electrostatic shielding layer 46 is connected to the secondary side 19b. The terminal 29 side (terminal 44 side) of the primary winding 27a and the terminal 45 side (terminal 3 side) of the primary winding 27b
1 side) as a pair, the primary windings 27a and 27b
is bifurcated on the electrostatic shielding layer, and the winding start of the primary winding 27a, that is, the terminal 29
The distance between the winding and the electrostatic shielding layer from the side to the midpoint of the winding 27a, and the end of winding of the primary winding 27a, that is, the distance between the winding and the static electricity from the terminal 44 side to the midpoint of the winding 27a. The distance to the shielding layer is made equal. Similarly, the distance between the winding and the electrostatic shielding layer from the start of winding of the primary winding 27b, that is, from the terminal 45 side to the midpoint of the winding 27b, and the end of winding of the primary winding 27b, that is, the distance between the winding and the electrostatic shielding layer, that is, the terminal Winding 27b from the 31 side
The distance between the winding and the electrostatic shielding layer to the midpoint of is made equal. Since it has such a structure, the primary side 18a-secondary side 19 is connected as explained below.
This has the effect of reducing the switching voltage generated between terminals a, that is, common mode switching noise.

第３図に示した従来のDC−DC変換回路の場
合、同相モードスイツチング雑音は、式(1)から１
次巻線２７の両端に生じるスイツチング電圧e1と
２次巻線２８の両端に誘起されるスイツチング電
圧e2との双方の影響により発生する。しかし、第
６図に示す実施例では、（）１次巻線２７−２
次巻線２８間に静電遮へい層４６が設けられ、か
つこれが２次巻線２８の静止端である２次側１９
ａに接続されていることにより、２次巻線２８の
両端に生じるスイツチング電圧e2が１次側１８ａ
−２次側１９ａ間の電圧（同相モードスイツチン
グ雑音）に寄与しない。（）また中点で分離さ
れた１次巻線の２つの半巻線は静電遮へい層上に
バイフアラ巻とされ、かつ、それらの各半巻線の
巻き始めから各半巻線の中点までの巻線と前記静
電遮へい層との距離と、半巻線の巻き終わりから
各半巻線の中点までの巻線と静電遮へい層との距
離と、を等しくしている。その結果、半巻線と静
電遮へい層との間の浮遊容量の分布状態は両半巻
線でほぼ同一になると共に各半巻線と静電遮へい
層との間に形成される浮遊容量の分布状態は各半
巻線の中点を中心としてほぼ対称となり、各半巻
線の巻始めと巻終りにおける浮遊容量はほぼ同一
の値となる。これらのことから、１次巻線２７
ａ，２７ｂの各両端に生じるスイツチング電圧
e1／２によつて１次側１８ａ−２次側１９間に誘
起される電圧（同相モードスイツチング雑音）を
抑圧できる。 In the case of the conventional DC-DC conversion circuit shown in Figure 3, the common mode switching noise is calculated from equation (1) as 1
This occurs due to the effects of both the switching voltage e 1 generated across the secondary winding 27 and the switching voltage e 2 induced across the secondary winding 28 . However, in the embodiment shown in FIG.
A static shielding layer 46 is provided between the secondary windings 28 and this is the stationary end of the secondary winding 28 on the secondary side 19
a, the switching voltage e2 generated across the secondary winding 28 is connected to the primary side 18a.
- It does not contribute to the voltage between the secondary side 19a (common mode switching noise). () Also, the two half windings of the primary winding separated at the midpoint are bifurcated on the electrostatic shielding layer, and from the beginning of each half winding to the midpoint of each half winding. The distance between the winding and the electrostatic shielding layer is made equal to the distance between the winding and the electrostatic shielding layer from the end of each half winding to the midpoint of each half winding. As a result, the distribution state of the stray capacitance between the half windings and the electrostatic shielding layer is almost the same for both half windings, and the stray capacitance formed between each half winding and the electrostatic shielding layer is The distribution state is approximately symmetrical about the midpoint of each half-winding, and the stray capacitances at the beginning and end of each half-winding have approximately the same value. From these facts, the primary winding 27
Switching voltage generated across each of a and 27b
The voltage induced between the primary side 18a and the secondary side 19 (common mode switching noise) can be suppressed by e 1 /2.

これらの点につき第７図を用いて更に詳細に説
明する。第７図は第６図に示したDC−DC変換回
路において同相モードスイツチング雑音の低減化
作用を交流成分に着目して示したものである。第
７図中の記号は第６図に順じ、e1，e2及びv1は任
意の時点での各端子間のスイツチング電圧をまた
矢印は各電圧極性の相互関係を示す。コンデンサ
４７，４８は１次巻線２７ａと静電遮へい層４６
との間に分布するストレー容量を集中定数回路で
表わし、コンデンサ４７，４８はそれぞれ１次巻
線２７ａの両端２９，４４と静電遮へい層４６と
の間に接続してある。コンデンサ４９，５１は１
次巻線２７ｂと静電遮へい層４６との間に分布す
るストレー容量を集中定数回路で表わし、コンデ
ンサ４９，５１はそれぞれ１次巻線２７ｂの両端
４５，３９と静電遮へい層４６との間に接続され
る。コンデンサ５２，５３は２次巻線２８と静電
遮へい層４６との間に分布するストレー容量を集
中定数回路で表わし、コンデンサ５２，５３は２
次巻線２８の両端３２，３３と静電遮へい層４６
との間に接続される。コンデンサ３７、１次巻線
２７ａ，２７ｂ、スイツチ素子２５の閉回路を閉
路とし、１次巻線２７ａ，２７ｂ、スイツチ素
子２５、静電遮へい層４６の閉回路を閉路と
し、１次巻線２７ａ、静電遮へい層４６、コンデ
ンサ４７，４８の閉回路を閉路とし、スイツチ
素子２５、静電遮へい層４６、コンデンサ４８，
４９の閉回路を閉路とし、１次巻線２７ｂ、静
電遮へい層４６、コンデンサ４９，５１の閉回路
を閉路とし、２次巻線２８、コンデンサ５２，
５３、静電遮へい層４６の閉回路を閉路とす
る。 These points will be explained in more detail using FIG. 7. FIG. 7 shows the effect of reducing the common mode switching noise in the DC-DC conversion circuit shown in FIG. 6, focusing on the alternating current component. The symbols in FIG. 7 are the same as in FIG. 6, where e 1 , e 2 and v 1 represent the switching voltages between the respective terminals at any given time, and the arrows represent the mutual relationship between the voltage polarities. The capacitors 47 and 48 are connected to the primary winding 27a and the electrostatic shielding layer 46.
The stray capacitance distributed between is represented by a lumped constant circuit, and capacitors 47 and 48 are connected between both ends 29 and 44 of the primary winding 27a and the electrostatic shielding layer 46, respectively. Capacitors 49 and 51 are 1
Stray capacitance distributed between the secondary winding 27b and the electrostatic shielding layer 46 is represented by a lumped constant circuit, and capacitors 49 and 51 are connected between both ends 45 and 39 of the primary winding 27b and the electrostatic shielding layer 46, respectively. connected to. The capacitors 52 and 53 represent the stray capacitance distributed between the secondary winding 28 and the electrostatic shielding layer 46 using lumped constant circuits.
Both ends 32 and 33 of the next winding 28 and the electrostatic shielding layer 46
connected between. The closed circuit of the capacitor 37, the primary windings 27a, 27b, and the switch element 25 is a closed circuit, and the closed circuit of the primary windings 27a, 27b, the switch element 25, and the electrostatic shielding layer 46 is a closed circuit, and the primary winding 27a is a closed circuit. , the electrostatic shielding layer 46, the capacitors 47 and 48 are closed, and the switch element 25, the electrostatic shielding layer 46, the capacitor 48,
49 is a closed circuit, the primary winding 27b, electrostatic shielding layer 46, and capacitors 49 and 51 are closed circuits, and the secondary winding 28, capacitor 52,
53, the closed circuit of the electrostatic shielding layer 46 is made a closed circuit.

最初に前記（）項を説明する。第７図におい
て、まず閉路に着目する。出力コンデンサ３５
はスイツチング周波数成分に対しては短絡（充分
に低インピーダンス）であるから、その両端には
スイツチング電圧は発生しない。したがつてキル
ヒホツフの電圧側から半波整流用のダイオード３
４の両端には、２次巻線２８の両端３２，３３間
に誘起されるスイツチング電圧e2に等しい振幅の
スイツチング電圧が逆位相で発生する。次に閉路
に着目する。コンデンサ５２の両端は静電遮へ
い層４６により短絡されているからスイツチング
電圧は発生しない。したがつて、閉路における
キルヒホツフの電圧側からコンデンサ５３の両端
には２次巻線２８の両端３２，３３間に生じるス
イツチング電圧e2に等しい振幅のスイツチング電
圧が逆位相で発生する。以上から２次側に発生す
るスイツチング電圧e2は静電遮へい層４６により
２次側のみに閉じ、１次側１８ａ−２次側１９間
の電圧には影響を及ぼさないことが説明された。 First, the above item () will be explained. In FIG. 7, attention is first paid to the closed circuit. Output capacitor 35
Since is a short circuit (sufficiently low impedance) for the switching frequency component, no switching voltage is generated across it. Therefore, diode 3 for half-wave rectification from the Kirchhoff voltage side
4, a switching voltage with an amplitude equal to the switching voltage e 2 induced between the ends 32 and 33 of the secondary winding 28 is generated in opposite phase. Next, we will focus on closed circuits. Since both ends of the capacitor 52 are short-circuited by the electrostatic shielding layer 46, no switching voltage is generated. Therefore, a switching voltage with an amplitude equal to the switching voltage e 2 generated between the ends 32 and 33 of the secondary winding 28 is generated in opposite phase across the capacitor 53 from the Kirchhoff voltage side in the closed circuit. From the above, it has been explained that the switching voltage e2 generated on the secondary side is closed only to the secondary side by the electrostatic shielding layer 46, and does not affect the voltage between the primary side 18a and the secondary side 19.

次に前記（）項について説明する。第７図に
おいて閉路に着目する。入力コンデンサ３７は
スイツチング周波数成分に対しては短絡であるか
ら、その両端にはスイツチング電圧は発生しな
い。１次巻線２７は中点４４，４５にて２分割さ
れているから、１次巻線２７ａの両端２９，４４
間と、１次巻線２７ｂの両端４５，３１間とに
は、等しい振幅のスイツチング電圧e1／２が同位相 で誘起される。こゝで閉路におけるキルヒホツ
フの電圧則からスイツチ素子２５の両端には１次
巻線２７ａの両端２９，４４間と、１次巻線２７
ｂの両端４５，３１間とにそれぞれ誘起されるス
イツチング電圧の和e1に等しい振幅のスイツチン
グ電圧が逆位相で発生する。 Next, the above item () will be explained. In FIG. 7, attention is paid to the closed circuit. Since the input capacitor 37 is short-circuited for the switching frequency component, no switching voltage is generated across it. Since the primary winding 27 is divided into two parts at the midpoints 44 and 45, both ends 29 and 44 of the primary winding 27a
A switching voltage e 1 /2 of equal amplitude and in phase is induced between both ends 45 and 31 of the primary winding 27b. Here, from Kirchhoff's voltage law in a closed circuit, between both ends 29 and 44 of the primary winding 27a, and between the ends 29 and 44 of the primary winding 27a,
A switching voltage with an amplitude equal to the sum e 1 of the switching voltages induced between both ends 45 and 31 of the transistor b is generated in opposite phase.

次に閉路，及びに着目する。通常コンデ
ンサ４７，４８，４９及び５１の容量値はともに
小さく、スイツチング周波数を含む高周波数に亘
り充分に高インピーダンスとなる。また１次巻線
２７ａ，２７ｂとその一端２９，４５を同一側と
して静電遮へい層上にバイフアラ巻き、すなわ
ち、１次巻線２７ａ，２７ｂをコアの一端の同じ
位置から並べて巻き始める巻き方にすることによ
り、静電遮へい層４６−一次巻線２７ａ間と、静
電遮へい層４６−一次巻線２７ｂ間との物理的な
位置関係、すなわち、１次巻線２７ａの巻線と静
電遮へい層４６との距離と、１次巻線２７ｂの巻
線と静電遮へい層４６との距離とは等しくなる。
従つて、一次巻線２７ａと静電遮へい層４６との
間の浮遊容量の分布状態と、一次巻線２７ｂと静
電遮へい層４６との間の浮遊容量の分布状態はほ
ぼ同一になるため、コンデンサ４７とコンデンサ
４９の容量値、及び、コンデンサ４８とコンデン
サ５１の容量値は各々概ね等しくなり、これらを
各々C3，C4とする。 Next, we will focus on cycles and. Normally, the capacitance values of capacitors 47, 48, 49, and 51 are all small, and the impedance is sufficiently high over high frequencies including the switching frequency. In addition, the primary windings 27a, 27b and their one ends 29, 45 are placed on the same side, and bi-alternative winding is performed on the electrostatic shielding layer, that is, the primary windings 27a, 27b are arranged side by side from the same position on one end of the core, and the winding starts. By doing so, the physical positional relationship between the electrostatic shielding layer 46 and the primary winding 27a and between the electrostatic shielding layer 46 and the primary winding 27b, that is, the winding of the primary winding 27a and the electrostatic shielding The distance to the layer 46 is equal to the distance between the winding of the primary winding 27b and the electrostatic shielding layer 46.
Therefore, the distribution of stray capacitance between the primary winding 27a and the electrostatic shielding layer 46 and the distribution of stray capacitance between the primary winding 27b and the electrostatic shielding layer 46 are almost the same. The capacitance values of the capacitor 47 and the capacitor 49 and the capacitance values of the capacitor 48 and the capacitor 51 are approximately equal to each other, and these are respectively designated as C 3 and C 4 .

こゝで、閉路に着目する。コンデンサ４７の
両端にスイツチング電圧v1が発生したとする。先
に述べたように１次巻線２７ａ，２７ｂの電圧の
和とスイツチ素子２５の電圧とは等しく逆位相で
あるから、キルヒホツフの電圧側から、コンデン
サ５１の両端にはコンデンサ４７の両端に発生す
るスイツチング電圧v1に等しい振幅のスイツチン
グ電圧が逆位相で発生する。このスイツチング電
圧v1は同相モードスイツチング電圧である。次に
第８図を用いて説明する。第８図は第７図中の閉
路，及び部分を抽象したものであり、記号
は第７図に順ずる。コンデンサ４７，４９の容量
値はC3、コンデンサ４８，５１の容量値C4とす
る。第８図の閉路，及びについてそれぞれ
閉路方程式を解くと、 v1＝C3−C4／C3＋C4 e1／４ ……(2) v2＝−3C3＋C4／C3＋C4 e1／４ ……(3) v3＝−C3＋3C4／C3＋C4 e1／４ ……(4) となる。式(2)から同相モードスイツチング雑音は
コンデンサ４７，４９の容量値C3とコンデンサ
４８，５１の容量値C4との差が小さい程低減化
される。さて、第６図において、静電遮へい層４
６一巻線端２９（あるいは４５）間のストレー容
量と、静電遮へい層４６一巻線端４４（あるいは
３１）間のストレー容量と等しくする技術は比較
的容易であり、静電遮へい層４６に対する巻線端
２６（あるいは４５）の物理的位置と、静電遮へ
い層４６に対する巻線端４４（あるいは３１）の
物理的位置とを対称、すなわち、１次巻線２７ａ
の巻き始めである端子２９側から巻線２７ａの中
点までの巻線と静電遮へい層との距離と、１次巻
線２７ａの巻き終わりである端子４４側から巻線
２７ａの中点までの巻線と静電遮へい層との距離
と、を等しくし、同様に、１次巻線２７ｂの巻き
始め、すなわち、端子４５側から巻線２７ｂの中
点までの巻線と静電遮へい層との距離と、１次巻
線２７ｂの巻き終わり、すなわち、端子３１側か
ら巻線２７ｂの中点までの巻線と静電遮へい層と
の距離と、を等しくすればよい。例えば、１次巻
線２７ａ，２７ｂを静電遮へい層４６の上に１層
巻きとなるように構成すればよい。従つて、第８
図において、コンデンサ４７（あるいはコンデン
サ４９）の容量値C3と、コンデンサ４８（ある
いはコンデンサ５１）の容量値C4とを概ね等し
くする技術は既知である。以上から、スイツチ素
子２５を１次巻線２７の中点に挿入接続すること
により１次巻線２７ａ，２７ｂの各両端に誘起さ
れるスイツチング電圧e1／２が１次側１８ａ−２次 側１９ａ間の電圧に及ぼす影響を低減化させ、同
相モードスイツチング雑音の発生を抑圧し得るこ
とを説明できた。 Here, we will focus on closed circuits. Assume that a switching voltage v 1 is generated across the capacitor 47. As mentioned earlier, the sum of the voltages of the primary windings 27a and 27b and the voltage of the switch element 25 are equal and in opposite phases, so from the Kirchhoff voltage side, the voltage generated at both ends of the capacitor 51 is generated at both ends of the capacitor 47. A switching voltage with an amplitude equal to the switching voltage v 1 is generated in opposite phase. This switching voltage v 1 is a common mode switching voltage. Next, it will be explained using FIG. FIG. 8 is an abstraction of the cycle and parts in FIG. 7, and the symbols are the same as in FIG. 7. The capacitance values of the capacitors 47 and 49 are assumed to be C 3 , and the capacitance value of the capacitors 48 and 51 is assumed to be C 4 . Solving the cycle equations for the cycles and in Figure 8, v 1 = C 3 - C 4 / C 3 + C 4 e 1 / 4 ... (2) v 2 = -3C 3 + C 4 / C 3 + C 4 e 1 /4 ... (3) v 3 = -C 3 +3C 4 /C 3 +C 4 e 1 /4 ... (4). From equation (2), the common mode switching noise is reduced as the difference between the capacitance value C 3 of the capacitors 47 and 49 and the capacitance value C 4 of the capacitors 48 and 51 is smaller. Now, in FIG. 6, the electrostatic shielding layer 4
It is relatively easy to make the stray capacitance between the electrostatic shielding layer 46 and the winding end 29 (or 45) equal to the stray capacitance between the electrostatic shielding layer 46 and the winding end 44 (or 31). The physical position of the winding end 26 (or 45) relative to the electrostatic shielding layer 46 is symmetrical with the physical position of the winding end 44 (or 31) relative to the electrostatic shielding layer 46, that is, the primary winding 27a
The distance between the winding and the electrostatic shielding layer from the terminal 29 side, where the winding starts, to the midpoint of the winding 27a, and from the terminal 44 side, where the primary winding 27a ends, to the midpoint of the winding 27a. The distance between the winding and the electrostatic shielding layer is made equal, and similarly, the distance between the winding and the electrostatic shielding layer from the beginning of the winding of the primary winding 27b, that is, from the terminal 45 side to the midpoint of the winding 27b. The distance between the end of the winding of the primary winding 27b, that is, the distance from the terminal 31 side to the midpoint of the winding 27b and the electrostatic shielding layer may be made equal. For example, the primary windings 27a and 27b may be configured to be wound in one layer on the electrostatic shielding layer 46. Therefore, the eighth
In the figure, a technique is known in which the capacitance value C 3 of capacitor 47 (or capacitor 49) and the capacitance value C 4 of capacitor 48 (or capacitor 51) are made approximately equal. From the above, by inserting and connecting the switch element 25 to the midpoint of the primary winding 27, the switching voltage e 1 /2 induced across each end of the primary windings 27a and 27b will be the same as that between the primary side 18a and the secondary side. It has been explained that the influence on the voltage between 19a and 19a can be reduced and the generation of common mode switching noise can be suppressed.

以上、第６図に示した構成により直流及びスイ
ツチング周波数を含む高周波域に亘り１次側１８
ａ，１８ｂ−２次側１９ａ，１９ｂ間を高インピ
ーダンスで分離し、かつ同相モードスイツチング
雑音の発生が少ないDC−DC変換回路を提供し得
る。 As described above, with the configuration shown in FIG. 6, the primary side 18
A, 18b and the secondary sides 19a, 19b are separated by high impedance, and a DC-DC conversion circuit that generates less common mode switching noise can be provided.

＜第２実施例＞ 第９図はこの発明の第２実施例を示し、スイツ
チ素子２５ａ，２５ｂが１次巻線２７の両端にそ
れぞれ直列に接続され、スイツチ素子２５ａ，２
５ｂは駆動回路３８により同一のタイミングで断
続制御される。スイツチ素子２５ａ，２５ｂの他
端は入力コンデンサ３７の両端に接続される。１
次巻線２７と２次巻線２８との間に静電遮へい層
４６が介在される。この静電遮へい層４６は２次
巻線２８の交流的な０電位点（以下静止端と呼
ぶ）である巻線端３２に接続している。２次側１
９ｂも静止端であり、静電遮へい層４６を２次側
１９ｂに接続しても効果は同一である。その他の
記号は第３図に順ずる。１次巻線２７の巻き始
め、すなわち、端子２９側から１次巻線２７の中
点までの巻線と静電遮へい層４６との距離と、１
次巻線２７の巻き終わり、すなわち、端子３１側
から１次巻線２７の中点までの巻線と静電遮へい
層４６との距離と、を等しくしている。このよう
な構造をしているから以下に述べるように１次側
１８ａ−２次側１９ａ間に発生するスイツチング
電圧、即ち同相モードスイツチング雑音を低減化
する作用がある。<Second Embodiment> FIG. 9 shows a second embodiment of the present invention, in which switch elements 25a and 25b are connected in series to both ends of the primary winding 27, respectively.
5b is controlled intermittently by the drive circuit 38 at the same timing. The other ends of switch elements 25a and 25b are connected to both ends of input capacitor 37. 1
An electrostatic shielding layer 46 is interposed between the primary winding 27 and the secondary winding 28 . This electrostatic shielding layer 46 is connected to a winding end 32 which is an AC zero potential point (hereinafter referred to as a stationary end) of the secondary winding 28. Secondary side 1
9b is also a stationary end, and the effect is the same even if the electrostatic shielding layer 46 is connected to the secondary side 19b. Other symbols are in accordance with Figure 3. The distance between the winding start of the primary winding 27, that is, from the terminal 29 side to the midpoint of the primary winding 27 and the electrostatic shielding layer 46, and 1
The end of the winding of the secondary winding 27, that is, the distance between the winding from the terminal 31 side to the midpoint of the primary winding 27 and the electrostatic shielding layer 46 is made equal. This structure has the effect of reducing the switching voltage generated between the primary side 18a and the secondary side 19a, that is, the common mode switching noise, as described below.

第９図に示した構成によれば、（）１次巻線
２７−２次巻線２８間に静電遮へい層４６が設け
られかつこれは２次巻線２８の静止端である巻線
端３２に接続されていることにより２次巻線２８
の両端に生じるスイツチング電圧e2が１次側１８
ａ−２次側１９ａ間の電圧（同相モードスイツチ
ング雑音）に寄与しない。（）１次巻線の巻き
始めから１次巻線の中点までの巻線と静電電遮へ
い層との距離と、１次巻線の巻き終わりから１次
巻線の中点までの巻線と静電遮へい層との距離
と、を等しくしている。その結果、１次巻線と静
電遮へい層との間に形成される浮遊容量の分布状
態は中点を中心としてほぼ対称となる、巻始めと
巻終りにおける浮遊容量はほぼ等しくなる。この
ため１次巻線２７の両端に生じるスイツチング電
圧e1によつて１次側１８ａ−２次側１９ａ間に誘
起される電圧（同相モードスイツチング雑音）を
抑圧できる。 According to the configuration shown in FIG. 9, an electrostatic shielding layer 46 is provided between the primary winding 27 and the secondary winding 28, and this is located at the winding end which is the stationary end of the secondary winding 28. 32, the secondary winding 28
The switching voltage e2 generated across the primary side 18
It does not contribute to the voltage between a and secondary side 19a (common mode switching noise). () The distance between the winding and the electrostatic shielding layer from the beginning of the primary winding to the midpoint of the primary winding, and the distance from the end of the primary winding to the midpoint of the primary winding and the distance to the electrostatic shielding layer are made equal. As a result, the distribution of stray capacitance formed between the primary winding and the electrostatic shielding layer is approximately symmetrical about the midpoint, and the stray capacitances at the beginning and end of the winding are approximately equal. Therefore, the voltage (common mode switching noise) induced between the primary side 18a and the secondary side 19a by the switching voltage e1 generated across the primary winding 27 can be suppressed.

これらについて第１０図に用いて詳細に説明す
る。第１０図は第９図に示したDC−DC変換回路
において同相モードスイツチング雑音の低減化作
用を交流成分に着目して示したものである。第１
０図中の記号は第９図に順じ、e1，e2，v1及びv2
は任意の時点での各端子間のスイツチング電圧
を、また矢印は各電圧極性の相互関係を示す。ま
た第１０図において第７図と対応する部分には同
一符号を付けてある。閉路はコンデンサ３７、
１次巻線２７、スイツチング素子２５ａ，２５ｂ
で構成され、閉路は１次巻線２７、コンデンサ
４７，５１、静電遮へい層４６で構成される。 These will be explained in detail using FIG. 10. FIG. 10 shows the effect of reducing the common mode switching noise in the DC-DC conversion circuit shown in FIG. 9, focusing on the alternating current component. 1st
The symbols in Figure 0 are as in Figure 9, e 1 , e 2 , v 1 and v 2
indicates the switching voltage between each terminal at any given time, and the arrows indicate the mutual relationship of each voltage polarity. Further, in FIG. 10, parts corresponding to those in FIG. 7 are given the same reference numerals. The closed circuit is capacitor 37,
Primary winding 27, switching elements 25a, 25b
The closed circuit is composed of a primary winding 27, capacitors 47 and 51, and an electrostatic shielding layer 46.

最初に前記（）項を説明する。第１０図にお
いてまず閉路に着目する。出力コンデンサ３５
はスイツチング周波数成分に対しては短絡（充分
に低インピーダンス）であるからその両端にはス
イツチング電圧は発生しない。したがつて、キル
ヒホツフの電圧則から半波整流用のダイオード３
４の両端には２次巻線２８の両端３２，３３間に
誘起されるスイツチング電圧e2に等しい振幅のス
イツチング電圧が逆位相で発生する。次に閉路
に着目する。コンデンサ５２，５３は２次巻線２
８と静電遮へい層４６との間に分布するストレー
容量を集中定数回路で表わしたものである。コン
デンサ５２は巻線端３２と静電遮へい層４６との
間に接続され、コンデンサ５３は巻線端３３と静
電遮へい層４６との間に接続される。こゝで、コ
ンデンサ５２の両端は静電遮へい層４６により短
絡されているからスイツチング電圧は発生しな
い。したがつて閉路におけるキルヒホツフの電
圧則からコンデンサ５３の両端には、２次巻線２
８の両端３２，３３間に生じるスイツチング電圧
e2に等しい振幅のスイツチング電圧が逆位相で発
生する。以上から２次側に発生するスイツチング
電圧e2は静電遮へい層４６により２次側のみに閉
じ、１次側１８ａ−２次側１９ａ間の電圧には影
響を及ぼさない。 First, the above item () will be explained. In FIG. 10, first focus on the closed circuit. Output capacitor 35
Since is a short circuit (sufficiently low impedance) for the switching frequency component, no switching voltage is generated across it. Therefore, from Kirchhoff's voltage law, diode 3 for half-wave rectification
A switching voltage having an amplitude equal to the switching voltage e 2 induced between both ends 32 and 33 of the secondary winding 28 is generated at both ends of the secondary winding 28 in opposite phases. Next, we will focus on closed circuits. Capacitors 52 and 53 are secondary winding 2
8 and the electrostatic shielding layer 46 is expressed by a lumped constant circuit. Capacitor 52 is connected between winding end 32 and electrostatic shielding layer 46 , and capacitor 53 is connected between winding end 33 and electrostatic shielding layer 46 . Here, since both ends of the capacitor 52 are short-circuited by the electrostatic shielding layer 46, no switching voltage is generated. Therefore, from Kirchhoff's voltage law in a closed circuit, the secondary winding 2 is connected to both ends of the capacitor 53.
Switching voltage generated between both ends 32 and 33 of 8
Switching voltages of amplitude equal to e 2 are generated in opposite phases. From the above, the switching voltage e2 generated on the secondary side is closed only to the secondary side by the electrostatic shielding layer 46, and does not affect the voltage between the primary side 18a and the secondary side 19a.

次に前記（）項について説明する。第１０図
において閉路に着目する。入力コンデンサ３７
はスイツチング周波数成分に対しては短絡である
からその両端にはスイツチング電圧は発生しな
い。また１次巻線２７の両端２９，３１間には、
スイツチ素子２５ａ，２５ｂのオン／オフは同位
相である。したがつて、閉路におけるキルヒホ
ツフの電圧則からスイツチ素子２５ａ，２５ｂの
両端には１次巻線２７の両端２９，３１間に誘起
されるスイツチング電圧e1とは逆位相のスイツチ
ング電圧が振幅が２分割されて発生する。こゝ
で、スイツチ素子の特性のばらつきを考えて、ス
イツチ素子２５ａ，２５ｂの両端に発生するスイ
ツチング電圧の振幅を各々e2／２＋△、e2／２−△とす る。 Next, the above item () will be explained. In FIG. 10, attention is paid to the closed circuit. input capacitor 37
Since is a short circuit for the switching frequency component, no switching voltage is generated across it. Moreover, between both ends 29 and 31 of the primary winding 27,
The switch elements 25a and 25b are turned on and off in the same phase. Therefore, according to Kirchhoff's voltage law in a closed circuit, a switching voltage having an opposite phase to the switching voltage e 1 induced between the ends 29 and 31 of the primary winding 27 is generated at both ends of the switching elements 25a and 25b with an amplitude of 2. Occurs in parts. Here, in consideration of variations in the characteristics of the switch elements, the amplitudes of the switching voltages generated across the switch elements 25a and 25b are assumed to be e 2 /2+Δ and e 2 /2−Δ, respectively.

次に閉路に着目する。コンデンサ４７，５１
は静電遮へい層４６と１次巻線２７との間に分布
するストレー容量を集中定数回路で表わしたもの
であり、コンデンサ４７は静電遮へい層４６と巻
線層２９との間に接続され、コンデンサ５１は静
電遮へい層４６と巻線端３１との間に接続され
る。通常、このコンデンサ４７，５１の容量値は
ともに小さく、スイツチング周波数を含む高周波
域に亘り充分に高インピーダンスとなる。さて、
コンデンサ４７，５１の両端に発生するスイツチ
ング電圧を各々v1，v2とすると、閉路における
キルヒホツフの電圧則からv1＋v2＝−e1となる関
係を満たす。 Next, we will focus on closed circuits. Capacitor 47, 51
is a lumped constant circuit representing the stray capacitance distributed between the electrostatic shielding layer 46 and the primary winding 27, and the capacitor 47 is connected between the electrostatic shielding layer 46 and the winding layer 29. , a capacitor 51 is connected between the electrostatic shielding layer 46 and the winding end 31. Normally, the capacitance values of the capacitors 47 and 51 are both small, and the impedance is sufficiently high over a high frequency range including the switching frequency. Now,
Letting the switching voltages generated across the capacitors 47 and 51 be v 1 and v 2 respectively, the following relationship is satisfied from Kirchhoff's voltage law in a closed circuit: v 1 +v 2 =-e 1 .

以下、閉路部分の拡大図である第１１図を用
いて説明する。第１１図中の記号は第１０図に順
ずる。各々コンデンサ４７，５１の容量値をC3，
C4とする。第１１図の閉路について閉路方程
式を解くと、 v1＝−C4／C3＋C4e1 ……(5) となる。さて再び第１０図に戻つて説明する。同
相モードスイツチング電圧は１次側１８ａ−２次
側１９ａ間に生じるスイツチング電圧であり、こ
れをv3と記すと、第１０図から、 v3＝v1＋（e1／２−△） ……(6) 式(6)に式(5)を代入し、 v3＝−C4−C3／C3＋C4 e1／２−△ ……(7) となる。式(7)において△の値は充分に小さく同相
モードスイツチング雑音は、コンデンサ４７の容
量値C3とコンデンサ５１の容量値C4との差が小
さい程低減化される。さて、第９図において、静
電遮へい層４６一巻線端２９間のストレー容量と
静電遮へい層４６一巻線端３１間のストレー容量
とを等しくする技術は比較的容易であり、静電遮
へい層４６に対する巻線端２９の物理的位置と静
電遮へい層４６に対する巻線端３１の物理的位置
を対称、すなわち、１次巻線２７の巻き始めであ
る巻先端２９から１次巻線２７の中点までの巻線
と静電遮へい層４６との距離と、１次巻線２７の
巻き終わりである巻先端３１から１次巻線２７の
中点までの巻線と静電遮へい層４６との距離と、
を等しくすればよい。例えば、１次巻線２７を静
電遮へい層４６の上に１層巻きとなるように構成
すればよい。従つて、第１０図においてコンデン
サ４７の容量値C3とコンデンサ５１の容量値C4
とを概ね等しくする技術は既知である。以上から
スイツチ素子２５ａ，２５ｂを１次巻線２７の両
側に接続することにより、１次巻線２７の両端に
誘起されるスイツチング電圧e1が１次側１８ａ−
２次側１９ａ間の電圧に及ぼす影響を低減化さ
せ、同相モードスイツチング雑音の発生を抑圧し
得ることを説明できた。 The explanation will be given below using FIG. 11, which is an enlarged view of the closed circuit portion. The symbols in FIG. 11 correspond to those in FIG. The capacitance values of capacitors 47 and 51 are C 3 ,
Let it be C 4 . Solving the cycle equation for the cycle in Figure 11 gives v 1 = -C 4 /C 3 +C 4 e 1 ...(5). Now, let us return to FIG. 10 and explain. The common mode switching voltage is the switching voltage generated between the primary side 18a and the secondary side 19a, and if this is written as v3 , then from Fig. 10, v3 = v1 + ( e1 /2-△) ...(6) Substituting equation (5) into equation (6), v 3 =-C 4 -C 3 /C 3 +C 4 e 1 /2-△ ...(7). In equation (7), the value of Δ is sufficiently small, and the common mode switching noise is reduced as the difference between the capacitance value C 3 of the capacitor 47 and the capacitance value C 4 of the capacitor 51 becomes smaller. Now, in FIG. 9, the technique of making the stray capacitance between the electrostatic shielding layer 46 and the winding end 29 equal to the stray capacitance between the electrostatic shielding layer 46 and the winding end 31 is relatively easy; The physical position of the winding end 29 with respect to the shielding layer 46 and the physical position of the winding end 31 with respect to the electrostatic shielding layer 46 are symmetrical, that is, the primary winding starts from the winding tip 29 where the primary winding 27 begins to wind. The distance between the winding and the electrostatic shielding layer 46 from the midpoint of the primary winding 27, and the distance between the winding and the electrostatic shielding layer from the end of the winding 31 of the primary winding 27 to the midpoint of the primary winding 27. The distance from 46 and
Just make them equal. For example, the primary winding 27 may be configured to be wound in one layer on the electrostatic shielding layer 46. Therefore, in FIG. 10, the capacitance value C 3 of the capacitor 47 and the capacitance value C 4 of the capacitor 51 are
Techniques for making these approximately equal are known. From the above, by connecting the switching elements 25a and 25b to both sides of the primary winding 27, the switching voltage e1 induced across the primary winding 27 is reduced to the primary side 18a-
It has been explained that the influence on the voltage between the secondary side 19a can be reduced and the generation of common mode switching noise can be suppressed.

以上、第９図に示した構成により直流及びスイ
ツチング周波数を含む高周波域に亘り１次側１８
ａ，１８ｂ−２次側１９ａ，１９ｂ間を高インピ
ーダンスで分離し、かつ同相モードスイツチング
雑音の発生が少ないDC−DC変換回路を提供でき
る。 As described above, with the configuration shown in FIG. 9, the primary side 18 is
A, 18b and the secondary sides 19a, 19b are separated by high impedance, and a DC-DC conversion circuit that generates little common mode switching noise can be provided.

さて、第６図、第９図において２次側が多出力
で２次巻線を複数個有するDC−DC変換回路とす
る場合には１次巻線、複数の２次巻線を順次同軸
心上に形成し、２次巻線相互間にも静電遮へい層
を設け、かつこの静電遮へい層を１次巻線−２次
巻線間の静電遮へい層４６に接続した構成とする
ことが、同相モードスイツチング雑音の発生を少
なくする上で有利である。 Now, in Figures 6 and 9, when the secondary side is a DC-DC conversion circuit with multiple outputs and multiple secondary windings, the primary winding and multiple secondary windings are sequentially arranged on the coaxial center. The electrostatic shielding layer may be formed between the secondary windings, and an electrostatic shielding layer may be provided between the secondary windings, and this electrostatic shielding layer may be connected to the electrostatic shielding layer 46 between the primary winding and the secondary winding. , which is advantageous in reducing the occurrence of common mode switching noise.

＜第３実施例＞ 以上はいわゆる電流伝送形、つまり第６図及び
第９図において１次側のスイツチ素子２５，２５
ａ，２５ｂがオフの時に２次側の半波整流用のダ
イオード３４が導通する形式のDC−DC変換回路
にこの発明を適用したが、いわゆる電圧伝送形、
つまり１次側のスイツチ素子がオンの時に、２次
側の半波整流用のダイオードが導通する形式の
DC−CC変換回路にも、この発明を適用できる。
その例を第６図と対応して第１２図に示す。これ
ら両図における相違は整流用ダイオード３４の極
性が逆にされていることである。また第９図に示
したものと対応する電圧伝送形DC−DC変換回路
を第１３図に示す。この場合も整流用ダイオード
３４の極性が逆となるだけである。<Third Embodiment> The above is a so-called current transmission type switch element 25, 25 on the primary side in FIGS. 6 and 9.
The present invention was applied to a DC-DC converter circuit in which the half-wave rectifier diode 34 on the secondary side conducts when a and 25b are off, but it is not applicable to the so-called voltage transmission type.
In other words, when the primary side switch element is on, the secondary side half-wave rectifier diode conducts.
The present invention can also be applied to a DC-CC conversion circuit.
An example thereof is shown in FIG. 12 corresponding to FIG. 6. The difference between these two figures is that the polarity of the rectifying diode 34 is reversed. Further, a voltage transmission type DC-DC conversion circuit corresponding to that shown in FIG. 9 is shown in FIG. In this case as well, only the polarity of the rectifying diode 34 is reversed.

＜効果＞ 以上説明したようにこの発明により、直流及び
スイツチング周波数を含む高周波域に亘り入力側
及び出力側間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生が少ないDC
−DC変換回路が提供できるため、例えば平衡形
ケーブルを用いたデイジタル加入者線伝送系にお
いて、局からの遠方給電によつて動作する加入者
宅内側に設置されるデイジタル回線終端装置用の
受電用電源としての適用に利点がある。具体的に
はDC−DC変換回路の発生するスイツチング雑音
のパルス伝送系回路への廻り込みが少なく、デイ
ジタル回線終端装置と加入者線との高インピーダ
ンス分離が可能である。これによる効果はパルス
伝送帯域においてデイジタル回線終端装置の高い
不平衡減衰量が得られ、加入者線上に誘導される
大きい縦雑音に対してデイジタル信号の符号誤り
を極力抑圧し得ることである。<Effects> As explained above, the present invention provides a DC switching system that isolates the input side and output side with high impedance over a high frequency range including DC and switching frequencies, and generates less common mode switching noise.
- Since it can provide a DC conversion circuit, for example, in a digital subscriber line transmission system using a balanced cable, it can be used to receive power for a digital line termination device installed inside a subscriber's premises that operates by distant power supply from a station. It has advantages in application as a power source. Specifically, the switching noise generated by the DC-DC conversion circuit is less likely to enter the pulse transmission system circuit, and high impedance separation between the digital line termination device and the subscriber line is possible. The effect of this is that a high unbalanced attenuation of the digital line termination device can be obtained in the pulse transmission band, and code errors in the digital signal can be suppressed as much as possible against large vertical noise induced on the subscriber line.

次に数値例を示す。第６図及び第１２図に示し
た構成において、入力電圧E1を約26V、入力電流
を約24ｍＡ、出力電圧E2を5V±3.5％、出力電力
約500mW、１次巻線２７ａ，２７ｂの巻線数を
各40回程度の２線巻き（バイフアイラ巻き）、２
次巻線２８の巻線数は16回程度、静電遮へい層４
６は銅箔、スイツチ素子２５はMOS−FET、整
流用ダイオード３４はシヨツトキーバリアダイオ
ード、１次巻線２７ａ，２７ｂは静電遮へい層４
６に対して１層巻き、スイツチング周波数約70K
HzとしたDC−DC変換回路において、同相モード
スイツチング雑音はリツプル成分で約0.5Vppで
あつた。スイツチ素子の駆動回路３８は、他励形
あるいは自励形としても、上記同相モードスイツ
チング雑音は同一であつた。なお、出力電圧の定
電圧化は２次側にシヤントレギユレータを用いて
いる。また、電力変換効率は約80％であつた。 A numerical example is shown next. In the configuration shown in FIGS. 6 and 12, the input voltage E 1 is approximately 26 V, the input current is approximately 24 mA, the output voltage E 2 is 5 V ± 3.5%, the output power is approximately 500 mW, and the primary windings 27a and 27b are 2-wire winding (bi-fila winding) with approximately 40 turns each, 2
The number of turns of the next winding 28 is about 16, and the electrostatic shielding layer 4
6 is a copper foil, the switch element 25 is a MOS-FET, the rectifier diode 34 is a shot key barrier diode, and the primary windings 27a and 27b are the electrostatic shielding layer 4.
1 layer winding for 6, switching frequency approximately 70K
In the DC-DC conversion circuit with Hz, the common mode switching noise was a ripple component of about 0.5Vpp. The common mode switching noise was the same whether the switch element drive circuit 38 was a separately excited type or a self-excited type. Note that a shunt regulator is used on the secondary side to make the output voltage constant. Furthermore, the power conversion efficiency was approximately 80%.

また、第９図及び第１３図に示した構成におい
て１次巻線２７の巻線数を80回程度で静電遮へい
層４６に対して１層巻きとし、スイツチ素子２５
ｂをＰチヤンネルMOS−FET、スイツチ素子２
５ａをＮチヤンネルMOS−FETとした他は上記
と同一とし、同様の結果を得た。 In addition, in the configuration shown in FIGS. 9 and 13, the number of turns of the primary winding 27 is about 80, and one layer is wound around the electrostatic shielding layer 46, and the switch element 25
b is P channel MOS-FET, switch element 2
The same results as above were obtained except that 5a was an N-channel MOS-FET.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図はそれぞれ加入者宅内側に設
定されるデイジタル回線終端装置の構成を示す
図、第３図は従来の電流伝送形DC−DC変換回路
の基本構成を示す接続図、第４図は第３図のDC
−DC変換回路における同相モードスイツチング
雑音の発生機構の説明図、第５図は第４図の閉路
部分の拡大図、第６図はこの発明を電流伝送形
DC−DC変換回路に適用した実施例を示す接続
図、第７図は第６図のDC−DC変換回路における
同相モードスイツチング雑音低減化作用の説明
図、第８図は第７図の閉路，，部分の拡大
図、第９図はこの発明を電流伝送形DC−DC変換
回路に適用した他の実施例を示す接続図、第１０
図は第９図のDC−DC変換回路における同相モー
ドスイツチング雑音低減化作用の説明図、第１１
図は第１０図の閉路部分の拡大図、第１２図は
この発明を電圧伝送形DC−DC変換回路に適用し
た実施例を示す接続図、第１３図はこの発明を電
圧伝送形DC−DC変換回路に適用した他の実施例
を示す接続図である。 ２４：直流電源、２５，２５ａ，２５ｂ：スイ
ツチ素子、２６：トランス、２７：１次巻線、２
７ａ，２７ｂ：中点で２分割された１次巻線、２
８：２次巻線、３４：半波整流用のダイオード、
３５：出力コンデンサ、３６：負荷、３７：入力
コンデンサ、３８：スイツチ素子の駆動回路、４
６：静電遮へい層。 Figures 1 and 2 are diagrams showing the configuration of a digital line termination device installed inside a subscriber's premises, respectively. Figure 3 is a connection diagram showing the basic configuration of a conventional current transmission type DC-DC conversion circuit. Figure 4 is the DC of Figure 3.
- An explanatory diagram of the generation mechanism of common mode switching noise in a DC conversion circuit, Fig. 5 is an enlarged view of the closed circuit part of Fig. 4, and Fig. 6 is a current transmission type
A connection diagram showing an example applied to a DC-DC conversion circuit, Fig. 7 is an explanatory diagram of the common mode switching noise reduction effect in the DC-DC conversion circuit of Fig. 6, and Fig. 8 is a closed circuit diagram of Fig. 7. , , an enlarged view of the parts, FIG. 9 is a connection diagram showing another embodiment in which the present invention is applied to a current transmission type DC-DC conversion circuit, and FIG.
The figure is an explanatory diagram of the common-mode switching noise reduction effect in the DC-DC conversion circuit in Figure 9, and Figure 11.
The figure is an enlarged view of the closed circuit part in Fig. 10, Fig. 12 is a connection diagram showing an embodiment in which the present invention is applied to a voltage transmission type DC-DC conversion circuit, and Fig. 13 is a connection diagram showing an embodiment in which the present invention is applied to a voltage transmission type DC-DC conversion circuit. FIG. 7 is a connection diagram showing another embodiment applied to a conversion circuit. 24: DC power supply, 25, 25a, 25b: switch element, 26: transformer, 27: primary winding, 2
7a, 27b: Primary winding divided into two at the midpoint, 2
8: Secondary winding, 34: Diode for half-wave rectification,
35: Output capacitor, 36: Load, 37: Input capacitor, 38: Switch element drive circuit, 4
6: Electrostatic shielding layer.

Claims (1)

【特許請求の範囲】 １ 第１、第２直流電源入力端子の間に、入力コ
ンデンサ及びトランスの１次巻線が接続され、そ
の１次巻線の中点に、オンオフ制御されるスイツ
チ素子が挿入され、前記トランスの２次巻線に誘
起されたスイツチング電圧を整流平滑して出力す
るDC−DC変換回路において、 前記１次巻線と２次巻線との間に、その２次巻
線の静止端に接続された静電遮へい層が設けら
れ、 前記中点で分離された１次巻線の２つの半巻線
を前記トランスのコアの一端の同じ位置から並べ
て巻き始めることにより、第１の半巻線の巻き始
めから巻き終わりまでの巻線と静電遮へい層との
距離と、第２の半巻線の巻き終わりから巻き始め
までの巻線と静電遮へい層との距離と、を等しく
し、前記第１の半巻線の巻き始め及び前記第２の
半巻線の巻き終わりを前記１次巻線の中点とする
か、あるいは前記第１の半巻線の巻き終わり及び
前記第２の半巻線の巻き始めを前記１次巻線の中
点とすることを特徴とするDC−DC変換回路。 ２ 第１、第２直流電源入力端子の間に入力コン
デンサ及びトランスの１次巻線が接続され、その
１次巻線の両端と前記第１第２直流電源入力端子
との間に、共通にオンオフ制御されるスイツチ素
子がそれぞれ挿入され、前記トランスの２次巻線
に誘起されたスイツチング電圧を整流平滑して出
力するDC−DC変換回路において、 前記１次巻線と２次巻線との間に、その２次巻
線の静止端に接続された静電遮へい層が設けら
れ、前記１次巻線の巻き始めから前記１次巻線の
中点までの巻線と前記静電遮へい層との距離と、
前記１次巻線の巻き終わりから前記１次巻線の中
点までの巻線と静電遮へい層との距離と、を等し
くすることを特徴とするDC−DC変換回路。[Claims] 1. An input capacitor and a primary winding of a transformer are connected between the first and second DC power input terminals, and a switch element for on/off control is connected at the midpoint of the primary winding. In a DC-DC conversion circuit that is inserted and rectifies and smoothes the switching voltage induced in the secondary winding of the transformer and outputs the same, the secondary winding is inserted between the primary winding and the secondary winding. is provided with an electrostatic shielding layer connected to the stationary end of the transformer, and the first winding is started by starting winding of the two half-windings of the primary winding separated at the midpoint side by side from the same position on one end of the core of the transformer. The distance between the winding and the electrostatic shielding layer from the start of winding to the end of the first half winding, and the distance between the winding and the electrostatic shielding layer from the end of winding to the start of winding of the second half winding. , and the start of the first half-winding and the end of the second half-winding are the midpoint of the primary winding, or the end of the first half-winding is the midpoint of the primary winding. and a DC-DC conversion circuit characterized in that the winding start of the second half winding is set at the midpoint of the primary winding. 2. An input capacitor and a primary winding of a transformer are connected between the first and second DC power input terminals, and a common terminal is connected between both ends of the primary winding and the first and second DC power input terminals. In a DC-DC conversion circuit in which switch elements for on/off control are inserted, the switching voltage induced in the secondary winding of the transformer is rectified, smoothed, and output, and the switching voltage between the primary winding and the secondary winding is An electrostatic shielding layer connected to the stationary end of the secondary winding is provided between the windings from the beginning of the primary winding to the midpoint of the primary winding and the electrostatic shielding layer. and the distance from
A DC-DC conversion circuit characterized in that the distance between the winding from the end of the primary winding to the midpoint of the primary winding and an electrostatic shielding layer is equal.
JP13236582A 1982-07-28 1982-07-28 Dc-dc converting circuit Granted JPS5925579A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP13236582A JPS5925579A (en) 1982-07-28 1982-07-28 Dc-dc converting circuit
US06/515,754 US4507721A (en) 1982-07-28 1983-07-21 DC-DC Converter for remote power feeding
DE8383107388T DE3374745D1 (en) 1982-07-28 1983-07-27 Dc-dc converter for remote power feeding
EP83107388A EP0100098B1 (en) 1982-07-28 1983-07-27 Dc-dc converter for remote power feeding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13236582A JPS5925579A (en) 1982-07-28 1982-07-28 Dc-dc converting circuit

Publications (2)

Publication Number Publication Date
JPS5925579A JPS5925579A (en) 1984-02-09
JPH0463628B2 true JPH0463628B2 (en) 1992-10-12

Family

ID=15079660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13236582A Granted JPS5925579A (en) 1982-07-28 1982-07-28 Dc-dc converting circuit

Country Status (1)

Country Link
JP (1) JPS5925579A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545656B2 (en) * 2006-07-18 2009-06-09 Comarco Wireless Technologies, Inc. Common mode noise reduction circuit utilizing dual primary windings
JP2008227421A (en) * 2007-03-15 2008-09-25 Taiyo Yuden Co Ltd Transformer for inverter circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50121728A (en) * 1974-03-13 1975-09-23
JPS5714554U (en) * 1980-06-27 1982-01-25

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50121728A (en) * 1974-03-13 1975-09-23
JPS5714554U (en) * 1980-06-27 1982-01-25

Also Published As

Publication number Publication date
JPS5925579A (en) 1984-02-09

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