JPH046258Y2 - - Google Patents
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- Publication number
- JPH046258Y2 JPH046258Y2 JP1982037668U JP3766882U JPH046258Y2 JP H046258 Y2 JPH046258 Y2 JP H046258Y2 JP 1982037668 U JP1982037668 U JP 1982037668U JP 3766882 U JP3766882 U JP 3766882U JP H046258 Y2 JPH046258 Y2 JP H046258Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplifier
- input
- output
- gain control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 238000011084 recovery Methods 0.000 claims description 12
- 238000009499 grossing Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 description 13
- 208000019300 CLIPPERS Diseases 0.000 description 6
- 208000021930 chronic lymphocytic inflammation with pontine perivascular enhancement responsive to steroids Diseases 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005236 sound signal Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000029058 respiratory gaseous exchange Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】
本考案は自動利得制御（AGC）付き増幅回路
に関し、リカバリタイムを小さくすることなく過
大妨害入力消滅後の利得過小状態持続時間を減少
させようとするものである。[Detailed Description of the Invention] The present invention relates to an amplifier circuit with automatic gain control (AGC), and is intended to reduce the duration of an undergain state after the disappearance of an excessive interference input without reducing the recovery time.
プレストーク通話装置ではプレストーク釦を押
して送話、離して受話となるが、このプレストー
ク釦のオンオフ時に音声増幅器（マイクアンプ）
に音声信号より遥かに大きいシヨツクパルス（ク
リツク音）が入力する。マイクアンプはAGC付
きのものを使用し、入力音声が大でもまた小でも
ほゞ一定の出力で送話できるようにしたもので
は、AGCアンプに過大入力が入ると該アンプの
AGC回路がこの過大入力に応動してアンプ利得
が大幅に減少し、アタツクタイムに比較して遥か
に時定数が大きいリカバリタイムを経過しなけれ
ばアンプ利得が回復せず、過大入力消滅後の入力
音声の先頭部が欠落する欠点がある。 With the Press Talk telephone device, press the Press Talk button to send a call, and release the Press Talk button to receive the call, but when the Press Talk button is turned on or off, the audio amplifier (microphone amplifier)
A shock pulse (click sound) that is much louder than the audio signal is input. If the microphone amplifier is equipped with AGC and is designed to transmit at a constant output no matter how large or small the input voice is, if excessive input is applied to the AGC amplifier, the amplifier will malfunction.
The AGC circuit responds to this excessive input and the amplifier gain decreases significantly, and the amplifier gain does not recover until the recovery time, which has a much larger time constant than the attack time, passes, and the input audio after the excessive input disappears. It has the disadvantage that the beginning of the word is missing.
本考案はかゝる点を改善しようとするもので、
リカバリタイムには手をつけずに過大雑音入力後
の入力信号の先頭部欠落を回避しようとするもの
であり、特徴とする所は、入力信号を増幅する増
幅器と、該増幅器の出力を整流する整流回路と、
該整流回路の出力を平滑する平滑回路の出力電圧
に応じて前記入力信号を減衰する利得制御回路か
らなり、前記平滑回路の充電時定数で定まる小さ
いアタツクタイムで前記利得制御回路の減衰度を
大きくして、前記平滑回路の放電時定数で定まり
前記アタツクタイムより大きいリカバリタイムで
前記利得制御回路の減衰度を小さくする自動利得
制御付き増幅回路において、前記利得制御回路が
減衰動作を行う回路部分に、所定レベル未満の信
号では動作せず、該所定レベル以上の信号で動作
して信号レベルを制限するリクツパを接続したこ
とにある。以下図面に示す実施例を参照しながら
これを説明する。 This invention aims to improve these points.
It attempts to avoid missing the leading part of the input signal after inputting excessive noise without touching the recovery time, and its features include an amplifier that amplifies the input signal and a rectifier that rectifies the output of the amplifier. rectifier circuit;
The gain control circuit includes a gain control circuit that attenuates the input signal according to the output voltage of a smoothing circuit that smooths the output of the rectifier circuit, and increases the degree of attenuation of the gain control circuit with a small attack time determined by a charging time constant of the smoothing circuit. In the amplifier circuit with automatic gain control that reduces the degree of attenuation of the gain control circuit with a recovery time determined by a discharge time constant of the smoothing circuit and larger than the attack time, a predetermined amount is applied to a circuit portion where the gain control circuit performs an attenuation operation. The reason is that a receiver is connected that does not operate on signals below the level, but operates on signals above the predetermined level to limit the signal level. This will be explained below with reference to embodiments shown in the drawings.
図面で１０は増幅器、１２は入力端、１４は出
力端である。鎖線枠DETは振幅（出力レベル）
検出回路で、出力端とグランドとの間に接続され
たポテンシヨメータ１６、その摺動腕に接続され
たコンデンサ１８、ダイオード２０，２２、コン
デンサ２４、および抵抗２６からなる整流平滑回
路を備える。鎖線枠ATTは電子アツテネータで、
入力信号回路に挿入された抵抗３０と、その増幅
器１０側とグランドとの間に接続されたトランジ
スタ３２を備える。３４はトランジスタ３２の制
御用トランジスタで、そのベースは抵抗２８を介
して振幅検出回路DETの出力端に、エミツタは
トランジスタ３２のベースに、そしてコレクタは
抵抗３６を介して電源＋Ｂへ接続される。３８
は、増幅器１０の入力端とアツテネータATTの
出力端との間に接続されたカツプリングコンデン
サである。以上は従来回路であり、本考案では
かゝる回路の抵抗３０の出力側とグランドとの間
に極性が逆な一対のダイオード４０，４２を並設
する。 In the drawing, 10 is an amplifier, 12 is an input end, and 14 is an output end. Dashed line frame DET is amplitude (output level)
The detection circuit includes a rectifying and smoothing circuit consisting of a potentiometer 16 connected between the output end and ground, a capacitor 18 connected to its sliding arm, diodes 20, 22, a capacitor 24, and a resistor 26. The dashed line frame ATT is an electronic attenuator.
It includes a resistor 30 inserted into the input signal circuit, and a transistor 32 connected between the amplifier 10 side and ground. 34 is a control transistor for the transistor 32; its base is connected to the output terminal of the amplitude detection circuit DET via a resistor 28, its emitter is connected to the base of the transistor 32, and its collector is connected to the power supply +B via a resistor 36. 38
is a coupling capacitor connected between the input terminal of the amplifier 10 and the output terminal of the attenuator ATT. The above is a conventional circuit, and in the present invention, a pair of diodes 40 and 42 with opposite polarities are arranged in parallel between the output side of the resistor 30 of such a circuit and the ground.
先ずダイオード４０，４２を除いた本回路の動
作を説明するに、端子１２に音声信号が入力する
と、該信号はアツテネータATTおよびコンデン
サ３８を通して増幅器１０に入り、増幅されて出
力端１４に出る。この増幅出力はダイオード２
０，２２、コンデンサ１８，２４で整流、平滑化
され、増幅された音声入力のレベルを示す信号と
なつてトランジスタ３４，３２に加わる。例えば
増幅された音声入力が大であれば振幅検出回路
DETの出力は大きく、トランジスタ３４，３２
には大きなベース電流が流れ（３２には更に３４
で増幅されたベース電流が流れ）てトランジスタ
３２のコレクタ、エミツタ間等価抵抗は減少し、
抵抗３０とトランジスタ３２の該等価抵抗で分圧
回路を構するアツテネータATTの分圧比は大と
なり、増幅器１０への入力信号は減少し、つれて
増幅器出力は減少する。増幅された音声入力が小
である場合はこの逆で、従つて第２図に示すよう
に音声入力がある範囲で大、小に変つても増幅器
出力レベルはほゞ一定となる。 First, the operation of this circuit excluding the diodes 40 and 42 will be described. When an audio signal is input to the terminal 12, the signal enters the amplifier 10 through the attenuator ATT and the capacitor 38, is amplified, and outputted to the output terminal 14. This amplified output is diode 2
0, 22, rectified and smoothed by capacitors 18, 24, and is applied to transistors 34, 32 as a signal indicating the level of the amplified audio input. For example, if the amplified audio input is large, the amplitude detection circuit
The output of DET is large, transistors 34, 32
A large base current flows through (32 has an additional 34
The base current amplified by flows), and the equivalent resistance between the collector and emitter of the transistor 32 decreases,
The voltage dividing ratio of the attenuator ATT, which constitutes a voltage dividing circuit with the equivalent resistances of the resistor 30 and the transistor 32, becomes large, the input signal to the amplifier 10 decreases, and the amplifier output decreases accordingly. When the amplified audio input is small, the opposite is true; therefore, as shown in FIG. 2, even if the audio input changes from high to low within a certain range, the amplifier output level remains approximately constant.
AGCアンプでは、かゝる利得制御が行なわれ
るが、それはある時定数をもつてなされる。この
時定数は主としてコンデンサ２４の充放電により
定まり、該コンデンサの充電回路の時定数がアタ
ツクタイム（立上りの急な過大入力に対し、出力
振幅が定常状態に近い、ある定められた値におち
つくまでに要する時間）を、また放電回路の時定
数がリカバリタイム（過大な入力信号が消滅した
後、利得が定常状態に近いある定められた値に回
復するまでに要する時間）を決定する。図示回路
から明らかなようにコンデンサ２４の充電はダイ
オード２２（順方向抵抗小）により直接行なわれ
るので充電時定数従つてアタツクタイムは小、該
コンデンサの放電は抵抗２６と、抵抗２８（これ
等の抵抗はダイオード２２の順方向抵抗よりもは
るかに大）およびトランジスタ３４，３２のベー
ス・エミツタ回路を通して行なわれるので放電時
定数従つてリカバリタイムは大である。勿論これ
らの抵抗の値を小にすればリカバリタイムは小に
なるが、これが小であると所謂息つき現象が生じ
たりして聴感を悪くするのでリカバリタイムには
適正値があり、通話用では0.5秒、音楽では１〜
２秒などの値が通常採用される。 Such gain control is performed in an AGC amplifier, but it is done with a certain time constant. This time constant is determined mainly by the charging and discharging of the capacitor 24, and the time constant of the charging circuit for the capacitor is the attack time (in response to an excessive input with a sudden rise, until the output amplitude settles to a certain predetermined value close to a steady state). The time constant of the discharge circuit determines the recovery time (the time required for the gain to recover to a predetermined value close to steady state after the excessive input signal disappears). As is clear from the illustrated circuit, the capacitor 24 is charged directly by the diode 22 (low forward resistance), so the charging time constant and attack time are small, and the capacitor is discharged by the resistors 26 and 28 (these resistors). is much larger than the forward resistance of diode 22) and the base-emitter circuit of transistors 34 and 32, so the discharge time constant and hence the recovery time are large. Of course, if the values of these resistors are made small, the recovery time will be shortened, but if this is too small, the so-called breathing phenomenon will occur and the hearing will be impaired, so there is an appropriate value for the recovery time, and it is not suitable for calls. 0.5 seconds, 1~ for music
A value such as 2 seconds is usually adopted.
しかしながらリカバリタイムが大（上記程度）
であると、過大入力時に問題がある。即ち端子１
２にクリツク音（これは標準入力よりたとえば
50dBも高い）などの過大雑音が入力すると、振
幅検出回路DETのコンデンサ２４はアタツクタ
イムに関連した時間でその最大電圧まで速やかに
充電され、アツテネータATTのトランジスタ３
２のコレクタ・エミツタ間はインピーダンスが低
下して、増幅器出力が定められた値を超えないよ
うにATTの減衰量が増大する。こうして速やか
に増幅器１０への過大入力は抑えられ、出力は適
正値に戻されるが、過大入力消滅後はコンデンサ
２４の放電は徐々にしか（0.5〜数秒の時定数で
しか）行なわれないから、過大入力が消滅した直
後はアツテネータATTは過度に入力を絞る状態
（例えば50dB減衰量が増大）になつている。第３
図はこれを説明する図でａが入力信号、ｂが出力
信号である。時点t1で過大入力があると、これは
振幅検出回路DETおよびアツテネータATTによ
り速やかに制限され、出力は僅かな上昇にとどま
る（アタツクタイムに関連する初期振幅安定化期
間は図示省略）。時点t2で過大入力が消滅すると、
この時点ではコンデンサ２４は過充電、トランジ
スタ３２のコレクタエミツタ間は著しく低インピ
ーダンスの状態にあるので、通常レベルの入力信
号は過度に減衰され、（例えば50dB過大な入力に
対して標準出力となつている場合には減衰量は
50dB増大している）出力は部分Ａで示すように
一時的に途切れることになる。即ち入力が通話信
号なら、話の始めが欠けることになる。 However, the recovery time is long (about the same as above)
If so, there will be a problem when excessive input is made. That is, terminal 1
2 is a click sound (this is a click sound from the standard input, for example
When excessive noise (as high as 50 dB) is input, the capacitor 24 of the amplitude detection circuit DET is rapidly charged to its maximum voltage in a time related to the attack time, and the transistor 3 of the attenuator ATT is
The impedance between the collector and emitter of 2 is lowered, and the amount of attenuation of ATT is increased so that the amplifier output does not exceed a predetermined value. In this way, the excessive input to the amplifier 10 is quickly suppressed and the output is returned to its proper value, but after the excessive input disappears, the capacitor 24 is only gradually discharged (with a time constant of 0.5 to several seconds). Immediately after the excessive input disappears, the attenuator ATT is in a state where the input is excessively reduced (for example, the amount of attenuation increases by 50 dB). Third
The figure is a diagram explaining this, where a is an input signal and b is an output signal. If there is an excessive input at time t1 , this is quickly limited by the amplitude detection circuit DET and the attenuator ATT, and the output increases only slightly (the initial amplitude stabilization period associated with the attack time is not shown). When the excessive input disappears at time t 2 ,
At this point, the capacitor 24 is overcharged and the impedance between the collector and emitter of the transistor 32 is extremely low, so the normal level input signal is excessively attenuated (for example, if the input is 50 dB too high, the standard output becomes the standard output). , the attenuation is
The output (increased by 50 dB) will be temporarily interrupted as shown in section A. That is, if the input is a speech signal, the beginning of the speech will be missing.
本考案はかゝる点を改善するもので、ダイオー
ド４０，４２が過大入力のクリツパとして働ら
く。ダイオード４０，４２をシリコンダイオード
とすると、印加電圧が0.5V以下なら該ダイオー
ドはほぼオフ、印加電圧が0.5V以上ならば印加
電圧の増大にしたがつて著しくインピーダンスが
低下し、出力を0.5Vより若干高い値に制限する。
増幅器１０の入力は0.5V以下とすると、通常時
はダイオード４０，４２はオフであつてないのと
同じである。従つて本回路は前述の動作を行な
い、そして過大入力が入るとダイオード４０，４
２はオン（詳しくは入力交流信号の正半波で４２
が、負半波で４０がオン）となつて出力信号振幅
を0.5Vより若干高い値に制限する。従つて増幅
器１０に過大入力が入ることはなく、従つてコン
デンサ２４はダイオード４０，４２がないときの
ように高い電圧には充電されず（アツテネータの
減衰量が適正値に回復する迄に要する時間が短縮
されるのみならず）、アツテネータATTが正常に
戻つた入力信号を一時的にもせよ聴きとれないほ
ど過度に減衰することはない。例えばクリツパレ
ベルを標準入力レベルより10dB高い状態に設定
した場合は利得低下は10dBに過ぎず、若干の音
量低下にとどまる。 The present invention improves this point, and the diodes 40 and 42 act as clippers for excessive input. If the diodes 40 and 42 are silicon diodes, if the applied voltage is 0.5V or less, the diodes will be almost off, and if the applied voltage is 0.5V or more, the impedance will drop significantly as the applied voltage increases, and the output will be lower than 0.5V. Limit to a slightly higher value.
When the input of the amplifier 10 is set to 0.5V or less, it is the same as if the diodes 40 and 42 are off during normal times. Therefore, this circuit operates as described above, and when an excessive input is applied, the diodes 40 and 4
2 is on (in detail, 42 is the positive half wave of the input AC signal)
However, in the negative half wave, 40 is on), limiting the output signal amplitude to a value slightly higher than 0.5V. Therefore, no excessive input is applied to the amplifier 10, and the capacitor 24 is not charged to a high voltage as it would be without the diodes 40 and 42 (the time required for the attenuation amount to recover to its proper value) In addition, the attenuator ATT does not attenuate the normalized input signal so much that it becomes inaudible, even temporarily. For example, when the clipper level is set to 10 dB higher than the standard input level, the gain decreases by only 10 dB, and the volume decreases only slightly.
AGCアンプの特徴は信号レベルに応じて利得
を変えることであり、クリツパのように信号の所
定振幅以上を切除するのではなく、該信号の全体
に対して被調整利得を作用させる、従つてクリツ
プによる歪は発生しない点にあるが、本回路でも
アタツクタイム経過後はATTの減衰量増大によ
りダイオード４０，４２に加わる信号の振幅をダ
イオードの立上り電圧以下に引き下げるように動
作し、正常時は単なるAGCアンプであるから、
かゝる利点を有する。過大入力時にはクリツパ４
０，４２が動作するからクリツプ歪は発生する
が、勿論、この入力は雑音であるから歪は問題で
ない。またアタツクタイム経過前はトランジスタ
３４，３２はオフであり、アツテネータATTは
動作しないので、増幅器１０に一時的に過大入力
が入る可能性があるが、ダイオード４０，４２を
設けておくとかゝる場合でも入力制限を行ない、
増幅器１０への過大入力侵入を阻止する。なお、
過大妨害信号持続期間中はAGC回路、クリツパ
の有無にかかわらず、希望信号は該妨害信号にマ
スクされる。これは止むを得ないことであり、そ
して妨害信号の持続期間はリカバリタイムなどに
比較しても短いことが多い。そしてプレストーク
通話装置で発生する釦操作時のクリツクノイズは
通話に先立つて発生するものであるから、それ自
体が妨害を与えることは先ずない。 A feature of the AGC amplifier is that it changes the gain according to the signal level, and instead of clipping the signal above a predetermined amplitude like a clipper, it applies the adjusted gain to the entire signal. However, after the attack time has elapsed, this circuit also operates to reduce the amplitude of the signal applied to the diodes 40 and 42 to below the rising voltage of the diodes by increasing the attenuation of ATT, and in normal operation it is a simple AGC. Since it is an amplifier,
It has such advantages. Clipper 4 in case of excessive input
0 and 42 operate, clipping distortion occurs, but of course this input is noise, so distortion is not a problem. Also, before the attack time elapses, the transistors 34 and 32 are off and the attenuator ATT does not operate, so there is a possibility that an excessive input may temporarily enter the amplifier 10, but even if the diodes 40 and 42 are provided, Restrict input,
To prevent excessive input from entering the amplifier 10. In addition,
During the duration of the excessive interference signal, the desired signal is masked by the interference signal regardless of the presence or absence of the AGC circuit and clipper. This is unavoidable, and the duration of the interference signal is often short compared to the recovery time. Since the click noise that occurs when a button is operated in a press-talk telephone device occurs prior to a telephone call, it is unlikely to cause any interference by itself.
以上説明したように本考案によれば、リカバリ
タイムは変更することなく過大入力消滅後の信号
先端部欠落を回避でき、有効である。 As explained above, according to the present invention, it is possible to avoid the loss of the leading edge of the signal after the excessive input disappears without changing the recovery time, which is effective.
第１図は本考案の実施例を示す回路図、第２図
および第３図は動作説明図である。
図面で１０は増幅器、DETは整流平滑回路、
ATTは利得制御回路、３０，４０，４２はクリ
ツパである。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are operation diagrams. In the drawing, 10 is an amplifier, DET is a rectifier and smoothing circuit,
ATT is a gain control circuit, and 30, 40, and 42 are clippers.
Claims (1)
を整流する整流回路と、該整流回路の出力を平滑
する平滑回路の出力電圧に応じて前記入力信号を
減衰する利得制御回路からなり、前記平滑回路の
充電時定数で定まる小さいアタツクタイムで前記
利得制御回路の減衰度を大きくして、前記平滑回
路の放電時定数で定まり前記アタツクタイムより
大きいリカバリタイムで前記利得制御回路の減衰
度を小さくする自動利得制御付き増幅回路におい
て、 前記利得制御回路が減衰動作を行う回路部分
に、所定レベル未満の信号では動作せず、該所定
レベル以上の信号で動作して信号レベルを制限す
るリクツパを接続したことを特徴とする自動利得
制御付き増幅回路。[Claims for Utility Model Registration] An amplifier that amplifies an input signal, a rectifier circuit that rectifies the output of the amplifier, and a gain that attenuates the input signal according to the output voltage of the smoothing circuit that smoothes the output of the rectifier circuit. The control circuit is configured to increase the attenuation degree of the gain control circuit with a small attack time determined by the charging time constant of the smoothing circuit, and increase the attenuation degree of the gain control circuit with a recovery time determined by the discharge time constant of the smoothing circuit and larger than the attack time. In an amplifier circuit with automatic gain control that reduces the degree of attenuation, the gain control circuit has a circuit section in which the attenuation operation is performed such that it does not operate on signals below a predetermined level, but operates on signals above the predetermined level to limit the signal level. An amplifier circuit with automatic gain control, characterized in that it is connected to a receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3766882U JPS58141616U (en) | 1982-03-17 | 1982-03-17 | Amplifier circuit with automatic gain control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3766882U JPS58141616U (en) | 1982-03-17 | 1982-03-17 | Amplifier circuit with automatic gain control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58141616U JPS58141616U (en) | 1983-09-24 |
| JPH046258Y2 true JPH046258Y2 (en) | 1992-02-20 |
Family
ID=30049046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3766882U Granted JPS58141616U (en) | 1982-03-17 | 1982-03-17 | Amplifier circuit with automatic gain control |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58141616U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370424A (en) * | 1976-12-06 | 1978-06-22 | Hitachi Ltd | Speaker protecting circuit |
-
1982
- 1982-03-17 JP JP3766882U patent/JPS58141616U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370424A (en) * | 1976-12-06 | 1978-06-22 | Hitachi Ltd | Speaker protecting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58141616U (en) | 1983-09-24 |
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