JPH0461314A - Method for forming pattern on semiconductor wafer - Google Patents
Method for forming pattern on semiconductor waferInfo
- Publication number
- JPH0461314A JPH0461314A JP17355390A JP17355390A JPH0461314A JP H0461314 A JPH0461314 A JP H0461314A JP 17355390 A JP17355390 A JP 17355390A JP 17355390 A JP17355390 A JP 17355390A JP H0461314 A JPH0461314 A JP H0461314A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- dicing lines
- wafer
- base film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 21
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体ウェハ(以下ウェハという)のパタ
ーン形成方法に関するもので、この種のものFi5例え
ば電子材料の製造の分野で利用され。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming patterns on semiconductor wafers (hereinafter referred to as wafers), and is used in the field of manufacturing electronic materials, for example.
ウェハの回路パターンの形成等に用いられる。Used for forming circuit patterns on wafers, etc.
Wc6図は従来のウェハのパターン形成方法を示すウェ
ハの上面図である。図に示すようにウェハ(1)の内部
にダイシングライン(4)及び回路パターン(5)を同
時に形成する。Figure Wc6 is a top view of a wafer showing a conventional wafer pattern forming method. As shown in the figure, dicing lines (4) and circuit patterns (5) are simultaneously formed inside the wafer (1).
従来のウェハのパターン形成方法は1以上のように行わ
れているので、ダイシングラインと回路パターンを同時
に形成するため、第6図に示すように、下地膜に残留ス
トレスが残っている場合。Since conventional wafer pattern formation methods are performed in one or more ways, dicing lines and circuit patterns are formed at the same time, so that residual stress remains in the underlying film, as shown in FIG.
感光性レジスト(以下レジストという)のパターンに影
響をおよぼし、レジストのパターンが寸法変動し、安定
性、信頼性に欠ける等の問題点があった。This affects the pattern of the photosensitive resist (hereinafter referred to as resist), resulting in dimensional variations in the resist pattern, resulting in problems such as lack of stability and reliability.
この発明は上記のような問題点を解決するためなされた
もので、下地膜のストレスを低減することによって信頼
性の高いウェハのパターン形成方法を得ることを目的と
する。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a highly reliable wafer pattern forming method by reducing the stress on the underlying film.
この発明は、レジストを付したウェハに露光。 This invention exposes a wafer with a resist attached.
現像を行うパターン形成方法において、ダイシングライ
ンのみを露光現像し、エツチングを行う第1の工程と、
上記第1の工程後、レジストを除去し、再びレジストを
付し、回路パターンをm党。In a pattern forming method that involves development, a first step of exposing and developing only the dicing lines and etching;
After the first step, the resist is removed and a resist is applied again to form a circuit pattern.
現偉するN2の工程を含む方法によりウエノ1のパター
ン形成を行う。Patterning of the wafer 1 is performed by a method including the N2 step, which is currently used.
この発明によるウェハのパターン形成方法は、下地膜の
ストレスを低減することができ、従って仕上がりの寸法
変動を抑えることができる。The wafer pattern forming method according to the present invention can reduce stress on the base film, and therefore can suppress finished dimensional variations.
以下、この発明の一実施例を図釦ついて説明する。第1
図かいし第4図はウェハのパターン形成方法の工程に従
って示す図で、第1図は、処理を行う前のウェハの斜視
図、第2図は第1図のウェハに写真製版を行い、ダイシ
ングラインのみのエツチングを行り光状態を示すウェハ
の斜視図%第3図は第2図の状態からレジストを取り除
いた状態のWc2図のム−Aにおける断面図、第4図は
第3図の状態からレジストを付し1回路パターンをパタ
ーニングしたときの第2図の八・ムにおける断面図であ
る。図において、(1)はウエノ・%(2)はレジス)
、(N1は下地膜、(4)はダイシングラインである0
次に動作について説明する。ウエノ(1)は第2図に示
すごとくダイシングライン(4)のみをノ(ターニング
し、レジストを除去する。その結果、ストレスのある下
地膜(3)をダイシングライン(4)Kよって第3図に
示すごとく小さく分割することにより、下地膜(3)の
ストレスを分散させることができる。Hereinafter, one embodiment of the present invention will be explained with reference to the diagrams. 1st
Figures 4 to 4 are diagrams showing the steps of the wafer pattern forming method, in which Figure 1 is a perspective view of the wafer before processing, and Figure 2 shows the wafer in Figure 1 after photolithography and dicing. A perspective view of a wafer showing the optical state after line-only etching % Figure 3 is a sectional view taken along line A of Figure Wc2 with the resist removed from the state shown in Figure 2; FIG. 3 is a sectional view taken along line 8-m in FIG. 2 when a resist is applied from the state and one circuit pattern is patterned. In the figure, (1) is Ueno, % (2) is Regis)
, (N1 is the base film, and (4) is the dicing line.) Next, the operation will be explained. As shown in Figure 2, Ueno (1) turns only the dicing line (4) and removes the resist. As a result, by dividing the stressed base film (3) into smaller pieces along the dicing lines (4)K as shown in FIG. 3, the stress in the base film (3) can be dispersed.
次に第4図に示すごとく第2のレジスト(2)を付し。Next, a second resist (2) is applied as shown in FIG.
回路パターンのパターニングを行う。下地膜(3)のス
トレスが大きいとレジストがはがれやすくなり。Patterning the circuit pattern. If the stress on the base film (3) is large, the resist will easily peel off.
横方向に広がりやすい。ダイシングライン(4)を最初
に形成することで横方向のエツチングを抑えることがで
きる。Easy to spread laterally. By first forming the dicing lines (4), lateral etching can be suppressed.
以上のように、この発明によれば、ウエノ・の回路パタ
ーンのパターニングに先立ってダイシング2インのみの
パターニングを行うことにより下地膜のストレスを低減
することができるので、レジストのはがれを抑制し、安
定かつ潜頼性の高いウェハのパターンを形成できる効果
がある0As described above, according to the present invention, the stress on the base film can be reduced by patterning only 2-in dicing prior to the patterning of the Ueno circuit pattern, so peeling of the resist can be suppressed, Effective in forming stable and reliable wafer patterns0
第1図ないし第4図はこの発明の一実施例による半導体
ウェハのパターン形成方法の工程に従って示す図で、N
1図は処理を行う前のウエノ・の斜視図、 第2図はダ
イシングラインのみのエツチングを行った状態のウェハ
の斜視図、第3図は第2図の状態からレジストを取り除
いた状態の第2図のA・ムにおける断面図、第4図は回
路パターンをパターニングした状態の第2図のム8Aに
おける断面図%第5図は従来のウェハのパターン形成方
法を示すウェハの上面図である。
図において、(1)はウェハ、(2)はレジスト%(3
)は下地膜、(4)はダイシングラインである。
なお、図中、同一符号は同一、又は相当部分を示す。FIGS. 1 to 4 are diagrams showing steps of a method for forming a pattern on a semiconductor wafer according to an embodiment of the present invention.
Figure 1 is a perspective view of the wafer before processing, Figure 2 is a perspective view of the wafer after etching only the dicing lines, and Figure 3 is a perspective view of the wafer after the resist has been removed from the state shown in Figure 2. 2 is a cross-sectional view at A and M in FIG. 2, and FIG. 4 is a cross-sectional view at A and M in FIG. 2 in a state where a circuit pattern has been patterned. . In the figure, (1) is the wafer, (2) is the resist% (3
) is the base film, and (4) is the dicing line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ストを付し、上記感光性レジストを付した半導体ウェハ
に露光、現像を行うパターン形成方法において、ダイシ
ングラインのみを露光、現像し、エッチングを行う第1
の工程と、上記第1の工程後、感光性レジストを除去し
、再び感光性レジストを付し、回路パターンを露光、現
像する。 第2の工程を含む半導体ウェハのパターン形成方法。[Claims] A pattern forming method in which a photosensitive resist is applied to the entire surface of a semiconductor wafer on which a pattern is to be formed, and the semiconductor wafer with the photosensitive resist applied is exposed and developed, wherein only the dicing lines are exposed and developed. The first step is to perform etching.
After the step and the first step, the photosensitive resist is removed, a photosensitive resist is applied again, and the circuit pattern is exposed and developed. A method for forming a pattern on a semiconductor wafer, including a second step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17355390A JPH0461314A (en) | 1990-06-29 | 1990-06-29 | Method for forming pattern on semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17355390A JPH0461314A (en) | 1990-06-29 | 1990-06-29 | Method for forming pattern on semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0461314A true JPH0461314A (en) | 1992-02-27 |
Family
ID=15962677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17355390A Pending JPH0461314A (en) | 1990-06-29 | 1990-06-29 | Method for forming pattern on semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0461314A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170304A (en) * | 1993-12-14 | 1995-07-04 | Chikyu Kagaku Sogo Kenkyusho:Kk | Geological structure investigating device |
-
1990
- 1990-06-29 JP JP17355390A patent/JPH0461314A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170304A (en) * | 1993-12-14 | 1995-07-04 | Chikyu Kagaku Sogo Kenkyusho:Kk | Geological structure investigating device |
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