JPH0460993A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0460993A JPH0460993A JP2167210A JP16721090A JPH0460993A JP H0460993 A JPH0460993 A JP H0460993A JP 2167210 A JP2167210 A JP 2167210A JP 16721090 A JP16721090 A JP 16721090A JP H0460993 A JPH0460993 A JP H0460993A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- power supply
- supply voltage
- delay
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 230000003111 delayed effect Effects 0.000 claims abstract description 15
- 238000001514 detection method Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 abstract description 8
- 238000005265 energy consumption Methods 0.000 abstract 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 33
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体メモリ装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.
従来の技術
最近、半導体メモリ装置の利用が高まり、これらの半導
体メモリ装置の使用にあたり高電源電圧でも動作時消費
電力が少ないものが要求されている。この動作時消費電
力の一つとしてアドレス信号遷移に消費されるものがあ
り、受は付けるアドレス信号遷移を少なくすることが重
要である。第２図（Ａ）は従来の半導体メモリ装置の回
路図、第２図（Ｂ）は第２図（Ａ）の回路図の外部入力
信号及び内部信号の信号波形図、第２図（Ｃ）は第２図
（Ａ）の回路図の内部信号ＣＬにみられる外部入力信号
ＲＡＳからの遅延時間ｔａ電源電圧ＶＣＣとの関係図で
ある。ＲＡＳ （ロウアドレスストローブ）、ＣＡＳ（
カラムアドレスストローブ）は外部入力信号、ＣＬはカ
ラムアドレスの受は付は制御の内部信号、Ｎｌ、Ｎ２は
ノード名、ｔは外部入力信号ＲＡＳから内部信号ＣＬま
での遅延時間である。動作について、第２図（Ａ）の回
路図と第２図（Ｂ）の信号波形図を参照しながら説明す
る。2. Description of the Related Art Recently, the use of semiconductor memory devices has increased, and when using these semiconductor memory devices, there is a demand for devices that consume less power during operation even at a high power supply voltage. One of the power consumptions during operation is that consumed by address signal transitions, and it is important to reduce the number of address signal transitions that are applied to the receiver. FIG. 2(A) is a circuit diagram of a conventional semiconductor memory device, FIG. 2(B) is a signal waveform diagram of external input signals and internal signals of the circuit diagram of FIG. 2(A), and FIG. 2(C) is a circuit diagram of a conventional semiconductor memory device. is a relationship diagram between the delay time ta from the external input signal RAS seen in the internal signal CL in the circuit diagram of FIG. 2(A) and the power supply voltage VCC. RAS (row address strobe), CAS (
Column address strobe) is an external input signal, CL is an internal control signal for column address reception, Nl and N2 are node names, and t is a delay time from external input signal RAS to internal signal CL. The operation will be explained with reference to the circuit diagram of FIG. 2(A) and the signal waveform diagram of FIG. 2(B).
ノードＮ１の信号は、外部入力信号ＲＡＳの遅延信号と
外部入力信号ＲＡＳとの論理和の否定信号で、ノードＮ
２の信号は、外部入力信号ＣＡＳの遅延信号と外部入力
信号ＣＡＳとの論理和信号で、内部信号ＣＬは、ノード
Ｎ１の信号とノードＮ２の信号との論理積の否定信号で
ある。つまり、内部信号ＣＬは、外部入力信号ＲＡＳが
論理電圧゛Ｌ“で外部入力信号ＣＡＳが論理電圧”Ｌ”
のときに論理電圧“Ｌ“になり、外部入力信号ＲＡＳの
立ち下がりから遅延して立ち下がり外部入力信号ＣＡＳ
の立ち下がりから遅延して立ち上がる信号である。この
内部信号ＣＬが論理電圧“Ｌ゛′である時がカラムアド
レスの受は付は期間であり、カラムアドレスの受は付は
期間中のアドレス信号遷移の回数が増すごとに消費電力
も増加する。外部入力信号ＲＡＳの立ち下がりから内部
信号ＣＬの立ち下がりまでの遅延時間ｔと電源電圧ＶＣ
Ｃとの関係を示したものが第２図（Ｃ）で遅延時間ｔは
電源電圧Ｖｃｃが高くなるにつれて短くなり短調減少の
関係になる。The signal at the node N1 is a negative signal of the logical sum of the delayed signal of the external input signal RAS and the external input signal RAS.
The signal No. 2 is a logical sum signal of the delayed signal of the external input signal CAS and the external input signal CAS, and the internal signal CL is a negative signal of the logical product of the signal at the node N1 and the signal at the node N2. In other words, the internal signal CL has the external input signal RAS at the logic voltage "L" and the external input signal CAS at the logic voltage "L".
, the logic voltage becomes “L” and falls with a delay from the falling edge of the external input signal RAS.
This is a signal that rises with a delay from the fall of . When this internal signal CL is at the logic voltage "L", the column address is accepted during the period, and the power consumption increases as the number of address signal transitions increases during the column address acceptance period. .Delay time t from the fall of external input signal RAS to the fall of internal signal CL and power supply voltage VC
FIG. 2(C) shows the relationship between the delay time t and the delay time t, which becomes shorter as the power supply voltage Vcc increases, resulting in a minor-key decreasing relationship.
発明が解決しようとする課題
このような従来の半導体メモリ装置では、電源電圧が高
くなると、外部入力信号ＲＡＳの立ち下がりから内部信
号ＣＬの立ち下がりまでの遅延時間が短くなり、ウラム
アドレスの受は付は期間が長くなるため、アドレス信号
遷移の受は付は回数も増すことがあり、消費電力も増加
するという問題があった。Problems to be Solved by the Invention In such conventional semiconductor memory devices, when the power supply voltage increases, the delay time from the fall of the external input signal RAS to the fall of the internal signal CL becomes shorter, and the reception of the URAM address becomes shorter. Since the period of reception becomes longer, the number of times of reception and determination of address signal transitions may increase, which poses a problem in that power consumption also increases.
課題を解決するための手段
このような課題を解決するために、本発明は、電源電圧
検知回路、第１及び第２の遅延回路を有し、前記第１の
遅延回路が外部からの入力信号の遅延信号を発生し、電
源電圧が高くなったときに、前記電源電圧検知回路によ
り前記第２の遅延回路が作動し、前記第２の遅延回路が
外部からの入力信号の遅延信号を発生することにより、
前記第１の遅延回路による遅延信号より遅延した遅延信
号を発生させる回路を有する半導体メモリ装置とする。Means for Solving the Problems In order to solve these problems, the present invention includes a power supply voltage detection circuit, first and second delay circuits, and the first delay circuit receives an external input signal. When the power supply voltage becomes high, the second delay circuit is activated by the power supply voltage detection circuit, and the second delay circuit generates a delayed signal of an input signal from the outside. By this,
A semiconductor memory device includes a circuit that generates a delayed signal delayed from a delayed signal by the first delay circuit.
作用
本発明の半導体メモリ装置によれば、電源電圧が高くな
ったときに電源電圧検知回路により所定の遅延回路が作
動し、電源電圧が高くなってもカラムアドレスの受は付
は時間が長くならず、アドレス信号遷移の受は付は回数
も増えず消費電力が増加しない低消費電力の半導体メモ
リ装置とすることができる。According to the semiconductor memory device of the present invention, a predetermined delay circuit is activated by the power supply voltage detection circuit when the power supply voltage becomes high, so that even if the power supply voltage becomes high, it takes a long time to receive a column address. First, it is possible to obtain a semiconductor memory device with low power consumption, in which the number of receptions of address signal transitions does not increase, and power consumption does not increase.
実施例
以下、本発明を実施例によって説明する。第１図（Ａ）
は本発明の半導体メモリ装置の一実施例の回路図、第１
図（Ｂ）は第１図（Ａ）の回路図のノード名Ｎ３の電圧
と電源電圧Ｖｃｃとの関係図、第１図（Ｃ）は第１図（
Ａ）の回路図の外部入力信号及び内部信号の信号波形図
、第１図（Ｄ）は第１図（Ａ）の回路図の内部信号ＣＬ
にみられる外部入力信号Ｒ’ＡＳからの遅延時間ｔと電
源電圧ＶＣＣとの関係図である。なお、図中の符号で、
ＲＡＳ（ロウアドレスストローブ）、ＣＡＳ （カラム
アドレスストローブ）は外部入力信号、ＣＬはカラムア
ドレスの受は付は制御の内部信号、１は電源電圧検知回
路、Ｎｌ、Ｎ２．Ｎ３はノード名、ｔは外部入力信号Ｒ
ＡＳから内部信号ＣＬまでの遅延時間を表している。動
作について、第１図（Ａ）の回路図、第１図（Ｂ）のノ
ード名Ｎ３の電圧と電源電圧ＶＣＣとの関係図、第１図
（Ｃ）の信号波形図を参照しながら説明する。ノードＮ
１の信号は、外部入力信号ＲＡＳの遅延信号と外部入力
信号ＲＡＳとの論理和の否定信号で、前記外部入力信号
ＲＡＳの遅延信号の遅延時間は電源電圧検知回路１から
出力されるノードＮ３の論理電圧レベルによってかわり
、電源電圧ＶＣＣが低く、ノードＮ３の論理電圧が“Ｌ
”であるときは作動する遅延用否定回路の段数が少なく
、遅延時間は短い。電源電圧ＶＣＣが高（なり、ノード
Ｎ３の論理電圧がＩ−１”であるときは作動する遅延用
否定回路の段数が多く遅延時間は長くなり、ノードＮ１
の信号の立ち上がりがより遅延する。ノードＮ２の信号
は、外部入力信号ＣＡＳの遅延信号と外部入力信号ＣＡ
Ｓとの論理和信号で、内部信号ＣＬは、ノードＮ１の信
号とノードＮ２の信号との論理積の否定信号である。つ
まり、内部信号ＣＬは、外部入力信号ＲＡＳが論理電圧
“Ｌ”で外部入力信号ＣＡＳが論理電圧゛Ｌ”のときに
論理電圧”°Ｌ゛。EXAMPLES Hereinafter, the present invention will be explained by examples. Figure 1 (A)
1 is a circuit diagram of an embodiment of the semiconductor memory device of the present invention.
Figure 1(B) is a relationship diagram between the voltage of node name N3 in the circuit diagram of Figure 1(A) and the power supply voltage Vcc, and Figure 1(C) is a diagram of the relationship between the voltage of node name N3 in the circuit diagram of Figure 1(A) and the power supply voltage Vcc.
Figure 1 (D) is a signal waveform diagram of the external input signal and internal signal in the circuit diagram of A), and the internal signal CL of the circuit diagram of Figure 1 (A).
FIG. 2 is a diagram showing the relationship between the delay time t from the external input signal R'AS and the power supply voltage VCC as seen in FIG. In addition, the symbols in the figure are
RAS (row address strobe) and CAS (column address strobe) are external input signals, CL is an internal control signal for column address reception, 1 is a power supply voltage detection circuit, Nl, N2 . N3 is the node name, t is the external input signal R
It represents the delay time from AS to internal signal CL. The operation will be explained with reference to the circuit diagram in FIG. 1(A), the relationship diagram between the voltage of node name N3 and power supply voltage VCC in FIG. 1(B), and the signal waveform diagram in FIG. 1(C). . Node N
The signal 1 is a negative signal of the logical sum of the delayed signal of the external input signal RAS and the external input signal RAS, and the delay time of the delayed signal of the external input signal RAS is equal to Depending on the logic voltage level, the power supply voltage VCC is low and the logic voltage of node N3 is “L”.
``, the number of stages of the delay NOT circuit that operates is small, and the delay time is short.When the power supply voltage VCC is high (and the logic voltage of node N3 is I-1'', the number of stages of the delay NOT circuit that operates is short. Since the number of stages is large and the delay time is long, node N1
The rise of the signal is delayed. The signal at node N2 is a delayed signal of external input signal CAS and external input signal CA.
The internal signal CL is a logical sum signal with S, and is a negative signal of the logical product of the signal at the node N1 and the signal at the node N2. That is, the internal signal CL is a logic voltage "°L" when the external input signal RAS is a logic voltage "L" and the external input signal CAS is a logic voltage "L".
になり、外部入力信号ＲＡＳの立ち下がりから遅延して
立ち下がり、外部入力信号ＣＡＳの立ち下がりから遅延
して立ち上がる信号である。外部入力信号ＲＡＳの立ち
下がりから内部信号ＣＬの立ち下がりまでの遅延時間ｔ
と電源電圧ＶＣＣとの関係を示したものが第２図（Ｄ）
で遅延時間ｔは電源電圧ＶＣＣが高（なるにつれて短く
なるが、電源電圧ＶＣＣが５．ＯＶのところで遅延時間
ｔは不連続に長くなる。このように、広い電源電圧範囲
で遅延時間ｔの変化の少ない内部信号ＣＬを発生ずる回
路としている。この内部信号ＣＬが論理電圧”°Ｌ“で
ある時がカラムアドレスの受は付は期間であり、カラム
アドレスの受は付は期間中のアドレス信号遷移の回数が
増すごとに消費電力も増加するが、本発明では、電源電
圧が高くなってもカラムアドレスの受は付は期間が長く
ならず、アドレス信号遷移の受は付は回数も増えず、消
費電力が増加しない低消費電力の半導体メモリ装置を実
現している。This is a signal that falls with a delay from the fall of the external input signal RAS, and rises with a delay from the fall of the external input signal CAS. Delay time t from the fall of external input signal RAS to the fall of internal signal CL
Figure 2 (D) shows the relationship between and power supply voltage VCC.
The delay time t becomes shorter as the power supply voltage VCC becomes higher, but the delay time t becomes discontinuously longer when the power supply voltage VCC reaches 5.0V.In this way, the delay time t changes over a wide power supply voltage range. The circuit is designed to generate an internal signal CL with a small amount of noise.When this internal signal CL is at the logic voltage "°L", the column address reception is during the period, and the column address reception is the address signal during the period. Power consumption also increases as the number of transitions increases, but in the present invention, even if the power supply voltage increases, the period for accepting and attaching column addresses does not increase, and the number of times that accepting and attaching address signal transitions does not increase. , a low power consumption semiconductor memory device that does not increase power consumption has been realized.
発明の効果
以」二説明したように、本発明によると、高電源電圧で
も動作時消費電力が少ない半導体メモリ装置が供給でき
るという大きな効果が得られる。Advantages of the Invention As described above, the present invention has the great effect of providing a semiconductor memory device that consumes less power during operation even at a high power supply voltage.
第１図（Ａ）は本発明の半導体メモリ装置の一実施例の
回路図、第１図（Ｂ）は第１図（Ａ＞の回路図のノード
名Ｎ３の電圧と電源電圧ＶＣＣとの関係図、第１図（Ｃ
）は第１図（Ａ）の回路図の外部入力信号及び内部信号
の信号波形図、第１図（Ｄ＞は第１図（Ａ）の回路図の
外部入力信号ＲＡＳから内部信号ＣＬまでの遅延時間ｔ
と電源電圧ＶＣＣとの関係図にある。第２図（Ａ）は従
来の半導体メモリ装置の一実施例の回路図、第２図（Ｂ
）は第２図（Ａ）の回路図の外部入力信号及び内部信号
の信号波形図、第２図（Ｃ）は第２図（Ａ＞の回路図の
内部信号ＣＬ外部入力信号ＲＡＳからの遅延時間ｔａ電
源電圧ＶＣＣとの関係図である。
ＲＡＳ（ロウアドレスストローブ）、ＣＡＳ（カラムア
ドレスストローブ）・・・・・・外部入力信号、ＣＬ・
・・・・・内部信号、１・・・・・・電源電圧検知回路
、Ｎｌ、Ｎ２．Ｎ３・・・・・・ノード名、ｔ・・・・
・・外部入力信号ＲＡＳから内部信号ＣＬまでの遅延時
間。
代理人の氏名 弁理士 粟野重孝 ほか１名塚
←娩岩芝ＰFIG. 1(A) is a circuit diagram of an embodiment of the semiconductor memory device of the present invention, and FIG. 1(B) is the relationship between the voltage of node name N3 in the circuit diagram of FIG. 1(A>) and the power supply voltage VCC. Figure, Figure 1 (C
) is the signal waveform diagram of the external input signal and internal signal in the circuit diagram of Figure 1 (A), and Figure 1 (D> is the signal waveform diagram of the external input signal RAS to the internal signal CL in the circuit diagram of Figure 1 (A)). delay time t
The diagram shows the relationship between VCC and power supply voltage VCC. FIG. 2(A) is a circuit diagram of an embodiment of a conventional semiconductor memory device, and FIG. 2(B) is a circuit diagram of an embodiment of a conventional semiconductor memory device.
) is a signal waveform diagram of the external input signal and internal signal in the circuit diagram of Figure 2 (A), and Figure 2 (C) is the delay from the internal signal CL external input signal RAS in the circuit diagram of Figure 2 (A>). It is a relationship diagram between time ta and power supply voltage VCC.RAS (row address strobe), CAS (column address strobe)...External input signal, CL.
...Internal signal, 1...Power supply voltage detection circuit, Nl, N2. N3...Node name, t...
...Delay time from external input signal RAS to internal signal CL. Name of agent: Patent attorney Shigetaka Awano and 1 other person Tsuka ← Kaiiwa Shiba P
Claims (1)
記第１の遅延回路で外部からの入力信号の遅延信号を発
生し、電源電圧が所定値をこえた高くなったときに、前
記電源電圧検知回路により前記第２の遅延回路が作動し
、これにより、前記第１の遅延回路による入力信号の遅
延信号より遅延した遅延信号を発生させる回路を有する
ことを特徴とする半導体メモリ装置。It has a power supply voltage detection circuit, first and second delay circuits, the first delay circuit generates a delayed signal of an input signal from the outside, and when the power supply voltage becomes higher than a predetermined value, A semiconductor memory device comprising: a circuit in which the second delay circuit is activated by the power supply voltage detection circuit, thereby generating a delayed signal delayed from a delayed signal of an input signal by the first delay circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2167210A JPH0460993A (en) | 1990-06-25 | 1990-06-25 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2167210A JPH0460993A (en) | 1990-06-25 | 1990-06-25 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0460993A true JPH0460993A (en) | 1992-02-26 |
Family
ID=15845467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2167210A Pending JPH0460993A (en) | 1990-06-25 | 1990-06-25 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0460993A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845784B1 (en) * | 2006-12-08 | 2008-07-14 | 주식회사 하이닉스반도체 | Delay Apparatus for Delay Locked Loop |
-
1990
- 1990-06-25 JP JP2167210A patent/JPH0460993A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845784B1 (en) * | 2006-12-08 | 2008-07-14 | 주식회사 하이닉스반도체 | Delay Apparatus for Delay Locked Loop |
| US7710178B2 (en) | 2006-12-08 | 2010-05-04 | Hynix Semiconductor Inc. | Delay apparatus for delay locked loop |
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