JPH0453140A - Processing of silicon single crystalline wafer - Google Patents
Processing of silicon single crystalline waferInfo
- Publication number
- JPH0453140A JPH0453140A JP15930290A JP15930290A JPH0453140A JP H0453140 A JPH0453140 A JP H0453140A JP 15930290 A JP15930290 A JP 15930290A JP 15930290 A JP15930290 A JP 15930290A JP H0453140 A JPH0453140 A JP H0453140A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- silicon single
- processing
- region
- defect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 40
- 239000010703 silicon Substances 0.000 title claims abstract description 40
- 238000005247 gettering Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 37
- 238000011282 treatment Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 abstract description 20
- 239000001301 oxygen Substances 0.000 abstract description 20
- 230000002950 deficient Effects 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 67
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000012535 impurity Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000002244 precipitate Substances 0.000 description 7
- 125000004430 oxygen atom Chemical group O* 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000003672 processing method Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001556 precipitation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、シリコン単結晶ウェハを１Ｇ処理とＥＣ処理
を併用するゲッタリング処理に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to gettering processing for silicon single crystal wafers using both 1G processing and EC processing.
半導体装置の製造工程においては、チョクラルスキー法
（引き上げ法とも言う）により形成されたシリコン単結
晶インゴットをスライスして形成されたシリコン単結晶
ウェハが各プロセスの際侵入してくるＦｅ、Ｃｕ、Ｎｉ
等の重金属等の不純物に汚染された場合、この不純物に
よる悪影響を防止するために、例えば素子形成領域以外
のウェハ内に不純物を固定させるゲッタリング処理が用
いられている。このゲッタリング処理としては、ウェハ
裏面に例えば燐を拡散させる。あるいは、機械用ダメー
ジによるストレスを与えてウェハ裏面に不純物をゲッタ
リングするいわゆるＥＣ処理と、ウェハ内部に酸素析出
物を形成してウェハ内部に不純物をゲッタリングするい
わゆるＩＣ処理とが挙げられる。In the manufacturing process of semiconductor devices, a silicon single crystal wafer, which is formed by slicing a silicon single crystal ingot formed by the Czochralski method (also called the pulling method), is exposed to Fe, Cu, etc. that invade during each process. Ni
When contaminated with impurities such as heavy metals such as, for example, gettering processing is used to fix the impurities within the wafer in areas other than the element formation region in order to prevent the adverse effects of the impurities. As this gettering process, for example, phosphorus is diffused onto the back surface of the wafer. Alternatively, there are a so-called EC process in which impurities are gettered on the backside of the wafer by applying stress due to mechanical damage, and a so-called IC process in which impurities are gettered inside the wafer by forming oxygen precipitates inside the wafer.
従来、ゲッタリング処理としては、処理されるウェハの
縦断面を示す第２図（ａ）に示すように、シリコン単結
晶ウェハ３１裏面３１．ｂにストレスを与えてウェハ３
１裏面３１ｂに欠陥領域３２を形成し、この欠陥領域３
２に不純物をゲッタリングするＥＣ処理がある。なお、
第２図（ａ）において、３１ａはシリコン単結晶ウェハ
３１の表面である。このＥＣ処理にはＳｉ等の粒子をウ
ェハ裏面に衝突させストレスを与えて欠陥領域を形成し
不純物をゲッタリングするサンドブラスト法、ウェハ裏
面にポリシリコン膜を堆積しシリコン単結晶ウェハとポ
リシリコン膜の界面にストレスを与えて不純物をゲッタ
リングするポリシリコンコート法、ウェハ裏面にＰＳＧ
等のＰ含有の膜を堆積しＰを単結晶ウェハ中に拡散させ
、Ｐにより不純物をゲッタリングする燐拡散法、ウェハ
裏面にレーザ光を照射してＳｔを溶融させ再び凝固させ
ることによりストし・スを与えて欠陥領域３２を形成し
不純物をゲッタリングするレーザダメージ法等が挙げら
れる。Conventionally, as for gettering processing, as shown in FIG. Wafer 3 with stress applied to b
1, a defective region 32 is formed on the back surface 31b, and this defective region 3
2 is an EC process for gettering impurities. In addition,
In FIG. 2(a), 31a is the surface of the silicon single crystal wafer 31. In FIG. This EC process involves a sandblasting method in which particles such as Si are collided with the backside of the wafer to apply stress to form a defective area and getter the impurities, and a polysilicon film is deposited on the backside of the wafer to form a bond between the silicon single crystal wafer and the polysilicon film. Polysilicon coating method that applies stress to the interface to getter impurities, PSG on the back side of the wafer
The phosphorus diffusion method involves depositing a P-containing film such as P-containing film, diffusing P into a single crystal wafer, and gettering impurities with P. - A laser damage method in which a defective region 32 is formed by applying a gas and gettering impurities can be used.
また、その他の従来のゲッタリング処理としては、第２
図（ｂ）に示すように、高温熱処理・低温熱処理・高温
熱処理の三段熱処理によりシリコン単結晶ウェハ３１表
面３１ａから表面３１近傍の素子形成領域に無欠陥領域
３３（ＤＺ（デヌデットゾーン）Ｍ域とも言う）を形成
するとともに（裏面３１ｂから裏面３１ｂ近傍にも形成
される）、ウェハ３１内部に酸素析出物による欠陥領域
３４を形成し、この欠陥領域３４に不純物をゲッタリン
グするＩＣ処理がある。ここでの素子形成領域となる無
欠陥領域３３の深さＸは無欠陥領域３３に形成される半
導体素子の性能を左右し、例えば無欠陥領域３３の深さ
が浅くなり過ぎて欠陥領域３４が素子形成領域まで及ん
でいると、接合電流リークの原因となる。また、無欠陥
領域３３の深さが深過ぎると、ウェハ３１表面３１ａに
汚染した不純物のゲッタリング能力が低下する。欠陥は
、ウェハ３１中に固溶されている酸素をシリコン酸化物
として析出させることにより形成される。従って、無欠
陥領域３３の深さを制御する必要があり、一般に、５〜
１１００ｕ程度に制御されている。In addition, as other conventional gettering processing,
As shown in Figure (b), a defect-free region 33 (also known as DZ (denuded zone) M region) is formed from the surface 31a of the silicon single crystal wafer 31 to the element formation region near the surface 31 by three-stage heat treatment of high temperature heat treatment, low temperature heat treatment, and high temperature heat treatment. There is an IC process in which a defect region 34 due to oxygen precipitates is formed inside the wafer 31 and impurities are gettered into the defect region 34. The depth X of the defect-free region 33, which is the device formation region, influences the performance of the semiconductor element formed in the defect-free region 33. For example, if the depth of the defect-free region 33 becomes too shallow, the defect region 34 becomes If it extends to the element formation region, it will cause junction current leakage. Moreover, if the depth of the defect-free region 33 is too deep, the gettering ability of impurities that have contaminated the surface 31a of the wafer 31 will be reduced. The defects are formed by precipitating oxygen dissolved in solid solution in the wafer 31 as silicon oxide. Therefore, it is necessary to control the depth of the defect-free region 33, and generally, the depth of the defect-free region 33 is
It is controlled to about 1100u.
上記したＥＣ処理のみ、またはＩＣ処理のみによる場合
よりも更に良好なゲッタリング効果を得るために従来で
はＥＣ処理とＩＣ処理を併用していた。具体的にはＩＣ
処理が高温熱処理を必要とするため、ＩＣ処理中の汚染
をゲッタリングするためにＥＣ処理を行ってからＩＣ処
理を行っていた。Conventionally, EC processing and IC processing have been used in combination in order to obtain a gettering effect that is better than that obtained by using only EC processing or only IC processing. Specifically, IC
Since the processing requires high-temperature heat treatment, EC processing is performed before IC processing in order to getter any contamination during IC processing.
（発明が解決しようとする課Ｂ］
しかしながら、上記したシリコン単結晶ウェハ３１裏面
３１ｂにＥＣ処理を行った後、更にシリコン単結晶ウェ
ハ３１にＩＣ，処理を行うと、シリコン単結晶ウェハ３
１表面３１ａ側の無欠陥領域３３の深さを制御するのが
非常に困難であるという問題があった。これは、シリコ
ン単結晶ウェハ３１裏面３１ｂにＥＣ，処理を行うと、
裏面３１ｂ近傍のストレスが大きくなり、これによりそ
の後のＩＣ処理時に生じる酸素析出が裏面３１ｂ近傍に
集中するため、無欠陥領域３３の深さが極端に深くなり
無欠陥領域３３の深さ制御が困難になってしまうものと
考えられる。(Problem B to be Solved by the Invention) However, if the silicon single crystal wafer 31 is further subjected to IC processing after the EC process is performed on the back surface 31b of the silicon single crystal wafer 31 described above, the silicon single crystal wafer 31
There was a problem in that it was very difficult to control the depth of the defect-free region 33 on the side of the first surface 31a. This is achieved by performing EC and processing on the back surface 31b of the silicon single crystal wafer 31.
The stress near the back surface 31b increases, and as a result, oxygen precipitation generated during subsequent IC processing concentrates near the back surface 31b, so the depth of the defect-free region 33 becomes extremely deep, making it difficult to control the depth of the defect-free region 33. It is thought that it will become.
具体的には、第３図（ａ）、（ｂ）に示すように、シリ
コン単結晶ウェハ３１裏面３１ｂ側に近づく程欠陥密度
が高くなり、無欠陥領域３３の深さが極端に深くなって
いるのが判る。Specifically, as shown in FIGS. 3(a) and 3(b), the closer to the back surface 31b of the silicon single crystal wafer 31, the higher the defect density becomes, and the depth of the defect-free region 33 becomes extremely deep. I can see that there is.
このように、半導体素子が形成されるシリコン単結晶ウ
ェハ３１裏面３１ｂ側の無欠陥領域３３が非常に深（な
る他、ゲッタリング効果がＥＣ処理のみの場合よりも向
上させることができるが、ＥＣ処理とＩＣ処理を加えた
だけの効果を期待できないという問題があった。In this way, the defect-free region 33 on the back surface 31b side of the silicon single crystal wafer 31 on which semiconductor elements are formed is very deep (in addition, the gettering effect can be improved compared to the case of only EC processing, There was a problem in that the effect of adding processing and IC processing could not be expected.
そこで本発明は、ＩＣ処理とＥＣ処理を併用するゲッタ
リング処理において、素子形成領域となる無欠陥領域の
深さ制御を安定に行うことができ、かつＥＣ処理とＩＣ
処理を加えただけの期待したゲッタリング効果を得るこ
とができるシリコン単結晶ウェハの処理方法を提供する
ことを目的としている。Therefore, the present invention is capable of stably controlling the depth of a defect-free region that becomes an element formation region in a gettering process that uses both IC processing and EC processing, and
The object of the present invention is to provide a method for processing silicon single crystal wafers that can obtain the expected gettering effect by simply adding processing.
〔課題を解決するための手段〕
本発明によるシリコン単結晶ウェハの処理方法は上記目
的達成のため、チョクラルスキー法により形成されたシ
リコン単結晶ウェハを先ずイントリンシックゲッタリン
グ処理し、次いでエクストリンシックゲッタリング処理
するものである。[Means for Solving the Problems] In order to achieve the above object, the method for processing a silicon single crystal wafer according to the present invention first performs an intrinsic gettering process on a silicon single crystal wafer formed by the Czochralski method, and then performs an extrinsic gettering process. This is for gettering processing.
本発明に係るイントリンシックゲッタリング処理には例
えば高温・低温・高温の三段熱処理によって行う場合が
挙げられる。また、エクストリンシックゲッタリング処
理にはサンドブラスト法、ポリシリコンコート法、燐拡
散法、レーザダメージ法等が挙げられ、この中でパーテ
ィクルの発生を少なくでき、かつ平坦度を良好にできる
好ましいエクストリンシックゲッタリング処理はポリシ
リコンコート法である。The intrinsic gettering treatment according to the present invention includes, for example, a case where it is performed by three-stage heat treatment of high temperature, low temperature, and high temperature. In addition, extrinsic gettering treatments include sandblasting, polysilicon coating, phosphorus diffusion, laser damage, etc. Among these, extrinsic gettering is preferred because it can reduce particle generation and improve flatness. The ring treatment is a polysilicon coating method.
〔作用］
本発明では、予めシリコン単結晶ウェハをＩＣ処理して
酸素析出物による安定した欠陥領域３を形成するととも
に、ウェハ表面の素子形成領域に適宜所望の深さの無欠
陥領域を形成している。この時、ウェハ内にはほとんど
酸素原子が存在しない（酸素原子はウェハ中に固溶限以
下になっている）。このため、この後ＥＣ処理によりウ
ェハ裏面にストレスを加えても特にウェハ表面側の素子
形成領域となる無欠陥領域の深さをほとんど変化させる
ことなくウェハ裏面に欠陥領域を形成することができる
。[Function] In the present invention, a silicon single crystal wafer is subjected to IC processing in advance to form a stable defect region 3 due to oxygen precipitates, and at the same time, a defect-free region with a desired depth is formed in the element formation region on the wafer surface. ing. At this time, there are almost no oxygen atoms in the wafer (oxygen atoms are below the solid solubility limit in the wafer). Therefore, even if stress is applied to the back surface of the wafer through subsequent EC processing, a defective region can be formed on the back surface of the wafer without substantially changing the depth of the defect-free region, which is the element formation region on the front side of the wafer.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第１図（ａ）〜（Ｃ）はシリコン単結晶ウェハの処理方
法の一実施例を説明する図である。第１図において、１
はシリコン単結晶ウェハ、２はＩＣ処理による無欠陥領
域、３はＩＣ処理による欠陥領域、４はＥＣ処理による
欠陥領域である。FIGS. 1A to 1C are diagrams illustrating an embodiment of a method for processing a silicon single crystal wafer. In Figure 1, 1
2 is a silicon single crystal wafer, 2 is a defect-free area formed by IC processing, 3 is a defective area formed by IC processing, and 4 is a defective area formed by EC processing.
次に、そのゲッタリング処理方法について説明する。Next, the gettering processing method will be explained.
まず、第１図（ａ）に示すように、予めチョクラルスキ
ー法により形成された適当な酸素濃度（１，０〜２．０
Ｘ１０” ａｔｏｍｓ／ｃＴ１程度）の酸素原子を含有
するシリコン単結晶インゴットをスライスして例えば膜
厚が６２５μｍ１直径が１５０ｍｍφ、ｐ型（１００）
のシリコン単結晶ウェハ１を形成する。First, as shown in FIG. 1(a), an appropriate oxygen concentration (1.0 to 2.0
A silicon single crystal ingot containing oxygen atoms of approximately
A silicon single crystal wafer 1 is formed.
ここでのシリコン単結晶ウェハｌは成長させたままのプ
ロセス熱処理を加えていない状態のａｓ−ｇｒ。The silicon single crystal wafer l here is as-gr in a grown state without any process heat treatment.
ｗｎ結晶であり、酸素原子が結晶内に均一に含有されて
いる。It is a wn crystal, and oxygen atoms are uniformly contained within the crystal.
次に、第１図（ｂ）に示すように、シリコン単結晶ウェ
ハ１をＩＣ処理してシリコン単結晶ウェハ１表面１ａの
素子形成領域に無欠陥領域２を形成するとともに（この
時、裏面１ｂにも形成される）、ウェハ１内部に酸素析
出物による欠陥領域３を形成する。Next, as shown in FIG. 1(b), the silicon single crystal wafer 1 is subjected to IC processing to form a defect-free region 2 in the element formation region on the front surface 1a of the silicon single crystal wafer 1 (at this time, the back surface 1b ), a defective region 3 due to oxygen precipitates is formed inside the wafer 1 .
ここでのＩＣ処理は具体的には、まずシリコン単結晶ウ
ェハ１に１１００°Ｃ１３時間の高温熱処理を施してウ
ェハ１表面１ａから表面１ａ近傍の素子形成領域の酸素
を外方拡散して抜き、ウェハ１内部のみに格子間酸素を
形成する。次いで、高温熱処理を施したウェハ１を６５
０″Ｃの低温で保持してウェハ１を低温熱処理し、ウェ
ハｌ内部に酸素析出核を形成する。そして、低温熱処理
されたウェハ１に更に１０００°Ｃの高温熱処理を施し
てウェハ１内部に酸素析出核を酸素析出物に成長させ欠
陥領域３を形成する。Specifically, in the IC processing here, first, the silicon single crystal wafer 1 is subjected to high-temperature heat treatment at 1100° C. for 13 hours, and oxygen in the element formation region near the surface 1a of the wafer 1 is diffused out and removed from the surface 1a of the wafer 1. Interstitial oxygen is formed only inside the wafer 1. Next, the wafer 1 subjected to high-temperature heat treatment is heated to 65
The wafer 1 is held at a low temperature of 0''C and subjected to low-temperature heat treatment to form oxygen precipitation nuclei inside the wafer 1.Then, the wafer 1 that has been subjected to the low-temperature heat treatment is further subjected to a high-temperature heat treatment of 1000°C to form an oxygen precipitation nucleus inside the wafer 1. Oxygen precipitate nuclei are grown into oxygen precipitates to form defect regions 3.
そして、ＩＣ処理されたシリコン単結晶ウェハ１をポリ
シリコンコート法によるＥＣ処理してウェハ１１Ｌ面ｌ
ｂに欠陥領域４を形成することにより、第１図（Ｃ）に
示すようなシリコン単結晶ウェハ１を得ることができる
。なお、ここでのポリシリコンコート法は例えば成長温
度が６２５°ＣのＣＶＤ法によりウェハ１裏面３１ｂに
ポリシリコン膜をｌａｍ成長させることにより行ってい
る。Then, the IC-treated silicon single crystal wafer 1 is subjected to EC treatment using a polysilicon coating method, and the wafer 11L surface l is
By forming a defective region 4 in b, a silicon single crystal wafer 1 as shown in FIG. 1(C) can be obtained. Note that the polysilicon coating method here is performed by, for example, growing a polysilicon film on the back surface 31b of the wafer 1 by a CVD method at a growth temperature of 625°C.
すなわち、本実施例では、チョクラルスキー法により形
成されたシリコン単結晶ウェハ１をまずＩＣ処理してウ
ェハ１表面１ａの素子形成領域に無欠陥領域２を形成す
るとともに、欠陥領域３を形成した後、ＥＣ処理してウ
ェハ１裏面１ｂに欠陥領域４を形成するようにしている
。このように、予めシリコン単結晶ウェハ１をＩＣ処理
して酸素析出物による安定した欠陥領域３を形成すると
ともに、ウェハ１表面１ａの素子形成領域に適宜所望の
深さの無欠陥領域２を形成している。この時、ウェハ１
内にはほとんど酸素原子が存在しない（酸素原子はウェ
ハ１中に固溶限以下になっている）。このため、この後
ＥＣ処理によりウェハ１裏面１ｂにストレスを加えても
特にウェハ１表面ｌａ側の無欠陥領域２の深さをほとん
ど変化させることなくウェハ１裏面１ｂに欠陥領域４を
形成することができる。That is, in this example, a silicon single crystal wafer 1 formed by the Czochralski method was first subjected to IC processing to form a defect-free region 2 in the element formation region on the surface 1a of the wafer 1, and at the same time, a defect region 3 was formed. After that, an EC process is performed to form a defective region 4 on the back surface 1b of the wafer 1. In this way, the silicon single crystal wafer 1 is subjected to IC processing in advance to form a stable defect region 3 due to oxygen precipitates, and at the same time, a defect-free region 2 of a desired depth is formed in the element formation region on the surface 1a of the wafer 1. are doing. At this time, wafer 1
Almost no oxygen atoms exist within the wafer 1 (oxygen atoms are below the solid solubility limit in the wafer 1). Therefore, even if stress is applied to the back surface 1b of the wafer 1 through EC processing, the defect-free region 4 can be formed on the back surface 1b of the wafer 1 without changing the depth of the defect-free region 2 on the front surface la side of the wafer 1. I can do it.
したがって、素子形成領域となる無欠陥領域２の深さ制
御を安定に行うことができ、かつＥＣ処理とＩＣ処理を
加えただけの期待したゲッタリング効果を得ることがで
きる。Therefore, it is possible to stably control the depth of the defect-free region 2, which is the element forming region, and to obtain the expected gettering effect obtained by adding only the EC processing and the IC processing.
本発明によれば、ＩＣ処理とＥＣ処理を併用するゲッタ
リング処理において、素子形成領域となる無欠陥領域の
深さ制御を安定に行うことができ、かつＥＣ処理とＩＣ
処理を加えただけの期待したゲッタリング効果を得るこ
とができるという効果がある。According to the present invention, in gettering processing that uses both IC processing and EC processing, it is possible to stably control the depth of a defect-free region that becomes an element formation region, and
The effect is that the expected gettering effect can be obtained by simply adding processing.
第１図は本発明に係るシリコン単結晶ウェハの処理方法
の一実施例のゲッタリング処理方法を説明する図、
第２図は従来例のゲッタリング処理方法を説明する図、
第３図は従来例の課題を説明する図である。
１・・・・・・シリコン単結晶ウェハ、１ａ・・・・・
・表面、
１ｂ・・・・・・裏面、
２・・・・・・無欠陥領域、
３．４・・・・・・欠陥領域。
ノー ノ
Ｎ、−
＼ −／
一実施例のゲッタリング処理方法を説明する図第１図
従来例のゲッタリング処理方法を説明する図第
図FIG. 1 is a diagram illustrating a gettering method according to an embodiment of the silicon single crystal wafer processing method according to the present invention, FIG. 2 is a diagram illustrating a conventional gettering method, and FIG. 3 is a diagram illustrating a conventional gettering method. It is a figure explaining an example problem. 1...Silicon single crystal wafer, 1a...
・Front surface, 1b... Back surface, 2... Defect-free area, 3.4... Defect area. No No N, - \ -/ Figure 1 for explaining the gettering processing method of an embodiment Figure 1 Diagram explaining the gettering processing method for the conventional example
Claims (3)
結晶ウェハを先ずイントリンシックゲッタリング処理し
、次いでエクストリンシックゲッタリング処理すること
を特徴とするシリコン単結晶ウェハの処理方法。(1) A method for processing a silicon single crystal wafer, characterized in that a silicon single crystal wafer formed by the Czochralski method is first subjected to an intrinsic gettering treatment and then subjected to an extrinsic gettering treatment.
低温・高温の三段熱処理により行われることを特徴とす
る請求項１記載のシリコン単結晶ウェハの処理方法。(2) The above-mentioned intrinsic gettering treatment is performed at high temperature.
2. The method of processing a silicon single crystal wafer according to claim 1, wherein the processing is performed by three-stage heat treatment at low and high temperatures.
シリコンコート法により行われることを特徴とする請求
項２記載のシリコン単結晶ウェハの処理方法。(3) The method of processing a silicon single crystal wafer according to claim 2, wherein the extrinsic gettering treatment is performed by a polysilicon coating method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15930290A JPH0453140A (en) | 1990-06-18 | 1990-06-18 | Processing of silicon single crystalline wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15930290A JPH0453140A (en) | 1990-06-18 | 1990-06-18 | Processing of silicon single crystalline wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0453140A true JPH0453140A (en) | 1992-02-20 |
Family
ID=15690834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15930290A Pending JPH0453140A (en) | 1990-06-18 | 1990-06-18 | Processing of silicon single crystalline wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453140A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5970366A (en) * | 1996-07-16 | 1999-10-19 | Nec Corporation | Method of removing metallic contaminants from simox substrate |
| JP2006165462A (en) * | 2004-12-10 | 2006-06-22 | Canon Inc | Semiconductor substrate for solid imaging device and its manufacturing method |
-
1990
- 1990-06-18 JP JP15930290A patent/JPH0453140A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for producing it. |
| US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5970366A (en) * | 1996-07-16 | 1999-10-19 | Nec Corporation | Method of removing metallic contaminants from simox substrate |
| JP2006165462A (en) * | 2004-12-10 | 2006-06-22 | Canon Inc | Semiconductor substrate for solid imaging device and its manufacturing method |
| JP4667030B2 (en) * | 2004-12-10 | 2011-04-06 | キヤノン株式会社 | Semiconductor substrate for solid-state imaging device and manufacturing method thereof |
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