JPH0452620B2 - - Google Patents

Info

Publication number
JPH0452620B2
JPH0452620B2 JP60038004A JP3800485A JPH0452620B2 JP H0452620 B2 JPH0452620 B2 JP H0452620B2 JP 60038004 A JP60038004 A JP 60038004A JP 3800485 A JP3800485 A JP 3800485A JP H0452620 B2 JPH0452620 B2 JP H0452620B2
Authority
JP
Japan
Prior art keywords
semiconductor device
flat display
display panel
film carrier
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60038004A
Other languages
Japanese (ja)
Other versions
JPS61198641A (en
Inventor
Kenzo Hatada
Koji Matsunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60038004A priority Critical patent/JPS61198641A/en
Priority to US06/829,819 priority patent/US4766426A/en
Publication of JPS61198641A publication Critical patent/JPS61198641A/en
Publication of JPH0452620B2 publication Critical patent/JPH0452620B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/365—Assembling flexible printed circuits with other printed circuits by abutting, i.e. without alloying process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10469—Asymmetrically mounted component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Metallurgy (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、液晶、EL等の平板デイスプレイパ
ネルとこれを駆動する回路を高密度、薄型かつ安
価に実装した平板デイスプレイ装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a flat panel display device in which a flat panel display panel such as a liquid crystal or EL panel and a circuit for driving the panel are mounted at high density, thinly and inexpensively.

従来の技術 近年液晶やELを用いた平板デイスプレイが開
発、商品化されてきている。これら平板デイスプ
レイは薄型のデイスプレイを実現できるものの、
平板デイスプレイの端面に導出された電極群にこ
れを駆動するための半導体装置を接続する必要が
ある。これら電極の数は平板デイスプレイの大き
さにもよるが数100本から数1000本に達するもの
であつた。第４図に従来の平板デイスプレイを示
しており、半導体装置はフラツトパツク等のパツ
ケージ１０に実装され、平板デイスプレイ７とほ
ぼ同一寸法の回路基板１２上に搭載される。Conventional technology In recent years, flat panel displays using liquid crystals and EL have been developed and commercialized. Although these flat displays can realize thin displays,
It is necessary to connect a semiconductor device for driving the electrode group to the end face of the flat display. The number of these electrodes ranged from several hundred to several thousand, depending on the size of the flat display. FIG. 4 shows a conventional flat panel display, in which a semiconductor device is mounted in a package 10 such as a flat pack, and mounted on a circuit board 12 having approximately the same dimensions as the flat panel display 7.

パツケージ１０のリード１１は、前記回路基板
１２上に形成した配線パターン１３に半田づけ固
定され、前記配線パターン１３は、回路基板１２
に設けたスルーホールを介して、反対面の回路基
板の電極１３′に接続される。前記回路基板の電
極１３′と平板デイスプレイパネル７の電極８と
は同一間隔で形成されるものである。また前記回
路基板の電極１３′と平板デイスプレイパネル７
の電極８とは、導電性領域と絶縁性領域とを交互
に積層した弾性接続体１４で接続され、枠体１５
で固定される。 The leads 11 of the package 10 are soldered and fixed to the wiring pattern 13 formed on the circuit board 12, and the wiring pattern 13 is connected to the circuit board 12.
It is connected to the electrode 13' of the circuit board on the opposite side through a through hole provided on the opposite side. The electrodes 13' of the circuit board and the electrodes 8 of the flat display panel 7 are formed with the same spacing. Further, the electrode 13' of the circuit board and the flat display panel 7
The electrode 8 is connected to the frame 15 by an elastic connecting body 14 in which conductive regions and insulating regions are alternately laminated.
It is fixed at

このような従来の構成においては、半導体装置
のパツケージはリード数の増大とともに大型にな
り回路基板に搭載され難くなり、平板デイスプレ
イ全体が大型化するものであつた。また回路基板
の電極を平板デイスプレイの電極と相対して、１
対１で形成しなければならない。実際には数10cm
の辺に数100μｍのピツチで電極を形成しなけれ
ばならないから、前記回路基板上の電極間隔の寸
法は熱膨張等で累積誤差をきたし、完全な接続を
得る事ができず、接続不良を発生していた。更に
また、接続箇所が著じるしく多い、例えば半導体
装置のパツケージ内のワイヤボンデイング、パツ
ケージ１１の半田づけ、弾性接続体の２箇所の部
分と少なくとも４箇所の接続を必要とし、これ
は、信頼性を低下さす原因になつていた。 In such a conventional configuration, as the number of leads increases, the size of the semiconductor device package becomes larger, making it difficult to mount it on a circuit board, resulting in an increase in the size of the entire flat display. In addition, the electrodes of the circuit board are placed opposite to the electrodes of the flat display.
Must be formed in a one-on-one format. Actually several 10cm
Since the electrodes must be formed at a pitch of several 100 μm on the sides of the circuit board, the dimensions of the electrode spacing on the circuit board will have cumulative errors due to thermal expansion, etc., making it impossible to obtain a perfect connection and causing connection failures. Was. Furthermore, it requires a significantly large number of connection points, such as wire bonding within the package of the semiconductor device, soldering of the package 11, and at least four connections to two parts of the elastic connector. It was a cause of decreased sexuality.

発明が解決しようとする問題点 従来のこのような構成では、平板デイスプレイ
装置の大きさが著じるしく大きくなつたり、ある
いは、接続点数が多く接続の信頼性を低下さす原
因になつている。これは、実装体の構成部品数が
多い事や、本当の平板デイスプレイの実装体を実
現できていない事によるものと思われる。Problems to be Solved by the Invention In such a conventional configuration, the size of the flat panel display device becomes significantly large, or the number of connection points is large, which causes a decrease in connection reliability. This seems to be due to the large number of component parts of the mounting body and the fact that it has not been possible to realize a true flat display mounting body.

そこで、本発明は、構成部品数を少なく、平板
デイスプレイパネルの電極と半導体装置の電極を
極力接近させんとするものである。 Therefore, the present invention aims to reduce the number of component parts and bring the electrodes of the flat display panel and the electrodes of the semiconductor device as close as possible.

問題点を解決するための手段 そして上記問題点を解決する本発明の技術的手
段は、半導体装置のパツケージにフイルムキヤリ
ヤ方式を用い、リードを２方向に導出するもので
ある。Means for Solving the Problems The technical means of the present invention for solving the above-mentioned problems is to use a film carrier method for the package of the semiconductor device and lead out the leads in two directions.

作 用 この技術的手段による作用は次のようになる。
すなわちフイルムキヤリヤ方式で半導体装置を実
装し、リードを２方向のみに導出し、その一方の
リードは少なくとも平板デイスプレイの電極と相
対し、同一間隔で構成され、この一方のリードと
平板デイスプレイの電極とを接しめるのである。
また、前記半導体装置を実装したフイルムキヤリ
ヤは平板デイスプレイ領域内に配設されているた
め、平板デイスプレイ装置が小型、薄型となり、
接続箇所も著じるしく少なくなるものである。Effect The effect of this technical means is as follows.
That is, the semiconductor device is mounted using a film carrier method, and leads are led out in only two directions, one of the leads faces at least the electrode of the flat display and is arranged at the same interval, and this one lead and the electrode of the flat display It brings them into contact with each other.
Furthermore, since the film carrier on which the semiconductor device is mounted is disposed within the flat display area, the flat display device can be made smaller and thinner.
The number of connection points is also significantly reduced.

実施例 本発明の実施例を第１図で説明する。Example An embodiment of the present invention will be explained with reference to FIG.

半導体装置１はフイルムキヤリヤ方式で実装さ
れ、平板デイスプレイ７の裏面の領域内に配設さ
れ、半導体装置１の電極２とフイルムキヤリヤ方
式のリード４および６は接合され、デイスプレイ
７の電極８と接合すべき一方のリード４の間隔
は、前記デイスプレイの電極８の間隔と同一間隔
で形成され、デイスプレイ７の電極８と接するも
のである。また、他方のリード６は、前記平板デ
イスプレイ７の裏面の領域内に配設された配線基
板９に接合された構成である。すなわち半導体装
置１から導出したリード６は半導体装置を駆動さ
せるための入力信号、電源を供給するための入力
端子に相当し、リード４は平板デイスプレイ７を
駆動させる信号を出力させる出力端子である。平
板デイスプレイの実装体においては、前記フイル
ムキヤリヤ方式で実装した半導体装置が複数個少
なくとも一列に配置されるものである。 The semiconductor device 1 is mounted using a film carrier method and is disposed within the area on the back surface of a flat display 7. The electrodes 2 of the semiconductor device 1 and the leads 4 and 6 of the film carrier method are bonded to each other, and the electrodes 8 of the display 7 are connected to each other. The interval between the leads 4 to be connected to the display 7 is the same as the interval between the electrodes 8 of the display 7, and the leads 4 are in contact with the electrodes 8 of the display 7. The other lead 6 is connected to a wiring board 9 disposed in a region on the back surface of the flat display 7. That is, the leads 6 led out from the semiconductor device 1 correspond to input terminals for supplying input signals and power for driving the semiconductor device, and the leads 4 are output terminals for outputting signals for driving the flat display 7. In a flat panel display package, a plurality of semiconductor devices mounted using the film carrier method are arranged in at least one row.

前記フイルムキヤリヤ方式について第２図で更
に述べれば、半導体装置１は、フイルムテープ３
の開孔部に突出したリード５と接合され、前記半
導体装置１の電極上には、Ti−Pd−Auや、Cr−
Cu−Au等の多層金属層を介して10〜30μｍ厚の
Au突起が形成され、銅箔を蝕刻して形成し、Sn
メツキ処理した前記リード５とがAu・Snの合金
で接合される。半導体装置１への入力端子である
リード６と出力端子であるリード４は互いに一方
向に突出され（すなわち２方向）、リード４は平
板デイスプレイの電極間隔と同一間隔に形成され
るものである。第２図の構成は長尺のフイルムに
複数個形成されたものを所定の寸法に切断したも
のである。また、第２図のデイスプレイ電極と接
する一方のリード４はその先端にフイルムキヤリ
ヤを残存させていないが、前記リード４の先端に
リード先端を固定する如くフイルムキヤリヤを残
存させても良い。 To further describe the film carrier method with reference to FIG.
Ti-Pd-Au, Cr-
10 to 30 μm thick through multilayer metal layers such as Cu-Au.
Au protrusions are formed, formed by etching copper foil, and Sn
The plated leads 5 are joined with an alloy of Au and Sn. The leads 6, which are input terminals to the semiconductor device 1, and the leads 4, which are output terminals, are mutually protruded in one direction (that is, in two directions), and the leads 4 are formed at the same spacing as the electrode spacing of a flat display. The structure shown in FIG. 2 is obtained by cutting a plurality of films formed on a long film into predetermined dimensions. Further, although one of the leads 4 in contact with the display electrode in FIG. 2 does not have a film carrier remaining at its tip, a film carrier may be left at the tip of the lead 4 so as to fix the lead tip.

また平板デイスプレイパネル７の電極８とリー
ド４との接合は、半田づけ、もしくは接着剤等を
介して接合する事ができる。第３図は前記平板デ
イスプレイパネル７の電極８とリード４との接合
方法の他の実施例である。デイスプレイパネル７
の電極８とリード４とを位置合せし、シリコーン
等の弾性を有する弾性体２１を前記リード４上に
置き、枠体２０で圧接した構成である。このよう
な構成であれば、半田づけを行なうための電極の
処理や、加熱治具が不用となる特徴がある。 Further, the electrodes 8 of the flat display panel 7 and the leads 4 can be joined by soldering, adhesive, or the like. FIG. 3 shows another embodiment of the method of joining the electrodes 8 and leads 4 of the flat display panel 7. In FIG. Display panel 7
The electrode 8 and the lead 4 are aligned, an elastic body 21 such as silicone is placed on the lead 4, and the frame 20 is pressed against the lead 4. Such a configuration has the advantage of eliminating the need for electrode processing and heating jigs for soldering.

発明の効果 以上のように、本発明によれば次のような効果
を得ることができる。Effects of the Invention As described above, according to the present invention, the following effects can be obtained.

(1) 半導体装置をフイルムキヤリヤ方式で実装
し、これを平板デイスプレイパネルの領域内に
配設せしめ、前記フイルムキヤリヤ方式で実装
された半導体装置の電極から延在したリードが
直接デイスプレイパネルの電極に接合している
ために、接合箇所が半導体装置の電極と、デイ
スプレイパネルの電極の２箇所しかなく、接合
の信頼性が著じるしく高いものである。また、
フイルムキヤリヤ方式で半導体装置が実装され
ているため平板デイスプレイ装置を薄型、小型
に実装できるものである。(1) A semiconductor device is mounted using a film carrier method and placed within the area of a flat display panel, and the leads extending from the electrodes of the semiconductor device mounted using the film carrier method are directly connected to the display panel. Since it is bonded to the electrode, there are only two bonding locations: the electrode of the semiconductor device and the electrode of the display panel, and the reliability of bonding is extremely high. Also,
Since the semiconductor device is mounted using a film carrier method, the flat display device can be mounted thin and compact.

(2) また、本発明の構成では、半導体装置から導
出したリードを直接、平板デイスプレイパネル
の電極に接しめているために、構成部品数が著
じるしく少なる一方、製造工数も削減でき、実
装体のコストを安価にできるものである。(2) Furthermore, in the configuration of the present invention, since the leads led out from the semiconductor device are brought into direct contact with the electrodes of the flat display panel, the number of component parts is significantly reduced, and the number of manufacturing steps can also be reduced. The cost of the mounting body can be reduced.

(3) 平板デイスプレイパネルの電極と半導体装置
からのリードとの接合において、その位置合せ
が各半導体装置のフイルムキヤリヤ毎で短かい
距離で実施できるため、従来の如く回路基板上
の電極の間隔ずれや、平板デイスプレイの電極
との位置合せずれが発生しない。(3) When bonding the electrodes of a flat display panel and the leads from a semiconductor device, alignment can be performed over a short distance for each film carrier of each semiconductor device, so the spacing between the electrodes on the circuit board can be reduced as required by conventional methods. No misalignment or misalignment with the electrodes of the flat display.

(4) また、万一半導体装置が破損したとしても、
単にフイルムキヤリヤのリードの半田づけをは
ずすのみで容易に交換できる。(4) Also, even if the semiconductor device is damaged,
It can be easily replaced by simply unsoldering the film carrier lead.

(5) 平板デイスプレイの電極とリードとの位置合
せが、間に介在物がないため著じるしく容易に
実施できる等の効果がある。(5) There are effects such as the fact that alignment of the electrodes and leads of a flat panel display can be carried out with great ease because there is no inclusion between them.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のデイスプレイ装置
の部分構成を示す断面図、第２図は同デイスプレ
イ装置におけるフイルムキヤリヤ方式で実装した
半導体装置の斜視図、第３図は本発明の他の実施
例の断面図、第４図は従来のデイスプレイ装置の
断面図である。 １……半導体装置、３……フイルムキヤリヤ、
４……一方のリード、６……他方のリード、７…
…平板デイスプレイ、８……電極、９……回路基
板。 FIG. 1 is a sectional view showing a partial configuration of a display device according to an embodiment of the present invention, FIG. 2 is a perspective view of a semiconductor device mounted using a film carrier method in the same display device, and FIG. FIG. 4 is a cross-sectional view of a conventional display device. 1...Semiconductor device, 3...Film carrier,
4...One lead, 6...The other lead, 7...
...Flat display, 8... Electrode, 9... Circuit board.

Claims (1)

【特許請求の範囲】[Claims] １ 端面に一列に配列された電極群を有する平板
デイスプレイパネルの端面を除く部分に前記平板
デイスプレイパネルを駆動させる半導体装置及び
該半導体装置を駆動させる回路基板が搭載された
平板デイスプレイ装置において、前記半導体装置
が互いに平行な対向する２方向に複数のリードを
導出したフイルムキヤリアテープに実装され、前
記フイルムキヤリアテープの一方向のリードの一
端は前記平板デイスプレイパネル端面の電極群の
間隔と同一間隔で形成されていると共に、前記電
極群に接続され、前記フイルムキヤリアテープの
一方向のリードの他端は前記半導体装置の前記平
板デイスプレイパネルを駆動する信号を出力する
出力端子に接続され、前記フイルムキヤリアテー
プの他の一方のリードの一端は前記回路基板の電
極に、前記他の一方のリードの他端は前記半導体
装置の該半導体装置を駆動する信号を入力する入
力端子に接続されてなり、前記平板デイスプレイ
パネルの電極群に接続された前記半導体装置は前
記電極群の配列と平行に一列に配列されて前記平
板デイスプレイパネルに搭載されていることを特
徴とする平板デイスプレイ装置。1. A flat display device in which a semiconductor device for driving the flat display panel and a circuit board for driving the semiconductor device are mounted on a portion other than the end face of a flat display panel having a group of electrodes arranged in a line on the end face, wherein the semiconductor The device is mounted on a film carrier tape having a plurality of leads led out in two mutually parallel opposing directions, and one end of the lead in one direction of the film carrier tape is formed at the same spacing as the spacing between the electrode groups on the end surface of the flat display panel. The film carrier tape is connected to the electrode group, and the other end of one lead of the film carrier tape is connected to an output terminal for outputting a signal for driving the flat display panel of the semiconductor device. One end of the other lead is connected to an electrode of the circuit board, the other end of the other lead is connected to an input terminal of the semiconductor device for inputting a signal for driving the semiconductor device, and the flat plate A flat display device, wherein the semiconductor devices connected to the electrode groups of the display panel are arranged in a line parallel to the arrangement of the electrode groups and mounted on the flat display panel.
JP60038004A 1985-02-14 1985-02-27 Flat display device Granted JPS61198641A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP60038004A JPS61198641A (en) 1985-02-27 1985-02-27 Flat display device
US06/829,819 US4766426A (en) 1985-02-14 1986-02-14 Display panel assembly having a plurality of film carrier tapes on each of which a semiconductor divice is mounted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60038004A JPS61198641A (en) 1985-02-27 1985-02-27 Flat display device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP7109245A Division JP2568815B2 (en) 1995-05-08 1995-05-08 Flat panel display device

Publications (2)

Publication Number Publication Date
JPS61198641A JPS61198641A (en) 1986-09-03
JPH0452620B2 true JPH0452620B2 (en) 1992-08-24

Family

ID=12513425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60038004A Granted JPS61198641A (en) 1985-02-14 1985-02-27 Flat display device

Country Status (1)

Country Link
JP (1) JPS61198641A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000783A (en) * 2011-09-19 2013-03-27 展晶科技(深圳)有限公司 Light emitting diode and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53101270A (en) * 1977-02-16 1978-09-04 Seiko Epson Corp Substraet for semiconductor device
JPS54124675A (en) * 1978-03-22 1979-09-27 Matsushita Electric Ind Co Ltd Semiconductor device and its mounting method
JPS5749273B2 (en) * 1976-03-05 1982-10-21
JPS58122586A (en) * 1982-01-14 1983-07-21 セイコ−京葉工業株式会社 Liquid crystal display
JPS60149079A (en) * 1984-01-13 1985-08-06 シャープ株式会社 Connector for display body unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749273U (en) * 1980-09-04 1982-03-19
JPS58188684U (en) * 1982-06-10 1983-12-15 セイコーエプソン株式会社 electronic display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749273B2 (en) * 1976-03-05 1982-10-21
JPS53101270A (en) * 1977-02-16 1978-09-04 Seiko Epson Corp Substraet for semiconductor device
JPS54124675A (en) * 1978-03-22 1979-09-27 Matsushita Electric Ind Co Ltd Semiconductor device and its mounting method
JPS58122586A (en) * 1982-01-14 1983-07-21 セイコ−京葉工業株式会社 Liquid crystal display
JPS60149079A (en) * 1984-01-13 1985-08-06 シャープ株式会社 Connector for display body unit

Also Published As

Publication number Publication date
JPS61198641A (en) 1986-09-03

Similar Documents

Publication Publication Date Title
US4072816A (en) Integrated circuit package
KR0127678B1 (en) Semiconductor device and the manufacture thereof
US6992395B2 (en) Semiconductor device and semiconductor module having external electrodes on an outer periphery
JP2870528B1 (en) 3D memory module
US4766426A (en) Display panel assembly having a plurality of film carrier tapes on each of which a semiconductor divice is mounted
JP3904058B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JPH0452620B2 (en)
JP2682198B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2864612B2 (en) Semiconductor device
JP2568815B2 (en) Flat panel display device
JPS61212031A (en) Mounting body on display panel
JPH0863106A (en) Flat plate display device
JPH10261852A (en) Heat-sealed connector and flexible wiring board
JPH0424857B2 (en)
JP2879503B2 (en) Surface mount type electronic circuit device
JPS5996759A (en) Semiconductor device
JPH04280696A (en) High integrated semiconductor device
JPH05152703A (en) Hybrid integrated circuit device
JP3987288B2 (en) Semiconductor element mounting structure and liquid crystal display device
JP3027841B2 (en) Wiring board connection method
JP3543415B2 (en) Imaging device
JPH0414022A (en) Liquid crystal display device
JPH11145373A (en) Tape carrier package, and liquid crystal display using the tape carrier package
JPH064605Y2 (en) Hybrid integrated circuit
JPH0338845A (en) Hybrid integrated circuit