JPH045105Y2 - - Google Patents
Info
- Publication number
- JPH045105Y2 JPH045105Y2 JP17557087U JP17557087U JPH045105Y2 JP H045105 Y2 JPH045105 Y2 JP H045105Y2 JP 17557087 U JP17557087 U JP 17557087U JP 17557087 U JP17557087 U JP 17557087U JP H045105 Y2 JPH045105 Y2 JP H045105Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- vertical synchronization
- circuit
- oscillation
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000926 separation method Methods 0.000 claims description 23
- 230000010355 oscillation Effects 0.000 claims description 22
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
【考案の詳細な説明】
本考案は、回転ヘツド式ビデオテープレコーダ
を利用するPCM再生装置のクロツク発生回路に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generation circuit for a PCM playback device using a rotary head type video tape recorder.
ビデオテープレコーダの再生PCM信号を音声
信号に変換するPCM再生装置は、再生PCM信号
処理のため再生情報に同期するクロツクパルスを
必要とする。しかし再生PCM信号は回転ヘツド
の回転変動によつて時間軸変動成分を含むため、
定発振出力をクロツクパルスとして利用すること
ができず、回転変動に応じて発振周波数を変更す
るクロツクパルスが必要となる。そこで従来より
垂直同期周期の変動に応じて発振周波数を変更す
ると共に基準信号となる垂直同期信号のドロツプ
アウトを疑似同期信号にて補う方法が採用されて
いるが、ドロツプアウトはPCM信号多重区間に
も発生し、垂直同期分離出力に混入して発振周波
数を乱すことが確認された。 A PCM playback device that converts a playback PCM signal of a video tape recorder into an audio signal requires a clock pulse synchronized with playback information in order to process the playback PCM signal. However, since the reproduced PCM signal includes time axis fluctuation components due to rotational fluctuations of the rotating head,
A constant oscillation output cannot be used as a clock pulse, and a clock pulse that changes the oscillation frequency in response to rotational fluctuations is required. Therefore, conventional methods have been adopted in which the oscillation frequency is changed according to fluctuations in the vertical synchronization period and the dropout of the vertical synchronization signal, which is the reference signal, is compensated for with a pseudo synchronization signal, but dropouts also occur in the PCM signal multiplex section. However, it was confirmed that it mixed into the vertical synchronization separation output and disturbed the oscillation frequency.
そこで、本考案は上述の点に鑑み、垂直同期区
間を含む僅かな区間にのみ垂直同期分離出力の導
出を許容することによりPCM信号多重域に於け
るドロツプアウトに起因する発振出力の乱れを解
消すると共に、従来例同様垂直同期区間に発生す
るドロツプアウトによつても発振出力を乱すこと
のない新規且つ有効なPCM再生装置のクロツク
発生回路を提案せんとするものである。 Therefore, in view of the above points, the present invention eliminates the disturbance in the oscillation output caused by dropout in the PCM signal multiplexing area by allowing the derivation of the vertical synchronization separated output only in a small period including the vertical synchronization period. In addition, it is an object of the present invention to propose a new and effective clock generation circuit for a PCM reproducing device, which does not disturb the oscillation output even by dropouts occurring in the vertical synchronization period, as in the conventional example.
以下本考案を図示せる一実施例に従い説明す
る。第１図は本考案の一実施回路ブロツク図であ
り、第２図はその要部波形説明図をそれぞれ顕わ
す。本実施例はまず動作開始時等発振出力の不安
定な第１のモードで、垂直同期分離回路１より導
出され垂直同期区間より約1/3Ｈ（Ｈは水平同期周
期）遅れる垂直同期分離出力V1を基準入力とし、
発振出力ａを第11/8分周回路２と第11/84分周回
路３と1/525分周回路４をそれぞれ介して得られ
る垂直同期周期相当の分周出力V2を比較［−］
入力することにより、発振出力ａの周波数を粗制
御し、動作が安定した第２のモードで垂直同期区
間に発生するドロツプアウトを前記同期分離出力
V1より僅か幅狭な幅狭パルスV3によつて補償し、
残るPCM信号多重期間のドロツプアウトに基づ
くノイズ成分を前記同期分離出力V1より僅か幅
広な幅広パルスV4にて阻止してドロツプアウト
に全く影響されない正規の垂直同意分離出力を基
準入力として発振出力周波数を安定且つ密に制御
するものである。 The present invention will be described below with reference to an illustrative embodiment. FIG. 1 is a block diagram of an implementation circuit of the present invention, and FIG. 2 shows an explanatory diagram of waveforms of the main parts thereof. In this embodiment, first, the oscillation output is unstable in the first mode at the start of operation, and the vertical synchronization separation output V is derived from the vertical synchronization separation circuit 1 and is delayed by about 1/3H (H is the horizontal synchronization period) from the vertical synchronization period. 1 as the reference input,
Compare the divided output V 2 corresponding to the vertical synchronization period obtained from the oscillation output a through the 11/8th frequency divider circuit 2, the 11/84th frequency divider circuit 3, and the 1/525 frequency divider circuit 4 [-]
By inputting the input, the frequency of the oscillation output a is roughly controlled, and the dropout that occurs in the vertical synchronization section in the second mode where the operation is stable is controlled as the synchronization separation output.
compensated by a narrow pulse V 3 slightly narrower than V 1 ;
The noise component based on the dropout of the remaining PCM signal multiplexing period is blocked by the wide pulse V4 , which is slightly wider than the synchronization separation output V1 , and the oscillation output frequency is adjusted using the regular vertical synchronization separation output, which is not affected by the dropout at all, as a reference input. It is stable and tightly controlled.
そのためモードの設定は、再生PCM信号の処
理の過程で生ずる誤検出出力ｂの発生頻度をロツ
ク検出回路５にて検出し、第１のモードでローレ
ベル出力を発して正規の垂直同期分離出力を他入
力とする第１アンドA1を常開すると共に、前記
幅狭パルスV3を他入力とする第２アンドゲート
A2と前記幅広パルスV4を他入力とする第３アン
ドゲートA3を何れも常閉する一方、第２のモー
ドで前記第２，第３アンドゲートA2，A3を開放
し、第１オアゲートO1より前記垂直同期分離出
力V1と前記幅狭パルスV3の論理和出力第１アン
ドゲートA1の信号入力すると共に前記幅広パル
スV4を第２オアゲートO2を介して前記第１アン
ドゲートA1の制御入力とすることにより、正規
の垂直同期信号が含まれる僅か幅広の区間にのみ
前記第１アンドゲートA1を開放せしめてノイズ
の混入を阻止している。 Therefore, to set the mode, the lock detection circuit 5 detects the frequency of occurrence of the false detection output b that occurs in the process of processing the reproduced PCM signal, and in the first mode, a low level output is generated and the normal vertical synchronization separation output is output. The first AND gate that uses the other input as the other input is kept open, and the second AND gate that uses the narrow pulse V 3 as the other input.
A 2 and the third AND gate A 3 whose other inputs are the wide pulse V 4 are both normally closed, while the second and third AND gates A 2 and A 3 are opened in the second mode, and the third AND gate A 3 is opened in the second mode. 1 OR gate O 1 inputs the logical sum output of the vertical synchronization separation output V 1 and the narrow pulse V 3 to the first AND gate A 1 , and the wide pulse V 4 is input to the first AND gate A 1 through the second OR gate O 2 . By using this as a control input for the 1-AND gate A1 , the first AND gate A1 is opened only in a slightly wide section that includes a regular vertical synchronizing signal, thereby preventing noise from entering.
以下幅狭パルスV3と幅広パルスV4の形成方法
に付いて説明する。まず、発振出力ａを入力とす
る第21/8分周回路２′を水平周期分離回路６の水
平同期分離出力Ｈにてリセツトして得られるクロ
ツクパルスｃを、更に後段の第21/84分周回路７
にて分周し前記水平同期分離出力に同期し２倍に
する同期分周出力2fHを導出し、続いて該同期分
離出力2fHを計数入力、正規の垂直同期分離出力
の立下りパルス直後のパルス（後述）をリセツト
入力として計数値519で立上り525で立下る計数出
力V5を後段のカウンタ８より導出し、更に続い
て該計数出力V5をＤ入力前記同期分周出力2fHを
Ｔ入力として前記計数出力V5より1/2Ｈ遅れた遅
延出力Q1を後段の第１フリツプフロツプ９より
導出して、前記計数出力V5と遅延出力Q1の論理
積出力を幅狭パルスV3、論理和出力を幅広パル
スV4として導出している。更に前述したカウン
タ８のリセツトに際してはまず前記垂直同期分離
出力V1をＤ入力前記発振出力ａをＴ入力として
前記垂直同期分離出力V1より高々前記発振出力
ａの一周期分遅れる反転遅延出力2を第2Dタイ
プフリツプフロツプ１０より導出し続いて前記垂
直同期分離出力V1と前記反転遅延出力2の後段
のノア回路Ｎに入力して前記垂直同期信号V1の
立下り部で立上りパルス幅を高々50nsecとするノ
ア出力をリセツトパルスｄとして前記カウンタ８
のリセツト入力としている。 The method for forming the narrow pulse V 3 and the wide pulse V 4 will be explained below. First, the clock pulse c obtained by resetting the 21/8 frequency divider circuit 2' which receives the oscillation output a as an input with the horizontal synchronization separation output H of the horizontal period separation circuit 6 is further divided into the 21/84 frequency dividers in the subsequent stage. circuit 7
Derive the synchronous frequency division output 2fH which is frequency-divided and doubled in synchronization with the horizontal synchronous separation output, and then the synchronous separation output 2fH is input for counting, and the pulse immediately after the falling pulse of the normal vertical synchronous separation output is derived. (described later) is used as a reset input to derive the count output V5 which rises at count value 519 and falls at count value 525 from the subsequent stage counter 8, and then the count output V5 is input to D and the synchronous frequency division output 2fH is input to T. The delayed output Q 1 delayed by 1/2H from the counting output V 5 is derived from the first flip-flop 9 in the subsequent stage, and the AND output of the counting output V 5 and the delayed output Q 1 is combined with the narrow pulse V 3 and the logical sum. The output is derived as a wide pulse V4 . Furthermore, when resetting the counter 8 mentioned above, first, the vertical synchronization separated output V 1 is input as a D input, the oscillation output a is input as a T input, and an inverted delay output 2 is delayed from the vertical synchronization separation output V 1 by at most one period of the oscillation output a. is derived from the second D-type flip-flop 10 and then inputted to the NOR circuit N at the subsequent stage of the vertical synchronization separation output V 1 and the inversion delay output 2 to generate a rising pulse at the falling edge of the vertical synchronization signal V 1 . The counter 8 uses the NOR output with a width of at most 50 nsec as the reset pulse d.
It is used as a reset input.
上述せる構成によつて導出される比較信号V2
と基準信号（正規の垂直同期分離出力）は比較回
路１１に於て比較され、比較出力をローパスフイ
ルタ１２を介して制御入力として電圧制御型発振
回路１３に入力し、発振出力ａの周波数コントロ
ールを為している。 Comparison signal V 2 derived by the configuration described above
and a reference signal (regular vertical synchronization separated output) are compared in a comparison circuit 11, and the comparison output is inputted as a control input to a voltage-controlled oscillation circuit 13 via a low-pass filter 12 to control the frequency of the oscillation output a. I am doing it.
よつて再生PCM装置は、データ処理のためのク
ロツク入力として前述せる電圧制御発振回路の発
振出力を分周して得るため確実なデータ処理が保
証されその効果は大である。Therefore, since the regenerating PCM device obtains the clock input for data processing by dividing the oscillation output of the voltage controlled oscillation circuit mentioned above, reliable data processing is guaranteed, which is highly effective.
第１図は本考案の一実施回路ブロツク図、第２
図は同要部波形説明図をそれぞれ顕わす。
主な図番の説明、１０……垂直同期分離回路、
２……同期分周回路（1/8分周回路）、V2……比
較出力、V3……幅狭パルス、V4……幅広パルス、
V1……垂直同期分離出力、１１……比較回路、
１３……（電圧制御型）発振回路。
Figure 1 is a block diagram of an implementation circuit of the present invention;
The figures each show an explanatory diagram of the waveforms of the same main parts. Explanation of main figure numbers, 10...Vertical synchronization separation circuit,
2...Synchronous frequency divider circuit (1/8 frequency divider circuit), V2 ...Comparison output, V3 ...Narrow width pulse, V4 ...Wide pulse,
V 1 ... Vertical synchronization separation output, 11 ... Comparison circuit,
13... (voltage controlled) oscillation circuit.
Claims (1)
と、発振出力を再生水平同期分離出力に同期して
分周してクロツク出力を発生する同期分周回路と
前記発振出力を分周して垂直同期周期相当の比較
出力を導出する分周回路と、前記クロツク出力若
しくはその分周出力を計数入力として正規の垂直
同期分離出力に含まれる幅狭パルスと該垂直同期
分離出力を含む幅広パルスを形成する手段と、前
記垂直同期分離出力と前記幅狭パルスの論理和に
より垂直同期区間に生じるドロツプアウトとを補
償すると共に前記垂直同期分離出力と幅広パルス
の論理積により垂直同期区間外に生ずるドロツプ
アウトの混入を阻止して正規の垂直同期分離出力
を導出する論理回路と、該正規の垂直同期分離出
力を基準入力として前記比較出力との比較を為す
位相比較回路と、該位相比較出力に基づいて発振
周波数をコントロールする発振回路とを備えて成
るPCM再生装置のクロツク発生回路。 A vertical synchronization separation circuit that derives a vertical synchronization separation output, a synchronous frequency divider circuit that divides the oscillation output in synchronization with the regenerated horizontal synchronization separation output to generate a clock output, and a synchronous frequency divider circuit that divides the oscillation output to generate a vertical synchronization period. a frequency dividing circuit for deriving a corresponding comparison output; and means for forming a narrow pulse included in the normal vertical synchronization separated output and a wide pulse containing the vertical synchronization separated output using the clock output or its frequency divided output as a counting input. and a logical sum of the vertical synchronization separation output and the narrow pulse to compensate for dropouts occurring in the vertical synchronization period, and a logical product of the vertical synchronization separation output and the wide pulse to prevent dropouts occurring outside the vertical synchronization period from being mixed in. a logic circuit that derives a regular vertical synchronization separated output, a phase comparison circuit that uses the regular vertical synchronization separation output as a reference input and compares it with the comparison output, and controls an oscillation frequency based on the phase comparison output. 1. A clock generation circuit for a PCM reproducing device, comprising an oscillation circuit for generating a clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17557087U JPH045105Y2 (en) | 1987-11-17 | 1987-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17557087U JPH045105Y2 (en) | 1987-11-17 | 1987-11-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63105964U JPS63105964U (en) | 1988-07-08 |
| JPH045105Y2 true JPH045105Y2 (en) | 1992-02-13 |
Family
ID=31115017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17557087U Expired JPH045105Y2 (en) | 1987-11-17 | 1987-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH045105Y2 (en) |
-
1987
- 1987-11-17 JP JP17557087U patent/JPH045105Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63105964U (en) | 1988-07-08 |
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