JPH0447940A - Production of multilayer printed wiring board - Google Patents
Production of multilayer printed wiring boardInfo
- Publication number
- JPH0447940A JPH0447940A JP2158017A JP15801790A JPH0447940A JP H0447940 A JPH0447940 A JP H0447940A JP 2158017 A JP2158017 A JP 2158017A JP 15801790 A JP15801790 A JP 15801790A JP H0447940 A JPH0447940 A JP H0447940A
- Authority
- JP
- Japan
- Prior art keywords
- prepreg
- layer circuit
- circuit board
- inner layer
- prepregs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000463 material Substances 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 239000011347 resin Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 7
- 238000001035 drying Methods 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 239000004744 fabric Substances 0.000 abstract description 3
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 2
- 239000002966 varnish Substances 0.000 abstract 2
- 239000011521 glass Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 72
- 238000010030 laminating Methods 0.000 description 9
- 239000011888 foil Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 230000032798 delamination Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011437 continuous method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Moulding By Coating Moulds (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
に産業上の利用分野】
本発明は、回路を多層に設けた多層配線板の製造方法に
関するものである。FIELD OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring board in which circuits are provided in multiple layers.
多層配線板Ａは内層回路板２に外層回路材４を積層する
ことによって作成される。すなわち、表面に内層回路１
を設けて形成される内層回路板２に複数枚のプリプレグ
３を介して外層回路材４を重ね、これを加熱加圧して積
層成形することによって作成されるものである。外層回
路材４としては外層回路が形成された外層回路板あるい
は銅箔などの金属箔等が用いられる。外層回路材４とし
て金属箔を用いる場合にはエツチング等の加工して外層
回路を形成して仕上げられる。The multilayer wiring board A is created by laminating an outer layer circuit material 4 on an inner layer circuit board 2. In other words, the inner layer circuit 1 is on the surface.
It is created by stacking an outer layer circuit material 4 on an inner layer circuit board 2 formed by providing a plurality of prepregs 3, and then applying heat and pressure to form a laminated layer. As the outer layer circuit material 4, an outer layer circuit board on which an outer layer circuit is formed, a metal foil such as copper foil, or the like is used. When a metal foil is used as the outer layer circuit material 4, it is finished by processing such as etching to form an outer layer circuit.
しかしこのようにして作成される多層配線板Ａにあって
、内層回路１は内層回路板２の表面から突出した状態で
設けられているために、内層回路板２に接着層３を介し
て外層回路材４を積層するに際して内層回路１の側面部
の空気が抜は難く、第３図に示すようにこの閉じ込めら
れた空気でボイド１０が発生するおそれがある。
そしてこのように多層配線板Ａにボイド１０が発生する
と半田付は時にボイド１０が膨らんでデラミネーシ１ン
（剥離）が発生し、また外層回路材４に回路形成する際
にメツキ液が染み込んで使用時に電食が発生し、絶縁性
能が劣化するという種々の問題が生じるものである。こ
のような問題は、高い加圧力で外層回路材４を積層する
ことができない連続成形工法において、特に多発するも
のであった。
本発明は上記の点に鑑みて為されたものであり、ボイド
の発生を低減することができる多層配線板の製造方法を
提供することを目的とするものである。However, in the multilayer wiring board A produced in this way, since the inner layer circuit 1 is provided in a state protruding from the surface of the inner layer circuit board 2, the outer layer is attached to the inner layer circuit board 2 via the adhesive layer 3. When laminating the circuit materials 4, it is difficult to remove air from the side surfaces of the inner layer circuit 1, and as shown in FIG. 3, this trapped air may cause voids 10. When voids 10 occur in the multilayer wiring board A in this way, the voids 10 sometimes bulge during soldering, causing delamination (peeling), and when forming a circuit on the outer layer circuit material 4, the plating liquid may seep into it. This sometimes causes various problems such as electrolytic corrosion and deterioration of insulation performance. Such problems occur particularly frequently in continuous molding methods in which the outer layer circuit material 4 cannot be laminated with high pressure. The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a multilayer wiring board that can reduce the occurrence of voids.
本発明に係る多層配線板の製造方法は、表面に内層回路
１が形成された内層回路板２に複数枚のプリプレグ３
ａ、 ３ ｂを介して外層回路材４を重ね、これを加熱
成形することによって内層回路板２に外層回路材４を積
層するにあたって、上記複数枚のプリプレグ３ ａｔ
３ ｂとして、内層回路板２に対して外側のプリプレグ
３ａを構成する樹脂の硬化速度が内側のプリプレグ３ｂ
を構成する樹脂の硬化速度よりも遅いものを用いて作成
されたものを使用することを特徴とするものである。The method for manufacturing a multilayer wiring board according to the present invention includes a method of manufacturing a multilayer wiring board by forming a plurality of prepregs 3 on an inner layer circuit board 2 having an inner layer circuit 1 formed on the surface thereof.
When laminating the outer layer circuit material 4 on the inner layer circuit board 2 by overlapping the outer layer circuit material 4 via the layers a and 3 b and heat-forming it, the plurality of prepregs 3 at
3b, the curing speed of the resin constituting the outer prepreg 3a with respect to the inner layer circuit board 2 is higher than that of the inner prepreg 3b.
It is characterized by using a material made of a material whose curing speed is slower than that of the resin constituting the material.
本発明にあっては、内層回路板２に外層回路材４を積層
するための複数枚のプリプレグ３１Ｌｔ ３ ｂとして
、内層回路板２に対して外側のプリプレグ３ａを構成す
る樹脂の硬化速度が内側のプリプレグ３ｂを構成する樹
脂の硬化速度よりも遅いものを用いて作成されたものを
使用することによって、外側のプリプレグ３ａは内層回
路板２に接する内側のプリプレグ３ｂよりも硬化が遅く
始まることになり、この外側のプリプレグ３ａのクッシ
タン作用で内層回路１の側面部に樹脂を充ＪＩＥさせて
この部分にボイドが発生することを防ぐことができる。In the present invention, as a plurality of prepregs 31Lt 3 b for laminating the outer layer circuit material 4 on the inner layer circuit board 2, the curing speed of the resin constituting the outer prepreg 3a with respect to the inner layer circuit board 2 is set to the inner layer. By using a prepreg 3b made of a material that is slower than the curing speed of the resin constituting the prepreg 3b, the outer prepreg 3a starts to harden later than the inner prepreg 3b that is in contact with the inner layer circuit board 2. This makes it possible to fill the side surface of the inner layer circuit 1 with resin due to the cushitan action of the outer prepreg 3a, thereby preventing the generation of voids in this portion.
以下本発明を実施例によって詳述する。
内層回路板２は、例えば、プラス布等の基材にエポキシ
樹脂等の熱硬化性樹脂フェスを含浸して乾燥することに
よって調製した複数枚のプリプレグを重ねると共に、こ
の片側もしくは両側の外面に銅箔等の金属箔を重ね、こ
れを加熱加圧して積層成形することによって金属箔張り
積層板を作成し、そしてこの積層板の金属箔にエツチン
グ加工等して内層回路１を形成することによって、製造
することがでさる。従ってこの内層回路板２において内
層回路１は内層回路板２の表面に突出するように設けら
れている。
このように作成した内層回路板２の表面に複数枚のプリ
プレグ３ ａ、 ３ ｂを介して外層回路材４を積層す
ることによって、多層配線板を製造することができる。
ここで、外層回路材４としては銅箔等の金属箔や、内層
回路板２と同様にして外層回路を形成した外層回路板を
用いることができる。
またプリプレグ３ ａ、 ３ ｂは既述したようにして
作成することができるが、この複数枚のプリプレグ３
ａ、 ３ ｂとしては、内層回路板２に対して外側のプ
リプレグ３ａを構成する樹脂の硬化速度が内側のプリプ
レグ３ｂを構成する樹脂の硬化速度よりも遅いものを用
いて作成されたものを使用するようにしている。例えば
第１図の実施例のように内層回路板２の表面に二枚のプ
リプレグ３ａ、３ｂを介して外層回路材４を重ね、これ
を積層成形する場合には、外側のプリプレグ３ａはその
含浸した樹脂の硬化速度を、内側プリプレグ３ｂに含浸
した樹脂の硬化速度よりも遅くなるようにｌｌＮ整する
ものである。この硬化速度の差は例えば１６０℃におけ
るデルタイムが、外側のプリプレグ３ａが内側のプリプ
レグ３ｂよりも３０〜１２０秒長くなるように設定する
のが好ましい。このようにプリプレグ３ ＋１ｔ ３
ｂの樹脂に硬化速度の差を付けるには、樹脂や硬化剤の
組成に差を付けて調整したり、プリプレグ３ ａｔ ３
ｂを作成する際の加熱乾燥条件に差を付けてｍ整した
りすることによっておこなうことができ、その方法は任
意である０例えば、プラス布にエポキシ樹脂フェスを含
浸して加熱乾燥することによってプリプレグ３ｍ、３ｂ
を作成するにあたって、エポキシ樹脂フェスの１６０℃
でのデルタイムが２００秒の場合、１７０℃で５分間加
熱して乾燥すると、デルタイムが１２０秒のプリプレグ
３ａを調製することができ、また１７０℃で５．５分間
加熱して乾燥すると、ｒルタイムが５０秒のプリプレグ
３ｂを調製することができる。
そしてこのように内層回路板２の表面に複数枚のプリプ
レグ３ ａ、 ３ ｂを介して外層回路材４を重ね、こ
れを加熱・加圧して積層成形してプリプレグ３ａ、３ｂ
を介して内層回路板２に外層回路材４を積層するにあっ
て、複数枚のプリプレグ３ａ、３ｂの硬化速度が同じで
あると加熱は外側のプリプレグ３ａに先に作用するため
に外側のプリプレグ３ａが先に硬化してしまい、この外
側のプリプレグ３ａをクツションにして内側のプリプレ
グ３ｂから溶融して流れ出す樹脂を内層回路板２の表面
から突出する内層回路１の側面部に充填させることが難
しいが、本発明では外側のプリプレグ３ａの硬化速度を
内側のプリプレグ３ｂの硬化速度よりも遅くしであるた
めに、外側のプリプレグ３ａは内側のプリプレグ３ｂよ
りも硬化が遅く始まることになり、外側のプリプレグ３
ａのクツション作用で内側のプリプレグ３ｂから溶融し
て流れ出す樹脂を内層回路１の側面部に充填させること
かでき、この部分に空気が残ってボイドが発生すること
を防ぐことができるものである。
第２図の実施例では、プリプレグ３ａ、３ｂとして長尺
帯状のものを、外層回路材４として長尺帯状の金属箔を
それぞれ用い、連続工法で外層回路材４の積層をおこな
うようにしている。すなわち、プリプレグ３ ａｔ ３
ｂと外層回路材４をそれぞれ繰り出して連続して送り
つつプリプレグ３ ａｔ ３ ｂを介して内層回路板２
の表面に外層回路材４を重ね、これを加熱された成形ロ
ール１２に通して加熱加圧することによって、連続した
流れで内層回路板２にプリプレグ３ａ、３ｂを介して外
層回路材４を積層することができるものである。このよ
うな連続工法で外層回路材４を積層する場合には、大き
な圧力で加圧することができないために空電を追い出す
ことが難しくボイドが発生し易いが、本発明のように外
側のプリプレグ３ａとして内側のプリプレグ３ｂよりも
硬化速度の遅いものを用いることによって、連続工法に
おいてもボイドの発生をな、くすことが可能になるもの
である。ちなみに、従来の方法で製造した多層配線板で
は、１０ｃ＋ｗＸ１０ｃｍの範囲に１〜３個のボイドが
発生し、半田耐熱試験（Ｄ−２／１００．２６０℃、３
０秒）条件）ヲオコナウとデラミネーシヨンが発生した
が、本発明の方法で製造した多層配線板では、ボイドの
発生は０個であり、デラミネーシヨンも発生しなかった
。The present invention will be explained in detail below with reference to Examples. The inner layer circuit board 2 is made of, for example, a plurality of sheets of prepreg prepared by impregnating a base material such as plastic cloth with a thermosetting resin face such as epoxy resin and drying the prepreg, and also coating copper on the outer surface of one or both sides. A metal foil clad laminate is created by stacking metal foil such as foil, heating and pressurizing it to form a laminate, and then etching the metal foil of this laminate to form the inner layer circuit 1. It is possible to manufacture it. Therefore, in this inner layer circuit board 2, the inner layer circuit 1 is provided so as to protrude from the surface of the inner layer circuit board 2. A multilayer wiring board can be manufactured by laminating the outer layer circuit material 4 on the surface of the inner layer circuit board 2 created in this way via a plurality of prepregs 3 a and 3 b. Here, as the outer layer circuit material 4, metal foil such as copper foil or an outer layer circuit board on which an outer layer circuit is formed in the same manner as the inner layer circuit board 2 can be used. Further, the prepregs 3a and 3b can be produced as described above, but if the prepregs 3a and 3b are
For a and 3b, those made using a resin that makes up the outer prepreg 3a with respect to the inner layer circuit board 2 have a curing speed that is slower than the curing speed of the resin that makes up the inner prepreg 3b. I try to do that. For example, when the outer layer circuit material 4 is layered on the surface of the inner layer circuit board 2 via two prepregs 3a and 3b and is laminated and molded as in the embodiment shown in FIG. The curing speed of the resin is adjusted to be slower than the curing speed of the resin impregnated into the inner prepreg 3b. This difference in curing speed is preferably set such that the del time at 160° C. is 30 to 120 seconds longer for the outer prepreg 3a than for the inner prepreg 3b. Prepreg 3 + 1t 3 like this
To create different curing speeds for the resins in b, you can adjust the compositions of the resins and curing agents differently, or prepreg
This can be done by adjusting the heat drying conditions when creating b, and the method is arbitrary. For example, by impregnating plus cloth with epoxy resin face and heating and drying it. Prepreg 3m, 3b
In creating the epoxy resin festival at 160℃
When the del time is 200 seconds at It is possible to prepare prepreg 3b with a heating time of 50 seconds. Then, in this way, the outer layer circuit material 4 is stacked on the surface of the inner layer circuit board 2 via a plurality of prepregs 3 a, 3 b, and this is heated and pressurized to form a laminated layer to form the prepregs 3 a, 3 b.
When laminating the outer layer circuit material 4 on the inner layer circuit board 2 via the inner layer circuit board 2, if the curing speed of the plurality of prepregs 3a and 3b is the same, the heating acts on the outer prepreg 3a first. 3a hardens first, and it is difficult to use the outer prepreg 3a as a cushion and fill the side surface of the inner circuit 1 protruding from the surface of the inner circuit board 2 with the resin that melts and flows from the inner prepreg 3b. However, in the present invention, since the curing speed of the outer prepreg 3a is slower than the curing speed of the inner prepreg 3b, the outer prepreg 3a starts curing later than the inner prepreg 3b, and the outer prepreg 3a starts to harden later than the inner prepreg 3b. Prepreg 3
By the cushioning action of a, the resin melted and flowing out from the inner prepreg 3b can be filled into the side surface of the inner layer circuit 1, and air can be prevented from remaining in this region and creating voids. In the embodiment shown in FIG. 2, long strip-shaped prepregs 3a and 3b are used, and long strip-shaped metal foil is used as the outer layer circuit material 4, and the outer layer circuit material 4 is laminated by a continuous method. . That is, prepreg 3 at 3
The inner layer circuit board 2 is fed through the prepreg 3 at 3 b while continuously feeding the outer layer circuit board 4 and the prepreg 3 at 3 b.
The outer layer circuit material 4 is layered on the surface of the inner layer circuit board 2 and is heated and pressurized by passing it through a heated forming roll 12, thereby laminating the outer layer circuit material 4 on the inner layer circuit board 2 via the prepregs 3a and 3b in a continuous flow. It is something that can be done. When laminating the outer layer circuit material 4 using such a continuous construction method, it is difficult to expel static electricity and voids are likely to occur because it is not possible to pressurize with a large pressure. By using a prepreg with a slower curing speed than the inner prepreg 3b, it is possible to eliminate the generation of voids even in continuous construction methods. By the way, in the multilayer wiring board manufactured by the conventional method, 1 to 3 voids occur in the range of 10c+w x 10cm, and the solder heat resistance test (D-2/100.260℃, 3
0 seconds) Conditions) Delamination and delamination occurred, but in the multilayer wiring board manufactured by the method of the present invention, no voids were generated and no delamination occurred.
上述のように本発明にあっては、表面に内層回路が形成
された内層回路板に複数枚のプリプレグを介して外層回
路材を重ね、これを加熱成形することによって内層回路
板に外層回路材を積層するにあたって、上記複数枚のプ
リプレグとして、内層回路板に対して外側のプリプレグ
を構成する樹脂の硬化速度が内側のプリプレグを構成す
る樹脂の硬化速度よりも遅いものを用いて作成されたも
のを使用するようにしたので、外側のプリプレグは内層
回路板に接する内側のプリプレグよりも硬化が遅く始ま
ることになり、この外側のプリプレグのクツション作用
で内層回路の側面部に樹脂を良好に充填させることでき
、この部分にボイドが発生することを低減できるもので
ある。As described above, in the present invention, the outer layer circuit material is stacked on the inner layer circuit board with the inner layer circuit formed on the surface via a plurality of prepregs, and the outer layer circuit material is placed on the inner layer circuit board by heating and molding this. In laminating the above-mentioned plural prepregs, the curing speed of the resin constituting the outer prepreg with respect to the inner layer circuit board is slower than the curing speed of the resin constituting the inner prepreg. As a result, the outer prepreg begins to harden later than the inner prepreg that is in contact with the inner layer circuit board, and the cushioning effect of this outer prepreg allows the side surfaces of the inner layer circuit to be well filled with resin. This makes it possible to reduce the occurrence of voids in this portion.
第１図は本発明の一実施例の概略断面図、第２図は同上
の連続工法を示す概略図、＃５３図は従来例の多層配線
板の断面図である。
１は内層回路、２は内層回路板、３ａ、３ｂはプリプレ
グ、４は外層回路材である。FIG. 1 is a schematic sectional view of an embodiment of the present invention, FIG. 2 is a schematic diagram showing the same continuous construction method, and FIG. 53 is a sectional view of a conventional multilayer wiring board. 1 is an inner layer circuit, 2 is an inner layer circuit board, 3a and 3b are prepregs, and 4 is an outer layer circuit material.
Claims (1)
のプリプレグを介して外層回路材を重ね、これを加熱成
形することによつて内層回路板に外層回路材を積層する
にあたって、上記複数枚のプリプレグとして、内層回路
板に対して外側のプリプレグを構成する樹脂の硬化速度
が内側のプリプレグを構成する樹脂の硬化速度よりも遅
いものを用いて作成されたものを使用することを特徴と
する多層配線板の製造方法。(1) In stacking the outer layer circuit material on the inner layer circuit board with the inner layer circuit formed on the surface via a plurality of prepregs and heat forming this, the outer layer circuit material is laminated on the inner layer circuit board. It is characterized by using a plurality of sheets of prepreg that are made using a material in which the curing speed of the resin constituting the outer prepreg is slower than the curing speed of the resin constituting the inner prepreg relative to the inner layer circuit board. A method for manufacturing a multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2158017A JPH074915B2 (en) | 1990-06-15 | 1990-06-15 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2158017A JPH074915B2 (en) | 1990-06-15 | 1990-06-15 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0447940A true JPH0447940A (en) | 1992-02-18 |
| JPH074915B2 JPH074915B2 (en) | 1995-01-25 |
Family
ID=15662454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2158017A Expired - Lifetime JPH074915B2 (en) | 1990-06-15 | 1990-06-15 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH074915B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056176A (en) * | 2008-08-26 | 2010-03-11 | Panasonic Electric Works Co Ltd | Method of manufacturing multilayer printed wiring board |
| CN103538264A (en) * | 2012-07-10 | 2014-01-29 | 四平市方元恒业复合材料科技有限公司 | Method for reducing voidage of glass steel |
| WO2021201252A1 (en) * | 2020-04-03 | 2021-10-07 | パナソニックＩｐマネジメント株式会社 | Thermosetting resin sheet and printed circuit board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58224750A (en) * | 1982-06-24 | 1983-12-27 | アイカ工業株式会社 | Manufacture of melamine-resin decorative material |
| JPS5989145A (en) * | 1982-11-13 | 1984-05-23 | 松下電工株式会社 | Manufacture of laminated board |
| JPS61146537A (en) * | 1984-12-21 | 1986-07-04 | 新神戸電機株式会社 | Manufacture of composite laminated board |
-
1990
- 1990-06-15 JP JP2158017A patent/JPH074915B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58224750A (en) * | 1982-06-24 | 1983-12-27 | アイカ工業株式会社 | Manufacture of melamine-resin decorative material |
| JPS5989145A (en) * | 1982-11-13 | 1984-05-23 | 松下電工株式会社 | Manufacture of laminated board |
| JPS61146537A (en) * | 1984-12-21 | 1986-07-04 | 新神戸電機株式会社 | Manufacture of composite laminated board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056176A (en) * | 2008-08-26 | 2010-03-11 | Panasonic Electric Works Co Ltd | Method of manufacturing multilayer printed wiring board |
| CN103538264A (en) * | 2012-07-10 | 2014-01-29 | 四平市方元恒业复合材料科技有限公司 | Method for reducing voidage of glass steel |
| WO2021201252A1 (en) * | 2020-04-03 | 2021-10-07 | パナソニックＩｐマネジメント株式会社 | Thermosetting resin sheet and printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH074915B2 (en) | 1995-01-25 |
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