JPH0445980B2 - - Google Patents
Info
- Publication number
- JPH0445980B2 JPH0445980B2 JP57022521A JP2252182A JPH0445980B2 JP H0445980 B2 JPH0445980 B2 JP H0445980B2 JP 57022521 A JP57022521 A JP 57022521A JP 2252182 A JP2252182 A JP 2252182A JP H0445980 B2 JPH0445980 B2 JP H0445980B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- recess
- semiconductor substrate
- substrate
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000012530 fluid Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、フイールド領域に比較的に厚い絶縁
膜を埋め込む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device in which a relatively thick insulating film is embedded in a field region.
半導体としてシリコンを用いた半導体装置、特
にMOS型半導体装置においては寄生チヤンネル
による絶縁不良をなくし、かつ寄生容量を小さく
するために素子間のいわゆるフイールド領域に厚
い絶縁膜を形成する事が行われている。
In semiconductor devices that use silicon as a semiconductor, especially MOS type semiconductor devices, a thick insulating film is formed in the so-called field region between elements in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance. There is.
従来このような素子間分離法としては選択酸化
法が良く知られている。これは素子形成領域を耐
酸化性マスク、代表的にはシリコン窒化膜で覆
い、高温酸化を行つてフイールド領域に選択的に
厚い酸化膜を形成する方法である。しかしこのよ
うな選択酸化法においては上記高温酸化中、シリ
コン窒化膜の端部からフイールド酸化膜が鳥のく
ちばし（バーズピーク）状に食い込み、これが素
子形成領域の寸法誤差の原因となり、また集積回
路の高集積化の妨げとなる。 A selective oxidation method is conventionally well known as such an element isolation method. This is a method in which the element formation region is covered with an oxidation-resistant mask, typically a silicon nitride film, and high-temperature oxidation is performed to selectively form a thick oxide film in the field region. However, in this selective oxidation method, during the high-temperature oxidation, the field oxide film digs into the edge of the silicon nitride film in the shape of a bird's beak (bird's peak), which causes dimensional errors in the element formation area and also causes problems in integrated circuits. This hinders high integration.
またこのような従来の選択酸化法においては、
フイールド酸化膜を形成後フイールド領域と素子
形成領域にフイード酸化膜厚（約0.7〜1.0μｍ）
の約半分程度の表面段差が形成される。 In addition, in such conventional selective oxidation methods,
After forming the field oxide film, apply a feed oxide film thickness (approximately 0.7 to 1.0 μm) to the field area and element formation area.
A surface level difference of about half is formed.
これが後々の工程まで段差として残るため、そ
の後のリングラフイー精度の低下や金属配線の段
差部での信頼性を下げる原因となつていた。 This remains as a step until subsequent processes, resulting in a subsequent drop in ring graphie accuracy and reliability at the step portion of the metal wiring.
これに対し、上記バーズピークをなくし、しか
も平坦にフイールド酸化膜を埋め込む方法が
BOX（Ｂ＝urying Ｏ＝ｘ＝ide into Silicon Groove）
として知られている。 On the other hand, there is a method that eliminates the bird's peak and embeds the field oxide film flatly.
BOX (B=urying O=x=ide into Silicon Groove)
known as.
BOX法を第１図を用いて簡単に説明する。 The BOX method will be briefly explained using Figure 1.
まず、第１図ａに示すように、例えばシリコン
基板１を用意して、通常の写真食刻工程により素
子形成領域をマスク２で覆い、フイールド領域の
シリコン基板１を所望のフイールド膜厚分相当エ
ツチングする。次に、第１図ｂに示すように、同
じマスク２を用いてフイールド領域にフイールド
反転防止のためにシリコン基板１と同導型の不純
物３、例えばＰ型基板の場合はボロンをイオン注
入する。その後、第１図ｃに示すようにリフトオ
フ加工法を用いてフイード領域にシリコン酸化膜
４を埋め込む。なお、このリフトオフ加工法は次
のように行う。即ち、全面に例えばPlasma
CVD SiO2膜を堆積する。 First, as shown in FIG. 1a, for example, a silicon substrate 1 is prepared, and an element formation area is covered with a mask 2 by a normal photolithography process, and the silicon substrate 1 in the field area is covered with a mask 2 corresponding to the desired field film thickness. Etching. Next, as shown in FIG. 1b, using the same mask 2, impurity 3 of the same conductivity type as the silicon substrate 1, for example boron in the case of a P-type substrate, is ion-implanted into the field region to prevent field inversion. . Thereafter, as shown in FIG. 1c, a silicon oxide film 4 is embedded in the feed region using a lift-off process. Note that this lift-off processing method is performed as follows. That is, for example, Plasma is applied to the entire surface.
Deposit CVD SiO2 film.
次に、例えば弗化アンモニウムで１分程度エツ
チングしてやると、フイールド領域と素子形成領
域の境界にできている段差部の側面に堆積した
PlasmaCVDSiO2膜は平坦部に比べてエツチング
速度が３〜20倍はやいため、上記段差部側面の
Plasma CVD SiO2膜が選択的に除去される。そ
の後、素子形成領域上のマスク２を除去するとマ
スク２上に堆積したPlasma CVD SiO2膜も一緒
に除去され、フイールド領域にのみPlasma
CVD SiO2膜４が埋め込まれる。この時フイール
ド領域と素子形成領域の境界には第１図ｃに示す
ように断面形状が一定の細い溝５が残される。 Next, when etching is performed for about 1 minute with ammonium fluoride, for example, deposits are deposited on the side surfaces of the step formed at the boundary between the field region and the element formation region.
The etching rate of PlasmaCVDSiO 2 film is 3 to 20 times faster than on flat areas, so
Plasma CVD SiO 2 film is selectively removed. After that, when the mask 2 on the element formation area is removed, the Plasma CVD SiO 2 film deposited on the mask 2 is also removed, and the Plasma CVD SiO 2 film is removed only in the field area.
A CVD SiO 2 film 4 is embedded. At this time, a narrow groove 5 with a constant cross-sectional shape is left at the boundary between the field region and the element forming region, as shown in FIG. 1c.
次に、第１図ｄ示すように、上記細い溝５を例
えばCVD SiO2膜６で均一に埋め込むとCVD
SiO2膜６表面には、上記細い溝５の上に一定の
凹部７ができる。次に、流動性でかつ上記CVD
SiO2膜６とエツチング速度が等しくなるような
被膜８を形成し、上記凹部７を埋め込みかつ表面
を平坦にする。その後、第１図ｅに示ように、上
記流動性被膜８およびCVD SiO2膜６を均一にエ
ツチング除去し、さらにエツチングを行ない、素
子形成領域のシリコンを露出させると、フイール
ド領域はほぼ平坦にCVD SiO2膜４とPlasma
CVD SiO2膜６で埋め込まれる。その後素子形成
領域に通常の方法により所望の素子を形成するも
のである。 Next, as shown in FIG .
A certain recess 7 is formed on the surface of the SiO 2 film 6 above the narrow groove 5 . Next, liquidity and the above CVD
A film 8 having an etching rate equal to that of the SiO 2 film 6 is formed to fill the recess 7 and flatten the surface. Thereafter, as shown in FIG. 1e, the fluid film 8 and the CVD SiO 2 film 6 are uniformly etched away, and further etching is performed to expose the silicon in the element formation region, so that the field region becomes almost flat. CVD SiO 2 film 4 and Plasma
It is filled with a CVD SiO 2 film 6. Thereafter, desired elements are formed in the element forming region by a conventional method.
このようなBOX法においては、シリコン基板
のエツチングにサイドエツチングのない反応性イ
オンエツチング（RIE）を用いる事により、素子
領域の寸法は写真食刻工程により形成したマスク
寸法によつてのみ規定され、素子形成領域の寸法
誤差を零にする事が可能になる。 In this BOX method, by using reactive ion etching (RIE) without side etching to etch the silicon substrate, the dimensions of the element area are defined only by the dimensions of the mask formed by the photolithography process. It becomes possible to reduce the dimensional error of the element formation region to zero.
また表面が完全に平坦な構造が得られるように
なつたため、その後のリングライフイー精度が上
がりまた配線の信頼性も著しく向上させる事がで
きる。 In addition, since a structure with a completely flat surface can be obtained, the subsequent ring life accuracy and wiring reliability can be significantly improved.
しかしながら、この種の方法では前記第１図ｄ
に示されるCVD SiO2膜６の表面の一定の凹部７
を平坦にすることが困難である。即ち、上記
CVD SiO2膜６を堆積した後、表面を平坦にする
ために流動性被膜８を形成するが、上記一定の凹
部７に流動性被膜８が十分入り込まず空洞が出来
る場合がある。そのため、均一なエツチングを行
なつても上記空洞が残り平坦化できない。さら
に、BOX工程においては、分離領域に形成する
凹部の寸法が小さくなると、前記第１の絶縁膜の
形成において凹部に第１の絶縁膜が残らなくな
る。即ち、第１の絶縁膜として前述のように
Plasma CVD SiO2膜を用いると寸法の小さい凹
部においては、Plasma CVD SiO2膜のリフトオ
フ加工中に上記凹部内のPlasma CVD SiO2膜は
全部除去されてしまう。 However, in this type of method, the above-mentioned FIG.
Certain depressions 7 on the surface of the CVD SiO 2 film 6 shown in
It is difficult to flatten the surface. That is, the above
After depositing the CVD SiO 2 film 6, a fluid film 8 is formed to flatten the surface, but the fluid film 8 may not fully enter the certain recesses 7, creating cavities. Therefore, even if uniform etching is performed, the cavity remains and cannot be flattened. Furthermore, in the BOX process, when the dimensions of the recess formed in the isolation region become smaller, no first insulating film remains in the recess when forming the first insulating film. That is, as the first insulating film, as described above,
When a Plasma CVD SiO 2 film is used, in a recess with small dimensions, the entire Plasma CVD SiO 2 film inside the recess is removed during lift-off processing of the Plasma CVD SiO 2 film.
したがつて、寸法の小さい凹部は、第２の絶縁
膜例えばCVD SiO2膜で平坦に埋め込む必要があ
る。しかし、Si基板１の凹部の寸法が小さくな
と、第２図ａに示す如く空洞９ａが形成された
り、また埋め込まれても同図ｂに示す如く酸化膜
４の密度が低くなり、後続するNH4Fのエツチン
グ時に密度の低い所に比してエツチレートが速く
なり、溝ができてしまう。 Therefore, it is necessary to fill the small-sized recesses flatly with a second insulating film, for example, a CVD SiO 2 film. However, if the dimensions of the recessed portion of the Si substrate 1 are small, a cavity 9a is formed as shown in FIG. When etching with NH 4 F, the etching rate is faster than in areas with low density, resulting in grooves.
したがつて、Si基板１の凹部の寸法が小さくな
るとその平坦化を行うことは困難であつた。 Therefore, when the size of the recessed portion of the Si substrate 1 becomes small, it is difficult to planarize the recessed portion.
本発明の目的は、素子形成領域とフイールド領
域との表面を完全に平坦化することができ、かつ
フイールド領域の凹部の寸法が小さくなつてもこ
の平坦化を確実に行うことができ、半導体装置の
電気的特性および製造歩留りの向上に寄与し得る
半導体装置の製造方法を提供することにある。
It is an object of the present invention to completely flatten the surfaces of an element formation region and a field region, and to reliably perform this flattening even when the dimensions of a recess in the field region become small. An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to improving the electrical characteristics and manufacturing yield of a semiconductor device.
本発明は、半導体装置を製造するに際し、半導
体基板の素子形成領域上に第１の被膜を形成した
のちこの第１の被膜をマスクとして半導体基板を
選択エツチングして該基板のフイールド領域に凹
部を形成し、次いでリフトオフ法を用い上記凹部
に周辺に溝が形成された状態で絶縁性の第２の被
膜を埋め込み、次いで第２の被膜および半導体基
板上に上記溝を埋める如く絶縁性の第３の被膜を
被着し、この第３の被膜上に酸化工程により絶縁
膜となる第４の被膜を被着したのち第４の被膜の
少なくとも一部を酸化し、次いで第４の被膜上を
平坦化し、しかるのち第４の被膜から全面エツチ
ングを施し半導体基板の素子形成領域のみを露出
せしるようにした方法である。
In manufacturing a semiconductor device, the present invention forms a first film on an element formation region of a semiconductor substrate, and then selectively etches the semiconductor substrate using the first film as a mask to form a recess in a field region of the substrate. Then, using a lift-off method, a second insulating film is buried in the recess with a groove formed around the periphery, and then a third insulating film is formed on the second film and the semiconductor substrate so as to fill the groove. After depositing a fourth film that becomes an insulating film on this third film through an oxidation process, at least a part of the fourth film is oxidized, and then the fourth film is flattened. In this method, the entire surface of the fourth film is etched to expose only the element formation region of the semiconductor substrate.
本発明によれば、第３の被膜の形成後カバーレ
ツジの良い第４の被膜を第３の被膜の空洞部或い
は密度の低い所に設け、この第４の被膜を酸化す
ることにより、上記空洞部に絶縁を埋め込んだ
り、上記低密度部をエツチングに対して保護する
ことがきる。このため、Si基板のフイールド領域
の凹部の寸法が小さい場合にあつても、平坦化を
容易に行うことができる。
According to the present invention, after the formation of the third coating, a fourth coating with good coverage is provided in the cavity or a low density area of the third coating, and by oxidizing the fourth coating, the cavity is removed. The low-density portions can be protected from etching. Therefore, even if the size of the recess in the field region of the Si substrate is small, planarization can be easily performed.
また、第３の被膜のエツチング条件がそれ程き
びしくならなくなり、Si基板の凹部の寸法に拘わ
らず、全ての凹部を絶縁膜で平坦に埋め込むこと
ができる。また、凹部内に埋め込まれた絶縁性の
第２の被膜及び基板上に形成された絶縁性の第３
の被膜上に、酸化工程により絶縁膜となる第４の
被膜を形成しているので、第４の被膜の酸化時に
該被膜の膨脹に起因して基板に加わるストレス及
び基板表面の不純物の再拡散を少なくすることが
できる。したがつて、製作のマージンが大きくと
れ、半導体表面の凹凸がなくなることから半導体
装置の信頼性向上をはかり得る。 Furthermore, the etching conditions for the third film are not so severe, and all the recesses can be flatly filled with the insulating film regardless of the dimensions of the recesses in the Si substrate. In addition, an insulating second film embedded in the recess and an insulating third film formed on the substrate are provided.
Since the fourth film, which becomes an insulating film, is formed on the film by an oxidation process, the stress applied to the substrate due to the expansion of the fourth film and the re-diffusion of impurities on the substrate surface are reduced when the fourth film is oxidized. can be reduced. Therefore, the manufacturing margin can be increased and the reliability of the semiconductor device can be improved because the unevenness on the semiconductor surface is eliminated.
第３図ａ〜ｆは本発明の一実施例に係わる半導
体装置のの製造工程を示す断面図である。まず、
第３図ａに示すように半導体基体、例えば面方位
（100）比抵抗５〜50Ωcm程度のＰ型のシリコン基
板１１を用意し、この基板１１上に例えば厚さ
500Å程度の熱酸化膜１２を形成して、該素子形
成領域をレジスト膜１３（第１の被膜）で覆う。
次に、第３図ｂに示すように、本発明の方法によ
りレジスト膜１３をマスクにして、ボロンのイオ
ン注入を例えば120KeVで行うと射影飛程は0.45μ
ｍであり標準偏差0.11μｍ横方向広がり0.14μｍで
１４に示すように分布する。その後、例えば反応
性イオンエツチング技術で同じレジスト膜１３を
マスクにして、フイールド部のシリコンを前記イ
オン注入により導入された不純物分布のピークよ
り深く0.8μｍ程度エツチングして凹部をつくる。
その後、第３図ｃに示すようにやはり同じマスク
を用いて凹部底面にボロンイオンを20から
30KeV程度の加速電圧で２回目のイオン注入を
行う。次に、第１図ｄに示すように全面に
Plasma CVD膜を堆積し、前述の方法によりフ
イールド領域と素子形成領域の境界に断面形状が
ほぼ一定の細い溝１５を残して、フイールド領域
にPlasma CVD SiO2膜１６（第２の被膜）を残
す。なお、このCVD膜１６の代りにはスパツタ
蒸着したSiO2膜、又はリン、ヒ素、ボロンを含
んだ酸化膜でも良い。
3a to 3f are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. first,
As shown in FIG. 3a, a semiconductor substrate, for example, a P-type silicon substrate 11 with a plane orientation (100) and a specific resistance of about 5 to 50 Ωcm is prepared, and a
A thermal oxide film 12 of about 500 Å is formed, and the element formation region is covered with a resist film 13 (first film).
Next, as shown in FIG. 3b, when boron ions are implanted at 120 KeV using the method of the present invention using the resist film 13 as a mask, the projected range is 0.45 μ.
m, and is distributed as shown in Figure 14 with a standard deviation of 0.11 μm and a lateral spread of 0.14 μm. Thereafter, using the same resist film 13 as a mask, the silicon in the field portion is etched approximately 0.8 μm deeper than the peak of the impurity distribution introduced by the ion implantation, using, for example, reactive ion etching technology to form a recess.
After that, as shown in Figure 3c, using the same mask, boron ions are applied to the bottom of the recess from 20 to
A second ion implantation is performed at an accelerating voltage of about 30 KeV. Next, as shown in Figure 1 d,
A Plasma CVD film is deposited, and a thin groove 15 with a substantially constant cross-sectional shape is left at the boundary between the field region and the element formation region using the method described above, and a Plasma CVD SiO 2 film 16 (second film) is left in the field region. . Note that instead of this CVD film 16, a sputter-deposited SiO 2 film or an oxide film containing phosphorus, arsenic, and boron may be used.
次に、第１図ｅに示すように全面に例えば
CVD法によるSiO2膜１７（第３の被膜）を1μｍ
程度堆積し、さらにこのSiO2膜１７上Poly−Si
１８（第４被膜）をCVD法により500Å厚さに堆
積する。次に第３図ｆに示すように上記Poly−
Si１８をスチーユ酸化法により酸化しSiO2膜２
０に変質せしめる。このときSiO2膜２０の体積
が約２倍となるため、凹部１９は完全に埋め込ま
れる。 Next, as shown in Figure 1e, for example,
1 μm SiO 2 film 17 (third film) by CVD method
Poly-Si is further deposited on this SiO 2 film 17.
18 (fourth film) is deposited to a thickness of 500 Å by CVD. Next, as shown in Figure 3 f, the above Poly-
Oxidize Si18 by still oxidation method to form SiO2 film 2
Transforms into 0. At this time, the volume of the SiO 2 film 20 is approximately doubled, so the recess 19 is completely filled.
次に、第３図ｆに示す如くSiO2膜２０上に
SiO2間２０の表面を平坦化する事が可能な被膜
２１を形成し、表面平坦化する。次に第３図ｇに
示すように上記被膜２１およびSiO2膜２０，１
７を均一にエツチングし、フイールド領域にシリ
コン酸化膜をほぼ平坦に埋め込む。 Next, as shown in FIG .
A film 21 capable of flattening the surface of the SiO 2 space 20 is formed to flatten the surface. Next, as shown in FIG. 3g, the coating 21 and the SiO 2 films 20, 1
7 is uniformly etched, and a silicon oxide film is buried almost flat in the field region.
ここで被膜２１としては、レジストを塗布して
も良いし、溶融可能なガラス膜例えばリン硅化ガ
ラス、リン−ボロン硅化ガラス膜などを形成後溶
融して平坦化しても良い。この後、半導体基板に
MOS型半導体素子を形成する。 Here, as the coating 21, a resist may be applied, or a meltable glass film such as phosphorus silicide glass or phosphorus-boron silicide glass may be formed and then melted and flattened. After this, on the semiconductor substrate
A MOS type semiconductor element is formed.
かくして本実施例方法によれば、Si基板１１の
素子形成領域とフイールド領域との表面を略完全
に平坦化することができる。また、第３被膜とし
てのPoly−Si１８はカバーレツジがよく凹部１
９の全ての部位に均一に形成され、さらに酸化処
理により絶縁膜２０となり、その体積が２倍に増
えるので、上記凹部１９の表面は滑らかなものに
なる。このため、平坦化膜２１の形成が容易とな
り、この部分で空洞ができる必要もなくなり、さ
らに寸法の小さい凹部においても平坦化は容易と
なる。 Thus, according to the method of this embodiment, the surfaces of the element formation region and field region of the Si substrate 11 can be almost completely flattened. In addition, Poly-Si18 as the third film has good coverage in the recesses 1.
The insulating film 20 is formed uniformly on all parts of the recess 19 and is further oxidized to become an insulating film 20, which doubles in volume, so that the surface of the recess 19 becomes smooth. Therefore, it becomes easy to form the flattening film 21, there is no need to create a cavity in this part, and furthermore, even small-sized recesses can be flattened easily.
なお、本実施例ではＰ型基板を用いる場合につ
いてのみ述べたが、Ｎ型基板の場合に適用できる
のは勿論のことてある。さらに、ＮとＰとが同時
に存在するＣ−MOSの製造に適用することも可
能である。また、前記第３の被膜としてPoly−
Siで説明したが、この代りには酸化工程により体
積が増加し絶縁物となり、かつカバーレツジの良
いものであればよい。さらに、第３の被膜は最初
から絶縁膜であつてもよい。 In this embodiment, only the case where a P-type substrate is used has been described, but it is of course applicable to the case where an N-type substrate is used. Furthermore, it is also possible to apply the present invention to the manufacture of C-MOS in which N and P exist at the same time. Further, as the third coating, Poly-
Although the explanation was made using Si, any material that increases the volume through the oxidation process, becomes an insulator, and has good coverage may be used instead. Furthermore, the third film may be an insulating film from the beginning.
また、第３の被膜としてのPoly−Siに不純物
をイオン打ち込みすれば、酸化時間が短くなり、
空洞の埋め込みが容易となる。さらに、Poly−
Siは必ずしも全部酸化する必要はない。その他、
本発明の要旨を逸脱しない範囲で、種々変形して
実施することができる。 In addition, if impurities are ion-implanted into Poly-Si as the third film, the oxidation time will be shortened.
Filling the cavity becomes easier. Furthermore, Poly−
Si does not necessarily need to be completely oxidized. others,
Various modifications can be made without departing from the spirit of the invention.
第１図ａ〜ｅは従来のBOX法による半導体装
置の製造工程を示す断面図、第２図ａ，ｂは上記
従来方法の問題点を説明するための模式図、第３
図ａ〜ｇは本発明の一実施例に係わる半導体装置
の製造工程を示す断面図である。
１１……シリコン基板、１２……酸化膜、１３
……マスク材（第１の被膜）、１４……フイール
ドイオン注入層、１５……溝、１６……Plasma
CVD SiO2膜（第２の被膜）、１７……CVD
SiO2膜（第３の被膜）、１８……Poli−Si膜（第
４の被膜）、１９……凹部、２０……SiO2膜、２
１……平坦化膜。
Figures 1 a to e are cross-sectional views showing the manufacturing process of a semiconductor device using the conventional BOX method, Figures 2 a and b are schematic diagrams for explaining the problems of the conventional method, and Figure 3
Figures a to g are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 11...Silicon substrate, 12...Oxide film, 13
...Mask material (first coating), 14...Field ion implantation layer, 15...Groove, 16...Plasma
CVD SiO 2 film (second film), 17...CVD
SiO 2 film (third coating), 18...Poli-Si film (fourth coating), 19... recess, 20... SiO 2 film, 2
1... Flattening film.
Claims (1)
成する工程と、上記第１の被膜をマスクとして上
記半導体基板を選択エツチングし該基板のフイー
ルド領域に凹部を形成する工程と、上記凹部に絶
縁性の第２の被膜を埋め込む工程と、上記第２の
被膜および半導体基板上に絶縁性の第３の被膜を
被着する工程と、上記第３の被膜上に酸化工程に
より絶縁膜となる第４の被膜を被着する工程と、
上記第４の被膜の少なくとも一部を酸化する工程
と、次いで上記第４の被膜上を平坦化する工程
と、しかるのち上記第４の被膜から前記半導体基
板に至る深さまで全面エツチングし上記半導体基
板の素子形成領域を露出せしめる工程とを具備し
たことを特徴とする半導体装置の製造方法。 ２ 前記フイールド領域に凹部を形成するに際
し、予め前記第１の被膜をマスクとして前記半導
体基板に該基板と同導電型の不純物をイオン打ち
込みすることを特徴とする特許請求の範囲第１項
記載半導体装置の製造方法。 ３ 前記凹部に絶縁性の第２の被膜を埋め込むに
際し、予め上記凹部の底部に前記半導体基板と同
導電型の不純物をイオン打ち込みすることを特徴
とする特許請求の範囲第１項記載の半導体装置の
製造方法。[Scope of Claims] 1. A step of forming a first film in an element formation region of a semiconductor substrate, and a step of selectively etching the semiconductor substrate using the first film as a mask to form a recess in a field region of the substrate. a step of embedding a second insulating film in the recess; a step of depositing a third insulating film on the second film and the semiconductor substrate; and an oxidation step on the third film. a step of depositing a fourth film that becomes an insulating film;
A step of oxidizing at least a portion of the fourth film, a step of planarizing the top of the fourth film, and then etching the entire surface from the fourth film to a depth of the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising: exposing an element formation region. 2. The semiconductor according to claim 1, wherein when forming the recess in the field region, impurities of the same conductivity type as the semiconductor substrate are ion-implanted into the semiconductor substrate in advance using the first film as a mask. Method of manufacturing the device. 3. The semiconductor device according to claim 1, wherein when embedding the second insulating film in the recess, ions of an impurity having the same conductivity type as that of the semiconductor substrate are implanted into the bottom of the recess in advance. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252182A JPS58139443A (en) | 1982-02-15 | 1982-02-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252182A JPS58139443A (en) | 1982-02-15 | 1982-02-15 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58139443A JPS58139443A (en) | 1983-08-18 |
| JPH0445980B2 true JPH0445980B2 (en) | 1992-07-28 |
Family
ID=12085074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2252182A Granted JPS58139443A (en) | 1982-02-15 | 1982-02-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58139443A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE202016003402U1 (en) | 2016-05-28 | 2017-08-30 | Neoperl Gmbh | Sanitary insert unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
-
1982
- 1982-02-15 JP JP2252182A patent/JPS58139443A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58139443A (en) | 1983-08-18 |
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