JPH0445244Y2 - - Google Patents
Info
- Publication number
- JPH0445244Y2 JPH0445244Y2 JP1985147747U JP14774785U JPH0445244Y2 JP H0445244 Y2 JPH0445244 Y2 JP H0445244Y2 JP 1985147747 U JP1985147747 U JP 1985147747U JP 14774785 U JP14774785 U JP 14774785U JP H0445244 Y2 JPH0445244 Y2 JP H0445244Y2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- electrode terminal
- semiconductor chip
- substrate
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000853 adhesive Substances 0.000 claims description 30
- 230000001070 adhesive effect Effects 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 239000002245 particle Substances 0.000 claims description 12
- 230000005496 eutectics Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、基板上に駆動用大規模集積回路チツ
プ（以下LSIチツプと記す。）等を実装した半導
体チツプの接続構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a connection structure for a semiconductor chip in which a driving large-scale integrated circuit chip (hereinafter referred to as an LSI chip) is mounted on a substrate.
基板上に、前記LSIチツプを実装する電気光学
装置における従来の実装方式を第２図へ示す。第
２図ａは、ワイヤーボンデイング、同図ｂは、半
田によるフエイスダウンボンデイング、同図ｃ
は、共晶結合によるボンデイングである。
FIG. 2 shows a conventional mounting method for an electro-optical device in which the LSI chip is mounted on a substrate. Figure 2a shows wire bonding, Figure 2b shows face-down bonding using solder, Figure 2c shows
is bonding by eutectic bonding.
従来、各実装方式においても電極端子２とLSI
チツプ３、との物理的固定及び、電気的接続に共
晶結合、金属間化合物による結合等の金属間の化
学反応を利用している。このため実装後にLSIチ
ツプの不良が発見された場合、LSIチツプを除去
するのが困難であり、万が一除去に成功しても、
電極端子２が破壊されることが多く、新しくLSI
チツプを実装するのは困難であるという欠点があ
つた。例外として第２図ａの接合部４を導電性接
着剤を用いてダイアタツチを行うこともあるが、
使用する接着剤は、ワイヤーボンデイングの高温
に耐えうるほど堅牢にできており金属間の化学反
応の場合と同様に、LSIチツプの除去を困難にす
るという点では同様である。 Conventionally, in each mounting method, electrode terminal 2 and LSI
For physical fixation and electrical connection with the chip 3, chemical reactions between metals such as eutectic bonding and bonding by intermetallic compounds are used. For this reason, if a defective LSI chip is discovered after implementation, it is difficult to remove the LSI chip, and even if removal is successful,
Electrode terminal 2 is often destroyed, and new LSI
The drawback was that it was difficult to implement the chip. As an exception, the joint 4 in Fig. 2a may be die-attached using a conductive adhesive.
The adhesive used is tough enough to withstand the high temperatures of wire bonding, making it difficult to remove the LSI chip, similar to the chemical reaction between metals.
また第２図ｃの金属線６と電極端子２、の間で
共晶結合を行うとき、金属線６の上部へボンデイ
ングツールにより高温高圧を付加する。このとき
ボンデイングツールにわずかな傾きがあると、共
晶生成にむらが生じ、信頼性の低い実装となる欠
点があつた。 Further, when performing eutectic bonding between the metal wire 6 and the electrode terminal 2 in FIG. 2c, high temperature and high pressure are applied to the upper part of the metal wire 6 using a bonding tool. At this time, if the bonding tool was slightly tilted, eutectic formation would be uneven, resulting in unreliable mounting.
さらに従来の技術では、いずれも120℃〜500℃
の高温が不可欠であり表示パネル１の材質が耐熱
性が低い場合、実装が困難であるという欠点があ
つた。 Furthermore, with conventional technology, the temperature range is 120℃ to 500℃.
A high temperature is essential, and if the material of the display panel 1 has low heat resistance, there is a drawback that mounting is difficult.
そこで本考案はこのような問題点を解決するも
ので、その目的とするところは、電極端子２、及
び基板１への損傷無しに実装された半導体チツプ
を取りはずすことを可能にし、ボンデイングツー
ルに傾きが生じても安定した実装が行え、高温を
必要としない半導体チツプの実装を可能にするこ
とにある。
The present invention is intended to solve these problems, and its purpose is to make it possible to remove the mounted semiconductor chip without damaging the electrode terminals 2 and the substrate 1, and to avoid tilting the bonding tool. The object of the present invention is to enable stable mounting even when heat is generated, and to enable semiconductor chip mounting that does not require high temperatures.
〔問題点を解決するための手段〕
本考案の半導体チツプの接続構造は、少なくと
も一方の面上に複数の電極端子が形成された基板
と、該電極端子に対応した複数の金属線の一方の
端が接続固定された半導体チツプとを有し、前記
電極端子と前記金属線の他方の端が、導電粒子と
混合された接着剤または異方性導電膜を介して電
気的接続されてなり、さらに前記金属線の他方の
端と前記電極端子との接続部を覆うように弾性を
有する基板が配設されたことを特徴とする。[Means for Solving the Problems] The semiconductor chip connection structure of the present invention includes a substrate having a plurality of electrode terminals formed on at least one surface, and one of the plurality of metal wires corresponding to the electrode terminals. a semiconductor chip whose end is connected and fixed, and the electrode terminal and the other end of the metal wire are electrically connected via an adhesive mixed with conductive particles or an anisotropic conductive film, Furthermore, an elastic substrate is disposed so as to cover a connecting portion between the other end of the metal wire and the electrode terminal.
本考案の作用を図面に基づき詳細に説明する。
第１図に本考案の基本構造を示す。同図ａが上面
図、同図ｂが側面断面図である。第１図ｂに示す
ようにLSIチツフ３にあらかばめ金属線６を接続
しておく。次に金属線６もしくは基板１上に形成
した電極端子２へ導電性粒子５及び接着剤４を塗
布する。
The operation of the present invention will be explained in detail based on the drawings.
Figure 1 shows the basic structure of the present invention. Figure a is a top view, and figure b is a side sectional view. As shown in FIG. 1b, a loosely fitted metal wire 6 is connected to the LSI chip 3. Next, conductive particles 5 and adhesive 4 are applied to metal wire 6 or electrode terminal 2 formed on substrate 1 .
導電性粒子５は、金属線幅および、電極端子幅
に対し十分に小さく、接着剤３中で４分に分散さ
せ、異方性の導通性を持たせる。また、導電性粒
子５と接着剤４は、別々に塗布しても良いし、混
合しているものを塗布しても良い。 The conductive particles 5 are sufficiently small with respect to the metal line width and the electrode terminal width, and are dispersed in four parts in the adhesive 3 to provide anisotropic conductivity. Moreover, the conductive particles 5 and the adhesive 4 may be applied separately or may be applied as a mixture.
次に金属線６の接着面の反対側に弾力性を有す
る板７を取りつけ、上部より圧力を加えることに
より導電性粒子を介し電極端子と金属線の電気的
接続を計る。また同時に、接着剤の硬化条件を満
たすことにより物理的固定を計り、加圧後にも電
気的接続が持続されるようにする。 Next, an elastic plate 7 is attached to the opposite side of the adhesive surface of the metal wire 6, and pressure is applied from above to establish an electrical connection between the electrode terminal and the metal wire via the conductive particles. At the same time, physical fixation is ensured by satisfying the conditions for curing the adhesive, and electrical connection is maintained even after pressure is applied.
本考案の構造とすれば、LSIチツフ３と電極端
子２との物理的固定に使用される接着剤４の成分
を任意に選択することができる。つまり接着剤４
に溶剤溶解性を有する接着剤を使用した場合、不
良LSIチツプ３の取り外しが容易に行なえ、か
つ、電極端子２の破壊を生じないため取り外し後
に容易に新しいLSIチツプ３を取り付けることが
できる。また低温硬化が可能な接着剤を用いるこ
とにより、基板１に熱衝撃を与えることなく、物
理的固定を行うことができる。 With the structure of the present invention, the components of the adhesive 4 used for physically fixing the LSI chip 3 and the electrode terminal 2 can be arbitrarily selected. In other words, adhesive 4
When a solvent-soluble adhesive is used, the defective LSI chip 3 can be easily removed, and since the electrode terminals 2 are not destroyed, a new LSI chip 3 can be easily attached after removal. Furthermore, by using an adhesive that can be cured at low temperatures, physical fixation can be performed without applying thermal shock to the substrate 1.
その他、使用する接着剤の性質により、様々な
特徴を持たせることができるようになるのは言う
までもない。 Needless to say, various other characteristics can be imparted depending on the properties of the adhesive used.
また弾力性を有する板７の上面より加圧するこ
とによりボンデイングツールの傾きを吸収し、
LSIチツプ３と電極端子２との安定な導通を実現
し、信頼性の高い接続を行うことができるように
する。 In addition, by applying pressure from the top surface of the elastic plate 7, the tilt of the bonding tool is absorbed.
To realize stable conduction between an LSI chip 3 and an electrode terminal 2, and to perform a highly reliable connection.
実施例 １
液晶表示体へ本考案を実施した例を示す。第１
図において、基板１にガラス基板、電極端子２に
Niメツキを施したITOを使用し、弾力性のある
板７に200μmのポリイミド膜を使用した。さら
に、導電性粒子５に、直径5μmのNiメツキを施
した樹脂ボールを用い、接着剤４に溶剤溶解性の
熱硬化性接着剤を使用した。Example 1 An example in which the present invention is applied to a liquid crystal display is shown. 1st
In the figure, substrate 1 is a glass substrate, electrode terminal 2 is
ITO plated with Ni was used, and a 200 μm polyimide film was used for the elastic plate 7. Furthermore, Ni-plated resin balls with a diameter of 5 μm were used as the conductive particles 5, and a solvent-soluble thermosetting adhesive was used as the adhesive 4.
接着剤と導電性の粒子の混合物をスクリーン印
刷で必要な場所へ印刷することにより作業能率を
高めることができ、熱硬化性の接着剤を使用する
ことにより短時間で、駆動用LSIを取り付けるこ
とができた。またポリイミド膜の上より加圧する
ことにより、加圧むらを無くし、良好な接続が実
現できた。さらに溶剤融解性の接着剤を使用する
ことにより、不良LSIチツプの取りはずしもスム
ースに行なえ、取りはずした後の電極端子の破壊
も皆無であつた。 Work efficiency can be increased by printing a mixture of adhesive and conductive particles onto the required locations using screen printing, and the use of thermosetting adhesive allows the drive LSI to be attached in a short time. was completed. In addition, by applying pressure from above the polyimide film, uneven pressure was eliminated and a good connection was achieved. Furthermore, by using a solvent-meltable adhesive, the defective LSI chip could be removed smoothly, and there was no damage to the electrode terminals after removal.
実施例 ２
実施例１の樹脂ボールと熱硬化性接着剤の代り
に異方性導電膜を使用した。この場合の異方性導
電膜は実施例１で使用した接着剤の粘性を高めシ
ート状にした物と考えることが出来る。あらかじ
め、金属線もしくは、電極端子に異方性導電膜を
取り付けておくことにより、作業効率を高めるこ
とができた。その他の効果は実施例１と同様であ
る。Example 2 An anisotropic conductive film was used in place of the resin balls and thermosetting adhesive of Example 1. The anisotropic conductive film in this case can be considered to be the adhesive used in Example 1 with increased viscosity and made into a sheet. By attaching an anisotropic conductive film to the metal wire or electrode terminal in advance, work efficiency could be improved. Other effects are similar to those in the first embodiment.
実施例 ３
基板を透明樹脂で形成し電極端子をITOのみと
し、接着剤を紫外線硬化性のものにする以外は実
施例１と同様の条件で行つた。この場合ポリイミ
ド膜上から加圧した状態で、表示パネル下部より
紫外線を照射して接着剤を硬化させることにより
加熱することなく駆動用LSIと電極端子を物理的
に固定することができた。Example 3 A test was carried out under the same conditions as in Example 1, except that the substrate was made of transparent resin, the electrode terminals were made only of ITO, and the adhesive was UV-curable. In this case, by applying pressure from above the polyimide film and curing the adhesive by irradiating ultraviolet rays from the bottom of the display panel, we were able to physically fix the driving LSI and electrode terminals without heating.
なお、本考案はLSIチツプのみならずMSIチツ
プ，SSIチツプ等にも応用できることは言うまで
もない。 It goes without saying that the present invention can be applied not only to LSI chips but also to MSI chips, SSI chips, etc.
実施例１−３について導電性の粒子は、電気抵
抗さえ十分に小さければ、カーボン、半田、等の
粒子を使用してもかまわない。 Regarding Examples 1-3, particles of carbon, solder, etc. may be used as the conductive particles as long as the electrical resistance is sufficiently small.
〔考案の効果〕
上述の如く本考案によれば、半導体チツプに配
設された金属線の一方の端と電極端子とを導電粒
子と混合された接着剤または異方性導電膜を介し
て電気的接続したので、半導体チツプの除去が容
易となつた。特に接着剤による接着固定が金属線
の一方の端と電極端子の部分で行われるので、半
導体チツプの取り外しがスムースとなる。すなわ
ち、仮に半導体チツプのバンプ等の端子部と基板
の電極端子とを接着剤等で接着した場合、接着剤
が半導体チツプの端子部以外に広がつてしまい、
場合によつては全面が接着面となる。したがつ
て、非常に強い接着力となり、半導体チツプの取
り外しが非常に困難になる。ともすれば、半導体
チツプを損傷してしまう。しかしながら、本考案
によれば接着面積が電気的接続に必要な部分のみ
でよいので、確実な電気的接続をとりながら半導
体チツプの取り外しが容易となる。[Effects of the invention] As described above, according to the invention, one end of a metal wire disposed on a semiconductor chip and an electrode terminal are connected to each other through an adhesive mixed with conductive particles or an anisotropic conductive film. Since the semiconductor chip is directly connected, the semiconductor chip can be easily removed. In particular, since adhesive fixation is performed at one end of the metal wire and the electrode terminal, the semiconductor chip can be removed smoothly. In other words, if a terminal such as a bump on a semiconductor chip and an electrode terminal on a substrate are bonded with an adhesive, the adhesive will spread to areas other than the terminal of the semiconductor chip.
In some cases, the entire surface becomes the adhesive surface. Therefore, the adhesive force is very strong, making it very difficult to remove the semiconductor chip. Otherwise, the semiconductor chip will be damaged. However, according to the present invention, since the bonding area is limited to only the area necessary for electrical connection, the semiconductor chip can be easily removed while maintaining reliable electrical connection.
さらに、接続部を覆うように弾性を有する基板
が配設されたので、この基板の上面より加圧を行
うことにより加圧むらを無くし、各接続部におい
て均一な電気的接続が得られる。 Further, since an elastic substrate is disposed to cover the connection portions, pressure is applied from the upper surface of the substrate to eliminate uneven pressure, and uniform electrical connection can be obtained at each connection portion.
第１図は本考案の電気光学装置の基本構成で、
ａは上面図、ｂは側面断面図である。第２図ａ，
ｂ，ｃは従来技術の説明図である。
１……基板、２……電極端子、３……LSIチツ
プ、４……接着剤、５……導電性粒子、６……金
属線、７……弾力性を有する板、８……ワイヤ
ー、９……半田。
Figure 1 shows the basic configuration of the electro-optical device of the present invention.
A is a top view, and b is a side sectional view. Figure 2a,
b and c are explanatory diagrams of the prior art. DESCRIPTION OF SYMBOLS 1... Board, 2... Electrode terminal, 3... LSI chip, 4... Adhesive, 5... Conductive particles, 6... Metal wire, 7... Elastic plate, 8... Wire, 9...Solder.
Claims (1)
された基板と、該電極端子に対応した複数の金属
線の二方の端が接続固定された半導体チツプとを
有し、前記電極端子と前記金属線の他方の端が、
導電粒子と混合された接着剤または異方性導電膜
を介して電気的接続されてなり、さらに前記金属
線の他方の端と前記電極端子との接続部を覆うよ
うに弾性を有する基板が配設されたことを特徴と
する半導体チツプの接続構造。 It has a substrate on which a plurality of electrode terminals are formed on at least one surface, and a semiconductor chip to which two ends of a plurality of metal wires corresponding to the electrode terminals are connected and fixed, and the electrode terminal and the metal wire are connected to each other. The other end of the line is
The electrical connection is made through an adhesive mixed with conductive particles or an anisotropic conductive film, and an elastic substrate is arranged to cover the connection between the other end of the metal wire and the electrode terminal. A connection structure for a semiconductor chip, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985147747U JPH0445244Y2 (en) | 1985-09-27 | 1985-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985147747U JPH0445244Y2 (en) | 1985-09-27 | 1985-09-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6255348U JPS6255348U (en) | 1987-04-06 |
| JPH0445244Y2 true JPH0445244Y2 (en) | 1992-10-23 |
Family
ID=31061393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985147747U Expired JPH0445244Y2 (en) | 1985-09-27 | 1985-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445244Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2705658B2 (en) * | 1994-08-31 | 1998-01-28 | 日本電気株式会社 | Electronic device assembly and method of manufacturing the same |
| WO1998046811A1 (en) * | 1997-04-17 | 1998-10-22 | Sekisui Chemical Co., Ltd. | Conductive particles and method and device for manufacturing the same, anisotropic conductive adhesive and conductive connection structure, and electronic circuit components and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120941A (en) * | 1974-08-14 | 1976-02-19 | Seikosha Kk | DODENSEISETSUCHAKUZAI |
| JPS5431566A (en) * | 1977-08-12 | 1979-03-08 | Nippon Kokuen Kogyo Kk | Way of connecting large scale integrated circuit to current carrying circuit portions on insulated substrate |
-
1985
- 1985-09-27 JP JP1985147747U patent/JPH0445244Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120941A (en) * | 1974-08-14 | 1976-02-19 | Seikosha Kk | DODENSEISETSUCHAKUZAI |
| JPS5431566A (en) * | 1977-08-12 | 1979-03-08 | Nippon Kokuen Kogyo Kk | Way of connecting large scale integrated circuit to current carrying circuit portions on insulated substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6255348U (en) | 1987-04-06 |
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