JPH0443712A - Semiconductor output circuit - Google Patents
Semiconductor output circuitInfo
- Publication number
- JPH0443712A JPH0443712A JP2151053A JP15105390A JPH0443712A JP H0443712 A JPH0443712 A JP H0443712A JP 2151053 A JP2151053 A JP 2151053A JP 15105390 A JP15105390 A JP 15105390A JP H0443712 A JPH0443712 A JP H0443712A
- Authority
- JP
- Japan
- Prior art keywords
- output
- channel
- ecl
- circuit
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 230000000295 complement effect Effects 0.000 claims abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＥ ＣＬ （Ｅｍｉｔｔｅｒ Ｃｏｕｐｌｅｄ
Ｌｏｇｉｃ）論理レベルの信号出力を行う半導体出力
回路に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is an ECL (Emitter Coupled
(Logic) This relates to a semiconductor output circuit that outputs a signal at a logic level.
近年の半導体回路においては、１つのチップ上にバイポ
ーラ素子とＣＭＯ５素子を混在させて、それぞれの特徴
を合わせもつＢ ｉ −ＣＭＯＳ回路が多用されるよう
になってきた。In recent years, in semiconductor circuits, B i -CMOS circuits in which bipolar elements and CMO5 elements are mixed on one chip and have the characteristics of each have come to be frequently used.
このようなり １−ＣＭＯＳ回路においては、高速動作
可能なＥ ＣＬ （Ｅｍｉｔｔｅｒ Ｃｏｕｐｌｅｄ
Ｌｏｇｉｃ）回路と、低消費電力のＣＭＯＳ回路を組み
合わせることによって、高速かつ低消費電力の論理回路
を実現することができる。このような、Ｂ１ＣＭＯＳ素
子によるＬＳＩのうち高速なものは、ボード上でのＬ
Ｓ Ｉ ｆの高速信号伝般をおこなうために、入出力イ
ンターフェースにＥＣＬレベル（ハイレベルは、Ｖｃｃ
（電源電圧）−０，８Ｖ程度、ロウレベルは、Ｖｃｃｌ
、６Ｖ程度）を用いるものが多い、一方、チップの内部
回路は、消費電流を抑えるために、ＣＭＯＳレベル（ハ
イレベルは、Ｖｃｃ（電源電圧）程度、ロウレベルは、
Ｖ ｅｅ程度）で動作するものが多い、よって、このよ
うなチップの入出力インターフェース部には、入力部で
ＥＣＬ−ＣＭＯＳ、出力部ではＣＭＯＳ−ＥＣＬの論理
レベル変換が必要となる。1-In a CMOS circuit, ECL (Emitter Coupled
A high-speed, low-power consumption logic circuit can be realized by combining a low-power consumption CMOS circuit with a low-power consumption CMOS circuit. Among these LSIs based on B1CMOS elements, high-speed ones have LSIs on the board.
In order to perform high-speed signal transmission of S If, the ECL level (high level is Vcc) is applied to the input/output interface.
(Power supply voltage) -0.8V or so, low level is Vccl
On the other hand, in order to suppress current consumption, the internal circuit of the chip uses CMOS level (high level is about Vcc (power supply voltage), low level is about Vcc (power supply voltage)).
Therefore, the input/output interface section of such a chip requires ECL-CMOS logic level conversion at the input section and CMOS-ECL logic level conversion at the output section.
ＥＣＬレベルによる入出力インターフェース部には、生
駒、市瀬著、近代科学社刊の“バイポーラ集積回路”１
００頁に示されるような従来型の電流切り替え型論理回
路が用いられている。それを利用した、ＥＣＬの出力バ
ッファ回路の従来例を第５図に示す。同図の回路は、Ｃ
ＭＯＳレベルの信号ＩＮに対して、ＣＭＯＳ−ＥＣＬの
レベル変換を行い、電流切り替え型論理回路によって、
出力バイポーラトランジスタ１を駆動する。The input/output interface section at the ECL level uses "Bipolar Integrated Circuit" 1 written by Ikoma and Ichise and published by Kindai Kagakusha.
A conventional current switching type logic circuit as shown on page 00 is used. A conventional example of an ECL output buffer circuit utilizing this is shown in FIG. The circuit in the same figure is C
CMOS-ECL level conversion is performed for the MOS level signal IN, and a current switching type logic circuit is used to
Drives the output bipolar transistor 1.
第５図に示す従来回路においては、ＣＭＯＳ−ＥＣＬの
レベル変換部および、ＥＬＣ出カバ・ンファ回路部で７
．８．９のような定を流源が必要であり、ＤＣ電流が消
費される。よって、近年の高性能マイクロプロセッサ等
、出力ピンを多くもつ半導体チップでは、第５図にしめ
す回路を用いると、ビン数に比例して、消費電流が増大
してしまい、出力が１００ピン程度では、出力バッファ
部だけで、２〜３Ｗの電流が必要である。In the conventional circuit shown in FIG. 5, the CMOS-ECL level conversion section and the ELC output buffer circuit section
．． A constant current source such as 8.9 is required and DC current is consumed. Therefore, for semiconductor chips with many output pins, such as recent high-performance microprocessors, if the circuit shown in Figure 5 is used, the current consumption will increase in proportion to the number of bins, and if the output is around 100 pins, the current consumption will increase. , the output buffer section alone requires a current of 2 to 3 W.
本発明の目的は、低消費電力化を図ったＥＣＬ論理レベ
ルの信号出力を行う半導体出力回路を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor output circuit that outputs ECL logic level signals with reduced power consumption.
本発明の半導体出力回路は、ＥＣＬ論理比カバッファ回
路において、１つの半導体チップ上にＥＣＬ論理レベル
の信号出力を行う出力バイポーラトランジスタと、前記
出力バイポーラトランジスタのベースに縦列接続の中点
が接続された２つのｐチャネルＭＩＳＦＥＴとを設け、
前記２つのｐチャネルＭＩＳＦＥＴのそれぞれのゲート
に相補なゲート信号を入力し前記出力バイポーラトラン
ジスタを制御する構成である。The semiconductor output circuit of the present invention is an ECL logic ratio buffer circuit, and includes an output bipolar transistor that outputs a signal at an ECL logic level on one semiconductor chip, and a midpoint of the cascade connection connected to the base of the output bipolar transistor. Two p-channel MISFETs are provided,
The configuration is such that complementary gate signals are input to the gates of each of the two p-channel MISFETs to control the output bipolar transistor.
また、上記構成において前記２つのｐチャネルＭＩＳＦ
ＥＴのそれぞれのゲートに前記相補なゲート信号のタイ
ミングを制御する手段を設け、前記２つのｐチャネルＭ
ＩＳＦＥＴが同時にはオンしないように制御する構成と
することができる。Further, in the above configuration, the two p-channel MISFs
Means for controlling the timing of the complementary gate signals is provided at each gate of the ET, and the two p-channel M
A configuration may be adopted in which control is performed so that the ISFETs are not turned on at the same time.
本発明では、ＣＭＯＳ等のＭＩＳＦＥＴにより、バイポ
ーラ素子を制御する構成で、ＤＳ消費電流は必要でない
、また、基準電圧源により、ＥＣＬ規格を満たす出力レ
ベルを確保可能である。また、回路が主にＭＩＳＦＥＴ
素子により構成されるために、従来のバイポーラ素子と
、抵抗で構成した回路よりも使用面積が小さくて済む。In the present invention, a bipolar element is controlled by a MISFET such as a CMOS, so that DS current consumption is not necessary, and the reference voltage source can ensure an output level that satisfies the ECL standard. Also, the circuit is mainly MISFET
Since it is composed of elements, it uses a smaller area than a conventional circuit composed of bipolar elements and resistors.
これにより、ＥＣＬの多ビン出力チップにおいては、出
力バッファ部のＤＣ消費電力を削減でき、また、比カバ
ッファの占有面積を小さくすることが可能となる。As a result, in the ECL multi-bin output chip, the DC power consumption of the output buffer section can be reduced, and the area occupied by the ratio buffer can be reduced.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す回路図である６本実施
例の半導体出力回路は、ＥＣＬレベルの信号出力を行う
出力バイポーラトランジスタ１と、そのベース電位を制
御する縦列接続された２つのｐチャネルＭＩＳＦＥＴ２
．３と、ｐチャネルＭＩＳＦＥＴ２のゲートに入力され
るＣＭＯＳレベルの入力信号から相補な信号を作成しｐ
チャネルＭＩＳＦＥＴ３のゲートに入力するインバータ
４とが同一半導体チップ上に設けられている。FIG. 1 is a circuit diagram showing an embodiment of the present invention.6 The semiconductor output circuit of this embodiment includes an output bipolar transistor 1 that outputs a signal at the ECL level, and a series-connected transistor 2 that controls the base potential of the output bipolar transistor 1. 2 p-channel MISFETs
．． 3 and the CMOS level input signal input to the gate of p channel MISFET2.
An inverter 4 input to the gate of channel MISFET 3 is provided on the same semiconductor chip.
出力端子１０につながる抵抗器５（５０Ω）はＥＣＬの
終端抵抗で、−２ｖの終端基準電圧源に接続される。電
源端子１１．１２からはそれぞれ、高位１１ｊｌｌ電源
電圧（Ｖｃｃ）、低位側電源電圧（ＶＥＥ）が供給され
る。出力端子１０と電源端子１２間に負荷コンデンサ６
が接続される。また、ｐチャネルＭＩＳＦＥＴ３のトレ
イン端子は、基準電圧端子１４に接続され■。０がらＥ
ＣＬの出力振幅分だけ小さい基準電圧（Ｖ、ｅｒ）が印
加される。A resistor 5 (50Ω) connected to the output terminal 10 is a termination resistance of ECL, and is connected to a −2V termination reference voltage source. A high power supply voltage (Vcc) and a low power supply voltage (VEE) are supplied from power supply terminals 11 and 12, respectively. A load capacitor 6 is connected between the output terminal 10 and the power supply terminal 12.
is connected. Further, the train terminal of the p-channel MISFET 3 is connected to the reference voltage terminal 14. 0garaE
A reference voltage (V, er) smaller by the output amplitude of CL is applied.
次に、動作を説明する。Next, the operation will be explained.
入力端子１３からの入力信号ＩＮがハイレベルのとき、
ｐチャネルＭＩＳＦＥＴ２はオフ、ｐチャネルＭ Ｉ
５ＦＥＴ３はオンで、出力バイポーラトランジスタ１の
ベース電位はＶ ｒ ｅ ｆとなり、出力端子１０はＥ
ＣＬのローレベルの出力信号ＯＵＴを出力する。一方、
入力信号ＩＮがローレベルのときは、ｐチャネルＭＩＳ
ＦＥＴ２がオン、ｐチャネルＭＩＳＦＥＴ３がオフで、
出力バイポーラトランジスタ１のベース電位はＶｃｃ（
ＯＶ）となり、出力端子１０の出力信号ＯＵＴはＥＣＬ
のハイレベルとなる。この回路の動作波形を第２図に示
す。When the input signal IN from the input terminal 13 is at high level,
p-channel MISFET2 is off, p-channel MISFET2
5FET3 is on, the base potential of the output bipolar transistor 1 becomes V r e f, and the output terminal 10 becomes E
A low level output signal OUT of CL is output. on the other hand,
When the input signal IN is low level, the p-channel MIS
FET2 is on, p-channel MISFET3 is off,
The base potential of the output bipolar transistor 1 is Vcc (
OV), and the output signal OUT of output terminal 10 is ECL.
becomes a high level. The operating waveforms of this circuit are shown in FIG.
なおこのとき、ｐチャネルＭＩＳＦＥＴ２．３は相補な
動作を行うために、ＤＣ電流を消費しない。また、出力
バイポーラトランジスタｌ以外はＭＩＳＦＥＴ素子を用
いているために、従来のバイポーラ素子と、抵抗を用い
た回路構成よりも素子の占有面積が小さくできる。Note that at this time, p-channel MISFET 2.3 performs complementary operations and therefore does not consume DC current. Furthermore, since MISFET elements are used except for the output bipolar transistor l, the area occupied by the elements can be smaller than in a conventional circuit configuration using bipolar elements and resistors.
第３図は本発明の他の実施例で、請求項２に記載の半導
体出力回路を示す、ｐチャネルＭＩＳ１−ＥＴ２．３の
それぞれのゲート端子２１．３１に、２人力ＮＡＮＤ４
０と直列に偶数個接続され信号遅延を行うインバータ４
１とからなるタイミング制御回路２２．３２がそれぞれ
接続されている。FIG. 3 shows another embodiment of the present invention, showing a semiconductor output circuit according to claim 2, in which two NAND4
0 and an even number of inverters 4 connected in series to delay the signal.
Timing control circuits 22 and 32 consisting of 1 and 1 are connected to each other.
第３図の回路では、入力信号ＩＮに対して、ゲート端子
２１．３１にはそれぞれ第４図に示すような、信号Ａ、
Ｂが発生される。このＡ、Ｂの信号によりｐチャネルＭ
ＩＳＦＥＴ２．３が制御されるために、ＰチャネルＭＩ
ＳＦＥＴ２．３が同時にオンすることはなく、ｐチャネ
ルＭＩＳＦＥＴ２．３をとうして流れる貫通電流かない
ために、低消費電力化か図れる。In the circuit shown in FIG. 3, in response to the input signal IN, the gate terminals 21 and 31 receive signals A and 31, respectively, as shown in FIG.
B is generated. With these A and B signals, p channel M
In order for ISFET2.3 to be controlled, the P-channel MI
Since the SFETs 2.3 are not turned on at the same time and no through current flows through the p-channel MISFET 2.3, power consumption can be reduced.
本発明の半導体集積回路は、出力バイポーラトランジス
タをｐチャネルＭＩＳＦＥＴで制御することにより、Ｅ
ＣＬ出力バッファ回路の低消費電力化をはかることがで
きる。The semiconductor integrated circuit of the present invention controls the output bipolar transistor with a p-channel MISFET, so that the E
The power consumption of the CL output buffer circuit can be reduced.
第１図は本発明の一実施例を示す回路図、第２図は第１
図の回路の動作の概要を説明するタイミング図、第３図
は本発明の他の実施例を示す回路図、第４図は第３図の
回路の動作の概要を説明するタイミング図、第５図は従
来のＥＣＬ出力バッファ回路を示す回路図である。
１・・・出力バイポーラトランジスタ、２，３・・・ｐ
チャ！ネルＭＩＳＦＥＴ、４・・・インバータ、５・・
抵抗器、６・・負荷コンデンサ、７〜９・・・定を流源
、１０・・・出力端子、１１．１２・・・電源端子、１
３・・・入力端子、１４・・・基準電圧端子、２１３１
・・・タイミング制御回路、４０・・・２人力ＮＡＮＤ
、４１・・インバータ。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram illustrating another embodiment of the present invention; FIG. 4 is a timing diagram illustrating an outline of the operation of the circuit in FIG. 3; The figure is a circuit diagram showing a conventional ECL output buffer circuit. 1... Output bipolar transistor, 2, 3...p
Cha! Channel MISFET, 4... Inverter, 5...
Resistor, 6...Load capacitor, 7-9... Constant current source, 10... Output terminal, 11.12... Power supply terminal, 1
3...Input terminal, 14...Reference voltage terminal, 2131
...Timing control circuit, 40...2 manual NAND
, 41... Inverter.
Claims (1)
体チップ上にＥＣＬ論理レベルの信号出力を行う出力バ
イポーラトランジスタと、前記出力バイポーラトランジ
スタのベースに縦列接続の中点が接続された２つのｐチ
ャネルＭＩＳＦＥＴとを設け、前記２つのｐチャネルＭ
ＩＳＦＥＴのそれぞれのゲートに相補なゲート信号を入
力し前記出力バイポーラトランジスタを制御することを
特徴とする半導体出力回路。 ２、前記２つのｐチャネルＭＩＳＦＥＴのそれぞれのゲ
ートに前記相補なゲート信号のタイミングを制御する手
段を設け、前記２つのｐチャネルＭＩＳＦＥＴが同時に
はオンしないように制御することを特徴とする請求項１
記載の半導体出力回路。[Claims] 1. In an ECL logic output buffer circuit, an output bipolar transistor that outputs a signal at an ECL logic level is provided on one semiconductor chip, and a midpoint of the cascade connection is connected to the base of the output bipolar transistor. two p-channel MISFETs are provided, and the two p-channel MISFETs are provided.
A semiconductor output circuit characterized in that complementary gate signals are input to each gate of an ISFET to control the output bipolar transistor. 2. Means for controlling the timing of the complementary gate signals is provided at each gate of the two p-channel MISFETs, and control is performed so that the two p-channel MISFETs are not turned on at the same time.
The semiconductor output circuit described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151053A JP2855796B2 (en) | 1990-06-08 | 1990-06-08 | Semiconductor output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151053A JP2855796B2 (en) | 1990-06-08 | 1990-06-08 | Semiconductor output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0443712A true JPH0443712A (en) | 1992-02-13 |
| JP2855796B2 JP2855796B2 (en) | 1999-02-10 |
Family
ID=15510271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2151053A Expired - Lifetime JP2855796B2 (en) | 1990-06-08 | 1990-06-08 | Semiconductor output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2855796B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2682518A2 (en) | 2012-07-03 | 2014-01-08 | Showa Denko K.K. | Method for producing composite carbon fibers |
-
1990
- 1990-06-08 JP JP2151053A patent/JP2855796B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2682518A2 (en) | 2012-07-03 | 2014-01-08 | Showa Denko K.K. | Method for producing composite carbon fibers |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2855796B2 (en) | 1999-02-10 |
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