JPH0443448B2 - - Google Patents
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- JPH0443448B2 JPH0443448B2 JP59233827A JP23382784A JPH0443448B2 JP H0443448 B2 JPH0443448 B2 JP H0443448B2 JP 59233827 A JP59233827 A JP 59233827A JP 23382784 A JP23382784 A JP 23382784A JP H0443448 B2 JPH0443448 B2 JP H0443448B2
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- multilevel
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- 238000006243 chemical reaction Methods 0.000 claims description 38
- 230000005540 biological transmission Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はDA変換装置に関し、特に2n個と異る
個数のレベルをとる多値信号を出力するDA変換
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DA conversion device, and particularly to a DA conversion device that outputs a multi-level signal having a number of levels different from 2 n .
従来のDA変換装置は、n桁の2進符号である
信号Do-1,Do-2……D1,D0を入力し、たがいに
等間隔の2n個のレベルをとる多値信号Pを数値
Do-1・2n-1+Do-2・2n-2+……+D1・2′+D0・20
の大小関係と同一のまたは逆の大小関係で出力す
る。DA変換装置の応用において、2n個と異る個
数のレベルをとる多値信号を出力するDA変換装
置が出現すれば有用であることがある。ところ
が、従来のDA変換装置は2n個と異る個数のレベ
ルをとる多値信号を出力できないという欠点があ
る。
Conventional DA converters input signals D o-1 , D o-2 ... D 1 , D 0 , which are n-digit binary codes, and convert them into multivalued signals that take 2 n levels equally spaced from each other. Signal P as a numerical value
D o-1・2 n-1 +D o-2・2 n-2 +……+D 1・2′+D 0・2 0
Output with the same or opposite magnitude relationship. In the application of a DA converter, it may be useful if a DA converter that outputs a multilevel signal having a number of levels different from 2 n appears. However, the conventional DA converter has a drawback in that it cannot output a multi-level signal having a number of levels different from 2n .
本発明が解決しようとする問題点、いいかえれ
ば本発明の目的は上記の欠点を解決して、2n個と
異る個数のレベルをとる多値信号を出力するDA
変換装置を提供することにある。
The problem to be solved by the present invention, or in other words, the purpose of the present invention is to solve the above-mentioned drawbacks and to output a multi-level signal having a number of levels different from 2n .
The purpose of the present invention is to provide a conversion device.
本発明のDA変換装置は、1〜n列目(ただ
し、n=3,4,……、1列目は最上位ビツト、
n列目は最下位ビツトである)のデータ信号を受
けて多値信号を出力するDA変換装置において、
i列目(ただし、iは2,3,……,n−1のう
ち少なくとも1つの値をとる)と(i+1)列目
とに対応する1組以上の同位ビツトの入力を有す
るDA変換回路と、前記i列目と前記(i+1)
列目とのデータ信号を受けて前記(i+1)列目
のデータ信号によつて前記i列目のデータ信号を
逆相あるいは正相に変換して出力する符号変換回
路とを含み、前記DA変換回路が前記符号変換回
路の出力を(i+1)列目のデータとして受ける
とともに他の入力データ列として前記(i+1)
列目を除く前記1〜n列目のデータ列を受けて
(22−α)値(ただし、αは2,4,6,……)
の多値信号を出力する。
The DA conversion device of the present invention has the first to nth columns (where n=3, 4,..., the first column is the most significant bit,
In a DA conversion device that receives a data signal (the nth column is the least significant bit) and outputs a multi-level signal,
A DA conversion circuit having inputs of one or more sets of identical bits corresponding to the i-th column (where i takes at least one value from 2, 3, ..., n-1) and the (i+1)-th column and the i-th column and the (i+1)
a code conversion circuit that receives the data signal of the column (i+1) and converts the data signal of the i column into a negative phase or positive phase and outputs the data signal of the (i+1) column; A circuit receives the output of the code conversion circuit as the (i+1)th column data, and also receives the (i+1) data as another input data string.
Receiving the data strings from the 1st to nth columns excluding column 2, calculate the (2 2 - α) value (where α is 2, 4, 6, ...)
Outputs a multilevel signal.
以下実施例を示す図面を参照して本発明につい
て詳細に説明する。
The present invention will be described in detail below with reference to drawings showing embodiments.
第1図は本発明のDA変換装置の第一の実施例
を示すブロツク図である。 FIG. 1 is a block diagram showing a first embodiment of the DA conversion device of the present invention.
第1図に示す実施例は、DA変換回路11と、
NOT回路111と、排他的論理和回路(以下、
EX−OR回路とよぶ)121とから構成される。
回路11は、信号D2,D1,D1′,D0を入力して
値k〔(−1)D2・22+(−1)D1・2′+(−1)D
1′・2′+(−1)D0・20〕を有する多値信号P1を出
力するように構成されている。ただしD2,D1,
D1′,D0はそれぞれ値“1”または“0”をと
り、kは定数である。したがつて第1図に示す
DA変換装置は、信号D2,D1,D1′,E0を入力し
て値k〔(−1)D2・22+(−1)D1・2′+(−1
)D
1′・2′+(−1)(D1′E0)・20〕を有する多値信号
P1
を出力する。ただしE0は値“1”または“0”
をとり、D 1′はD1の符号反転値を、は排他的
論理和演算を表す。 The embodiment shown in FIG. 1 includes a DA conversion circuit 11,
NOT circuit 111 and exclusive OR circuit (hereinafter referred to as
(referred to as EX-OR circuit) 121.
The circuit 11 inputs the signals D 2 , D 1 , D 1 ', and D 0 and calculates the value k [(-1) D 2 2 2 + (-1) D 1 2' + (-1) D
1′·2′+(−1) D 0 ·2 0 ]. However, D 2 , D 1 ,
D 1 ′ and D 0 each take the value “1” or “0”, and k is a constant. Therefore, as shown in Figure 1
The DA converter inputs the signals D 2 , D 1 , D 1 ', E 0 and converts the value k [(-1) D 2 2 2 + (-1) D 1 2' + (-1
) D
1′・2′+(−1) (D1 ′ E0)・2 0 ]
P1
Output. However, E 0 has the value “1” or “0”
where D 1 ' represents the sign-inverted value of D 1 , and represents the exclusive OR operation.
第1図に示すDA変換装置の動作を説明する
と、信号E0=0の場合は、2進符号である信号
D2,D1,D1′をD−A変換して間隔が“2k”で
あり“−7k”〜“7k”の8(=23)個のレベルを
とる多値信号P1を出力する。信号E0=1の場合
は、信号(D2,D1,D1′)=(000)のとき多値信
号P1=9k、信号(D2,D1,D1′)=(111)のとき
多値信号P1=−9kとなる。したがつて多値信号
P1のレベル数は、信号E0=0とすると23個とな
り、信号E0=1とすると信号E0=0の場合の23個
のレベルの上と下に1個ずつが追加されるので全
体で(23+2)個のレベルが得られる。 To explain the operation of the DA converter shown in Fig. 1, when the signal E 0 = 0, the signal is a binary code.
D-A converts D 2 , D 1 , D 1 ' and outputs a multilevel signal P 1 with an interval of "2k" and 8 (=2 3 ) levels from "-7k" to "7k". do. In the case of signal E 0 = 1, when signal (D 2 , D 1 , D 1 ′) = (000), multilevel signal P 1 = 9k, signal (D 2 , D 1 , D 1 ′) = (111 ), the multilevel signal P 1 =−9k. Therefore, the multilevel signal
The number of levels of P 1 will be 23 if the signal E 0 = 0, and if the signal E 0 = 1, one will be added above and below the 23 levels when the signal E 0 = 0. A total of (2 3 + 2) levels are obtained.
第2図は本発明のDA変換装置の第二の実施例
を示すブロツク図である。 FIG. 2 is a block diagram showing a second embodiment of the DA conversion device of the present invention.
第2図に示す実施例は、DA変換回路21と、
NOT回路212と、EX−OR回路222とから
構成される。DA変換回路21は、信号D2,D2′,
D1,D0を入力して値k〔(−1)D2・22+(−1)D
2′・22+(−1)D1・2′+(−1)D0・20〕を有す
る多値信号P2を出力するように構成されている。
ただしD2′は値“1”または“0”をとる。した
がつて第2図に示すDA変換装置は、信号D2,
D2′,E1,D0を入力して値k〔(−1)D2・22+
(−1)D2′・22+(−1)(D2′E1)・2′+(−1
)D0・
20〕を有する多値信号P2を出力する。ただしE1は
値“1”または“0”をとる。 The embodiment shown in FIG. 2 includes a DA conversion circuit 21,
It is composed of a NOT circuit 212 and an EX-OR circuit 222. The DA conversion circuit 21 receives signals D 2 , D 2 ′,
Enter D 1 and D 0 and enter the value k [(-1) D 2・2 2 + (-1) D
2′·2 2 +(−1) D 1·2′+(−1) D 0·2 0 ] .
However, D 2 ' takes the value "1" or "0". Therefore, the DA converter shown in FIG .
Input D 2 ′, E 1 , D 0 and set the value k [(-1) D 2・2 2 +
(-1) D 2′・2 2 +(-1) (D2 ′ E1)・2′+(-1
) D 0・
2 0 ] is output. However, E1 takes the value "1" or "0".
第2図に示すDA変換装置の動作を説明する
と、信号E1=0の場合は、2進符号である信号
D2,D2′,D0をD−A変換して間隔が“2k”で
あり“−7k”〜“7k”の8(=23)個のレベルを
とる多値信号P2を出力する。信号E1=1の場合
は、信号(D2,D2′,D0)=(000)のとき多値信
号P1=11k、信号(D2,D2′,D0)=(001)のと
き多値信号P1=9k、信号(D2,D2′,D0)=
(111)のとき多値信号P1=11k、信号(D2,D2,
D0)=(110)のとき多値信号P1=−9kとなる。し
たがつて多値信号P2のレベル数は、信号E1=0
とすると23個となり、信号E1=1とすると信号E1
=0の場合の23個のレベルの上と下に2個ずつが
追加されるので全体で(23+4)個のレベルが得
られる。 To explain the operation of the DA converter shown in FIG. 2, when the signal E 1 =0, the signal is a binary code.
D-A conversion is performed on D 2 , D 2 ′, and D 0 to output a multilevel signal P 2 with an interval of “2k” and 8 (=2 3 ) levels from “-7k” to “7k”. do. In the case of signal E 1 = 1, when signal (D 2 , D 2 ′, D 0 ) = (000), multilevel signal P 1 = 11k, signal (D 2 , D 2 ′, D 0 ) = (001 ), multilevel signal P 1 = 9k, signal (D 2 , D 2 ′, D 0 ) =
(111), the multilevel signal P 1 = 11k, the signal (D 2 , D 2 ,
When D 0 )=(110), the multilevel signal P 1 becomes −9k. Therefore, the number of levels of the multilevel signal P 2 is as follows: signal E 1 =0
Then, the number becomes 2 3 , and if the signal E 1 = 1, the signal E 1
Two levels are added above and below the 23 levels in the case of =0, resulting in a total of ( 23 +4) levels.
第3図は本発明のDA変換装置の第三の実施例
を示すブロツク図である。 FIG. 3 is a block diagram showing a third embodiment of the DA conversion device of the present invention.
第3図に示す実施例は、DA変換回路31と、
2個のNOT回路311,312と、2個のEX−
OR回路321,322とから構成される。回路
31は、信号D2,D2′,D1,D1′,D0を入力して
値k〔(−1)D2・22+(−1)D2′・22+(−1)D
1・2′+(−1)D1・2′+(−1)D0・20〕を有す
る多値信号P3を出力するように構成されている。
したがつて第3図に示すDA変換装置は、信号
D2,D2′,E1,D1′,E0を入力して値k〔(−1)D
2・22+(−1)D2′・22+(−1)(D2′E1)・2′
+(−
1)D1′・2′+(−1)(D′1 E0)・20〕を有する多
値信
号P3を出力する。 The embodiment shown in FIG. 3 includes a DA conversion circuit 31,
Two NOT circuits 311, 312 and two EX-
It is composed of OR circuits 321 and 322. The circuit 31 inputs the signals D 2 , D 2 ′, D 1 , D 1 ′, D 0 and calculates the value k [(-1) D 2 2 2 + (-1) D 2 2 2 + ( -1) D
1.2'+(-1) D 1.2'+(-1) D 0.2 0 ].
Therefore, the DA converter shown in FIG.
Input D 2 , D 2 ′, E 1 , D 1 ′, E 0 and set the value k [(-1) D
2・2 2 +(−1) D 2′・2 2 +(−1) (D2 ′ E1)・2′
+(-
1) A multilevel signal P 3 having D 1′·2′+(−1) (D ′ 1 E0) ·2 0 ] is output.
第3図に示すDA変換装置の動作を説明する
と、信号(E1,E0)=(00)の場合は、2進符号
である。信号D2,D2′,D1′をD−A変換して間
隔が“2k”であり、“−7k”〜“7k”の8(=23)
個のレベルをとる多値信号P3を出力する。信号
(E1,E0)=(01)の場合は、信号(D2,D2′,
D1′)=(000)のとき多値信号P3=9k、信号(D2,
D2′,D1′)=(111)のとき多値信号P3=−9kとな
る。信号(E1,E0)=(10)の場合は、信号(D2,
D2′,D2)=(000)のとき多値信号P3=11k、信号
(D2,D2′,D1′)=(111)のとき多値信号P3=−
11kとなる。信号(E1,E0)=(11)の場合は、信
号(D2,D2′,D1′)=(000)のとき多値信号P3=
13kとなり、信号(D2,D2′,D1′)=(111)のと
き多値信号P3=−13kとなる。したがつて多値信
号P3のレベル数は、信号(E1,E0)=(00)とす
ると23個となり、信号(E1,E0)≠(00)とすると
信号(E1,E0)=(100)の場合の23個のレベルの
上と下に3個ずつが追加されるので全体で(23+
6)個のレベルが得られる。 To explain the operation of the DA converter shown in FIG. 3, when the signal (E 1 , E 0 )=(00), it is a binary code. The signals D 2 , D 2 ′, D 1 ′ are DA converted and the interval is “2k”, and 8 (=2 3 ) from “-7k” to “7k”
A multilevel signal P3 having three levels is output. If the signal (E 1 , E 0 ) = (01), then the signal (D 2 , D 2 ′,
When D 1 ′) = (000), multilevel signal P 3 = 9k, signal (D 2 ,
When D 2 ′, D 1 ′)=(111), the multilevel signal P 3 becomes −9k. If the signal (E 1 , E 0 ) = (10), then the signal (D 2 ,
When D 2 ′, D 2 ) = (000), the multi-value signal P 3 = 11k; when the signal (D 2 , D 2 ′, D 1 ′) = (111), the multi-value signal P 3 = −
It will be 11k. When the signal (E 1 , E 0 ) = (11), when the signal (D 2 , D 2 ′, D 1 ′) = (000), the multilevel signal P 3 =
13k, and when the signal (D 2 , D 2 ′, D 1 ′)=(111), the multilevel signal P 3 becomes −13k. Therefore, the number of levels of the multilevel signal P 3 is 23 if the signal (E 1 , E 0 ) = (00), and the number of levels of the multilevel signal P 3 is 23 if the signal (E 1 , E 0 )≠( 00 ). , E 0 ) = (100), 3 pieces are added above and below the 2 3 levels, so the total is (2 3 +
6) Levels are obtained.
以上説明した第一〜第三の実施例を本発明の3
段のDA変換装置ということにする。 The first to third embodiments explained above are the third embodiments of the present invention.
Let's call it the DA conversion device.
本発明のn段のDA変換装置は、NOT回路1
11およびEX−OR回路121とから構成され
る部分に相当する部分を最大(n−1)組備える
ことができる。 The n-stage DA converter of the present invention has a NOT circuit 1
11 and EX-OR circuit 121 can be provided at maximum (n-1).
NOT回路111およびEX−OR回路121か
ら構成される部分に相当する部分を(n−1)組
備える本発明のn段のDA変換装置は、信号
(Eo-2,Eo-3……E1,E0)=(00……00)の場合、
n桁の2進符号である信号Do-1,Do-1′……D2′,
D1′をDA変換して多値信号Poを出力し、その信
号レベルの個数は2n個である。多値信号Poのレベ
ルの最大個数は(2n+1−2)個である。 The n-stage DA converter of the present invention, which includes (n-1) sets of parts corresponding to the parts constituted by the NOT circuit 111 and the EX-OR circuit 121, has a signal (E o-2 , E o-3 . . . If E 1 , E 0 ) = (00...00),
Signals D o-1 , D o-1 ′……D 2 ′, which are n-digit binary codes,
D 1 ' is subjected to DA conversion and a multilevel signal P o is output, and the number of signal levels is 2 n . The maximum number of levels of the multilevel signal P o is (2 n+1 −2).
次に本発明のDA変換装置の具体的な応用の一
例について説明する。 Next, an example of a specific application of the DA conversion device of the present invention will be explained.
第4図は、円状256値直交振幅変調方式を用い
る変調器の一例を示すブロツク図であり、DA変
換部4は本発明のDA変換装置の第四の実施例で
ある。 FIG. 4 is a block diagram showing an example of a modulator using the circular 256-value orthogonal amplitude modulation method, and the DA converter 4 is a fourth embodiment of the DA converter of the present invention.
従来の256値直交振幅変調器は、それぞれが4
桁の2進符号であるp信号S11,S21,S31,S41・
q信号S12,S22,S32,S42に所定の論理変換をし
た後、2個の従来の4段のDA変換回路でそれぞ
れD−A変換してそれぞれが24(=16)個のレベ
ルをとる信号P4・信号Q4とし、同一周波数であ
りたがいに直交する二つの搬送波を、一方は信号
P4で他方は信号Q4で振幅変調し、合成して搬送
波帯信号とする。 Conventional 256-value quadrature amplitude modulators each have 4
p signals S 11 , S 21 , S 31 , S 41 , which are binary codes of digits;
After performing predetermined logic conversion on the q signals S 12 , S 22 , S 32 , and S 42 , two conventional 4-stage DA conversion circuits perform D-A conversion on each signal, resulting in 24 (=16) signals. Let the signal P 4 and the signal Q 4 take the level of
P 4 and the other signal Q 4 are amplitude modulated and combined to form a carrier band signal.
第5図は、多値直交振幅変調方式の信号点の配
置を示す説明図であり、256値の場合について、
信号平面上の第一象限に位置する信号点を示して
いる。黒丸印および白丸印の合計64個の信号点は
上記のようにして作つた256個の信号点のうちの
1/4を示している。信号点群の最外側点が正方形
であるからこのような変調方式を正方状256値直
交振幅変調方式ということにする。 FIG. 5 is an explanatory diagram showing the arrangement of signal points of the multilevel orthogonal amplitude modulation method, and in the case of 256 values,
The signal points located in the first quadrant on the signal plane are shown. A total of 64 signal points indicated by black circles and white circles indicate 1/4 of the 256 signal points created as described above. Since the outermost point of the signal point group is a square, such a modulation method will be referred to as a square 256-value orthogonal amplitude modulation method.
多値直交振幅変調方式は、搬送波帯の専有周波
数幅の単位周波数当りの伝送情報量が大きく、無
線伝送において電波を有効に使用できるので、大
容量のデイジタル無線通信に用いられる。 The multilevel orthogonal amplitude modulation method is used for large-capacity digital wireless communication because the amount of information transmitted per unit frequency of the exclusive frequency width of the carrier band is large and radio waves can be used effectively in wireless transmission.
さて、変調された搬送波帯信号の振幅は信号平
面上の原点から信号点までの距離に比例するか
ら、正方状256値直交振幅変調方式においては、
振幅の最大値と最小値との比Rは√2×152/√
2×12=15と大きな値となる。変調器から復調器
にいたる伝送路には振幅に依存する伝送歪があ
り、Rの値が大きいほどこの歪が大きい。 Now, since the amplitude of the modulated carrier band signal is proportional to the distance from the origin to the signal point on the signal plane, in the square 256-value orthogonal amplitude modulation method,
The ratio R between the maximum value and the minimum value of amplitude is √2×15 2 /√
2×1 2 =15, which is a large value. The transmission path from the modulator to the demodulator has transmission distortion that depends on the amplitude, and the larger the value of R, the greater this distortion.
第4図に示す変調器は、第5図の黒丸印および
三角印で信号点の一部が表される円状256値直交
振幅変調方式を用いる。すなわち、信号平面の第
第一象限においては、正方状256値直交振幅変調
方式の信号点の一部である信号点a,b,c,
d,e,fを信号点a′,b′,c′,d′,e′,f′に変
更
し、第二,三,四象限においても同様に変更して
信号点群の最外側点を円状にする。この信号点配
置においては、Rの値は√157であり正方状256値
直交振幅変調方式におけるRの値の役0.84倍にな
つている。 The modulator shown in FIG. 4 uses a circular 256-value quadrature amplitude modulation system in which some signal points are represented by black circles and triangles in FIG. That is, in the first quadrant of the signal plane, signal points a, b, c, which are part of the signal points of the square 256-value orthogonal amplitude modulation method,
Change d, e, f to signal points a', b', c', d', e', f', and change them in the same way in the second, third, and fourth quadrants to find the outermost point of the signal point group. Make it circular. In this signal point arrangement, the value of R is √157, which is 0.84 times the value of R in the square 256-value orthogonal amplitude modulation system.
第4図に示す変調器の構成を説明すると、p信
号S11、q信号S12を入力し4相送信差動変換して
p信号D3、q信号D3(二つのD3のうち上の方をp
信号D3とする)を出力する送信差動論理回路4
1と、p信号S21,S31,S41・q信号S22,S32,
S42を入力し信号TCONT・p信号S21′,S31′,
S41′・q信号S22′,S32′,S42′・p信号H1・q信
号H2を出力する送信論理変換部42と、p信号
S21,S31,S41・q信号S22,S32,S42・p信号
S21′,S32′,S42′・q信号S22′,S32′,S42′・信
号
TCONTを入力しp信号S21,S31,S41・q信号
S22,S32,S42を出力するかまたはp信号S21′,
S31′,S41′・q信号S22′,S32′,S42′を出力する
送信径路選択部43と、13個のEX−OR回路と
4個のAND回路とを有しp信号D3・q信号D3と
送信径路選択部43の出力とp信号H1・q信号
H2とを入力しp信号D3・q信号D3とそれぞれが
3桁の2進符号であるp信号・q信号とp信号
E0・q信号E0とを出力する符号変換部44と、
それぞれが3個のEX−OR回路を有しp信号D3
またはq信号D3と符号変換部44の出力であり
3桁の2進符号であるp信号またはq信号とp信
号E0またはq信号E0とを入力しp信号D3,D2,
D1,D1′,E0またはq信号D3,D2,D1,D1′,E0
を出力する2個の符号変換部45と、NOT回路
411とEX−OR回路421とDA変換回路41
とを有しp信号D3,D2,D1,D1′,E0またはq
信号D3,D2,D1,D1′,E0を入力し多値信号で
ある信号P4または信号Q4を出力する2個のDA変
換部4と、直交変調回路(図示されていない)と
を備えて構成されている。 To explain the configuration of the modulator shown in FIG. 4, a p signal S 11 and a q signal S 12 are inputted and subjected to four-phase transmission differential conversion to produce a p signal D 3 and a q signal D 3 (the upper of the two D 3 p toward
Transmission differential logic circuit 4 that outputs signal D3 )
1, p signals S 21 , S 31 , S 41 and q signals S 22 , S 32 ,
S 42 is input and the signal TCONT/p signal S 21 ′, S 31 ′,
A transmission logic converter 42 that outputs S 41 ′ and q signals S 22 ′, S 32 ′, S 42 ′ and p signals H 1 and q signals H 2 ;
S 21 , S 31 , S 41・q signal S 22 , S 32 , S 42・p signal
S 21 ′, S 32 ′, S 42 ′・q signal S 22 ′, S 32 ′, S 42 ′・signal
Input TCONT and send p signal S 21 , S 31 , S 41 and q signal
S 22 , S 32 , S 42 or p signal S 21 ′,
It has a transmission path selection unit 43 that outputs S 31 ′, S 41 ′, and q signals S 22 ′, S 32 ′, and S 42 ′, 13 EX-OR circuits, and 4 AND circuits, and p signal D3・q signal D3 , output of transmission path selection section 43, p signal H1・q signal
Input H 2 , p signal D 3 , q signal D 3 , p signal, q signal, and p signal, each of which is a 3-digit binary code.
a code conversion unit 44 that outputs E 0 and q signal E 0 ;
Each has 3 EX-OR circuits and p signal D 3
Alternatively, input the q signal D 3 and the p signal or q signal, which is the output of the code converter 44 and is a 3-digit binary code, and the p signal E 0 or the q signal E 0 , and convert the p signal D 3 , D 2 ,
D 1 , D 1 ′, E 0 or q signal D 3 , D 2 , D 1 , D 1 ′, E 0
two code converters 45 that output
and p signal D 3 , D 2 , D 1 , D 1 ′, E 0 or q
Two DA converters 4 input signals D 3 , D 2 , D 1 , D 1 ′, E 0 and output a signal P 4 or signal Q 4 which is a multilevel signal, and a quadrature modulation circuit (not shown). (No)
次に第4図に示す変調器の動作について説明す
る。 Next, the operation of the modulator shown in FIG. 4 will be explained.
この変調器の入力信号であるp信号S11,S21,
S31,S41・q信号S12,S22,S32,S42に対応する
信号点が第5図の黒丸印(第二・三・四象限にも
原点に対して点対称に黒丸印が存在するものとす
る)の一つである場合は、送信論理変換部42は
このことを検出して、論理値“0”をとる信号
TCONTとそれぞれ値が“0”であるp信号
H1・q信号H2とを出力する。送信径路選択部4
3は信号TCONTの値が“0”のときp信号S21,
S31,S41・q信号S22,S32,S42を選択して出力す
る。符号変換部44と2個の符号変換部45とは
一体となつてp信号S21,S31,S41,H1・q信号
S22,S32,S42,H2を回転対称変換し、一方の符
号変換部45はp信号D3,D2,D1,D1′,E0を
出力し、他方の符号変換部45はq信号D3,D2,
D1,D1′,E0を出力する(この場合E0=0とな
る)。2個の符号変換部45の出力は2個のDA
変換部4でそれぞれD−A変換されて信号P4・
信号Q4となる。E0=0であるから、第1図に示
す実施例の説明から容易に類推できるように信号
P4・信号Q4のとるレベルの個数は24(=16)個で
ある。直交変調回路は、同一周波数でたがいに直
交する二つの搬送波を、一方は信号P4で他方は
信号Q4で振幅変調し、合成して搬送波帯信号と
する(この部分は図示されていない)。P信号
S211,S31,S41,H1・q信号S22,S32,S42,H2
は符号変換部44と2個の符号変換部45とで回
転対称変換されているので、上記のようにして得
られた任意の信号点に対応するp信号S21,S31,
S41,H1・q信号S22,S32,S42,H2と、この信
号点を信号平面の原点を中心としてπ/2・πま
たは3π/2回転した位置の信号点に対応するp
信号S21,S31,S41,H1・q信号S22,S32,S42,
H2とは一致する。したがつてp信号S11,S21,
S31,S41・q信号S12,S22,S32,S42のそれぞれ
の2桁目以降の符号が受信復調のさいの4相位相
不確実性の影響を受けない信号点配置になつてい
る。S11,S12は送信差動論理回路41の作用によ
り4相位相不確実性の影響を受けない。 The p signals S 11 , S 21 , which are the input signals of this modulator,
The signal points corresponding to S 31 , S 41 and q signals S 12 , S 22 , S 32 , and S 42 are marked with black circles in Figure 5 (black circles are also marked symmetrically with respect to the origin in the second, third, and fourth quadrants). ), the transmission logic converter 42 detects this and converts the signal to take a logical value of "0".
TCONT and p signal whose value is “0” respectively
Outputs H 1 and q signal H 2 . Transmission route selection section 4
3 is the p signal S 21 when the value of the signal TCONT is “0”,
S 31 , S 41 and q signals S 22 , S 32 and S 42 are selected and output. The code converter 44 and the two code converters 45 are integrated to convert p signals S 21 , S 31 , S 41 , H 1 and q signals.
S 22 , S 32 , S 42 , H 2 are rotationally symmetrically transformed, one code conversion unit 45 outputs p signals D 3 , D 2 , D 1 , D 1 ′, E 0 , and the other code conversion unit 45 is the q signal D 3 , D 2 ,
D 1 , D 1 ′, and E 0 are output (in this case, E 0 =0). The outputs of the two code converters 45 are the two DAs.
The converter 4 converts the signal P4 into a signal P4 .
Signal Q becomes 4 . Since E 0 = 0, the signal
The number of levels taken by P 4 and signal Q 4 is 2 4 (=16). The quadrature modulation circuit amplitude-modulates two carrier waves that are orthogonal to each other at the same frequency, one with signal P 4 and the other with signal Q 4 , and synthesizes them into a carrier band signal (this part is not shown). . P signal
S 211 , S 31 , S 41 , H 1・q signal S 22 , S 32 , S 42 , H 2
are rotationally symmetrically transformed by the code converter 44 and the two code converters 45, so the p signals S 21 , S 31 , corresponding to arbitrary signal points obtained as described above are
S 41 , H 1・q signal S 22 , S 32 , S 42 , H 2 corresponds to the signal point at the position rotated by π/2・π or 3π/2 around the origin of the signal plane. p
Signal S 21 , S 31 , S 41 , H 1・q signal S 22 , S 32 , S 42 ,
It is consistent with H 2 . Therefore, p signals S 11 , S 21 ,
The codes from the second digit onward of each of the S 31 , S 41 and q signals S 12 , S 22 , S 32 , and S 42 have a signal point arrangement that is not affected by the four-phase phase uncertainty during reception demodulation. ing. S 11 and S 12 are not affected by four-phase phase uncertainty due to the action of the transmission differential logic circuit 41.
p信号S11,S21,S31,S41・q信号S12,S22,
S32,S42に対応する信号点が第5図の白丸印の一
つであるときは、送信論理変換部42はこのこと
を検出して、論理値“1”をとる信号TCONTを
出力し、またp信号S21,S31,S41・q信号S22,
S32,S42を論理変換してp信号S21′,S31′,
S41′・q信号S22′,S32′,S42′とp信号H1・q信
号H2とを出力する。第6図は、この論理変換の
真理値表を、第5図に示す信号点a,b,c,
d,e,fを信号点a′,b′,c′,d′,e′,f′に変
更
する場合を例にとつて示したものである。p信号
H1・q信号H2のいずれか一方が“0”に、他方
が“1”になる。送信径路選択部43は信号
TCONTの値が論理値“1”のときp信号S21′,
S31′,S41′・q信号S22′,S32′,S42′を選択して
出力する。符号変換部44と2個の符号変換部4
5と2個のDA変換部4とは、すでに説明したの
と同じ動作をする。ただしこの場合はp信号
E0・q信号E0のいずれか一方が“1”となるの
で信号P4・信号Q4のいずれか一方がとるレベル
の個数は18個となる。この場合もp信号S11,
S21,S31,S41・q信号S12,S22,S32,S42のそれ
ぞれの2桁目以降の符号が受信復調のさいの4相
位相不確性の影響を受けない信号点配置となつて
いる。 p signal S 11 , S 21 , S 31 , S 41・q signal S 12 , S 22 ,
When the signal point corresponding to S 32 and S 42 is one of the white circles in FIG. 5, the transmission logic converter 42 detects this and outputs a signal TCONT with a logic value of "1". , and p signals S 21 , S 31 , S 41 and q signals S 22 ,
By logically converting S 32 and S 42 , p signals S 21 ′, S 31 ′,
S 41 ′ and q signals S 22 ′, S 32 ′, and S 42 ′ and p signal H 1 and q signal H 2 are output. FIG. 6 shows the truth table of this logic conversion at the signal points a, b, c, shown in FIG.
This example shows a case where d, e, and f are changed to signal points a', b', c', d', e', and f'. p signal
One of the H 1 and q signals H 2 becomes "0" and the other becomes "1". The transmission path selection unit 43
When the value of TCONT is the logical value “1”, the p signal S 21 ′,
S 31 ′, S 41 ′ and q signals S 22 ′, S 32 ′, and S 42 ′ are selected and output. Code converter 44 and two code converters 4
5 and the two DA converters 4 operate in the same manner as already described. However, in this case, the p signal
Since either the E 0 or the q signal E 0 becomes "1", the number of levels that either the signal P 4 or the signal Q 4 takes becomes 18. In this case as well, p signal S 11 ,
S 21 , S 31 , S 41 and q signals S 12 , S 22 , S 32 , and S 42 have a signal point arrangement in which the codes from the second digit onward are not affected by the four-phase phase uncertainty during reception demodulation. It is becoming.
以上説明したように、本発明のDA変換装置の
第四の実施例を用いることにより、電波を有効に
利用してしかも伝送路において受ける歪が小さい
円状256値直交振幅変調方式を用いる変調器を提
供できるという効果がある。 As explained above, by using the fourth embodiment of the DA converter of the present invention, a modulator using a circular 256-value quadrature amplitude modulation method that effectively utilizes radio waves and suffers less distortion in the transmission path. It has the effect of being able to provide
以上詳細に説明したように、本発明を用いるこ
とにより2n個と異なる偶数の個数のレベルをとる
多値信号を出力するDA変換装置を提供できると
いう効果がある。
As described above in detail, by using the present invention, it is possible to provide a DA conversion device that outputs a multilevel signal that takes an even number of levels different from 2 n levels.
第1図、第2図、第3図は本発明のDA変換装
置の第一、第二、第三の実施例を示すブロツク
図、第4図は本発明のDA変換装置の第四の実施
例を備える変調器を示すブロツク図、第5図は多
値直交振幅変調方式の信号点の配置を示す説明
図、第6図は送信論理変換部の論理変換の真理値
表を示す図面である。
11……DA変換回路、111……NOT回路、
121……EX−OR回路。
1, 2, and 3 are block diagrams showing first, second, and third embodiments of the DA converter of the present invention, and FIG. 4 is a fourth embodiment of the DA converter of the present invention. FIG. 5 is an explanatory diagram showing the arrangement of signal points in the multilevel orthogonal amplitude modulation method, and FIG. 6 is a diagram showing the truth table of logic conversion in the transmission logic conversion section. . 11...DA conversion circuit, 111...NOT circuit,
121...EX-OR circuit.
Claims (1)
列目は最上位ビツト、n列目は最下位ビツトであ
る)のデータ信号を受けて多値信号を出力する
DA変換装置において、i列目(ただし、iは
2,3,……,n−1のうち少なくとも1つの値
をとる)と(i+1)列目とに対応する1組以上
の同位ビツトの入力を有するDA変換回路と、前
記i列目と前記(i+1)列目とのデータ信号を
受けて前記(i+1)列目のデータ信号によつて
前記i列目のデータ信号を逆相あるいは正相に変
換して出力する符号変換回路とを含み、前記DA
変換回路が前記符号変換回路の出力を(i+1)
列目のデータとして受けるとともに他の入力デー
タ列として前記(i+1)列目を除く前記1〜n
列目のデータ列を受けて(2n−α)値(ただし、
αは2,4,6,……)の多値信号を出力するこ
とを特徴とするDA変換装置。1 1st to nth columns (where n=3, 4,..., 1
The 1st column is the most significant bit, the nth column is the least significant bit) and outputs a multi-level signal.
In a DA conversion device, input of one or more sets of identical bits corresponding to the i-th column (where i takes at least one value from 2, 3, ..., n-1) and the (i+1)-th column a DA conversion circuit having a DA conversion circuit, which receives data signals from the i-th column and the (i+1)-th column, and converts the data signal from the i-th column into an inverse phase or positive phase by the data signal from the (i+1) column; and a code conversion circuit that converts and outputs the DA.
A conversion circuit converts the output of the code conversion circuit into (i+1)
1 to n except for the (i+1)th column are received as the data in the column and as other input data strings.
The (2 n − α) value (however,
A DA conversion device characterized in that it outputs a multi-value signal where α is 2, 4, 6, ...).
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23382784A JPS61112431A (en) | 1984-11-06 | 1984-11-06 | Digital-analog converter |
US06/794,662 US4750191A (en) | 1984-11-06 | 1985-11-04 | D/A converter capable of producing an analog signal having levels of a preselected number different from 2N and communication network comprising the D/A converter |
AU49365/85A AU588162B2 (en) | 1984-11-06 | 1985-11-05 | D/A converter capable of producing an analog signal having levels of a preselected number different from 2N and communication network comprising the D/A converter |
CA000494589A CA1282494C (en) | 1984-11-06 | 1985-11-05 | D/a converter capable of producing an analog signal having levels of a preselected number different from 2 and communication network comprising the d/a converter |
DE3588126T DE3588126T2 (en) | 1984-11-06 | 1985-11-06 | D / A converter capable of generating an analog signal with a preselected level number different from 2N, and a communication network provided with such a D / A converter |
BR8505564A BR8505564A (en) | 1984-11-06 | 1985-11-06 | DIGITAL-ANALOG CONVERTER, MODULATOR AND DEMODULATOR |
EP93119447A EP0588387B1 (en) | 1984-11-06 | 1985-11-06 | D/A converter capable of producing an analog signal having levels of a preselected number different from 2**N and communication network comprising the D/A converter |
DE3588002T DE3588002T2 (en) | 1984-11-06 | 1985-11-06 | QAM modulator and demodulator. |
EP85114133A EP0186757B1 (en) | 1984-11-06 | 1985-11-06 | QAM modulator and demodulator |
CN85108891A CN1007951B (en) | 1984-11-06 | 1985-11-06 | D/a converter capable of producing an analog signal having levels of a preselected number different from 2 to the power n and communication network comprising the d/a converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23382784A JPS61112431A (en) | 1984-11-06 | 1984-11-06 | Digital-analog converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61112431A JPS61112431A (en) | 1986-05-30 |
JPH0443448B2 true JPH0443448B2 (en) | 1992-07-16 |
Family
ID=16961181
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23382784A Granted JPS61112431A (en) | 1984-11-06 | 1984-11-06 | Digital-analog converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61112431A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07112208B2 (en) * | 1987-02-19 | 1995-11-29 | 富士通株式会社 | Multi-level amplitude modulation / demodulation communication system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57118430A (en) * | 1981-01-14 | 1982-07-23 | Matsushita Electric Ind Co Ltd | Digital-to-analog converter |
JPS58117723A (en) * | 1981-12-31 | 1983-07-13 | Advantest Corp | Digital-to-analog converter |
-
1984
- 1984-11-06 JP JP23382784A patent/JPS61112431A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57118430A (en) * | 1981-01-14 | 1982-07-23 | Matsushita Electric Ind Co Ltd | Digital-to-analog converter |
JPS58117723A (en) * | 1981-12-31 | 1983-07-13 | Advantest Corp | Digital-to-analog converter |
Also Published As
Publication number | Publication date |
---|---|
JPS61112431A (en) | 1986-05-30 |
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