JPH0442126A - Production of liquid crystal display element - Google Patents
Production of liquid crystal display elementInfo
- Publication number
- JPH0442126A JPH0442126A JP14916790A JP14916790A JPH0442126A JP H0442126 A JPH0442126 A JP H0442126A JP 14916790 A JP14916790 A JP 14916790A JP 14916790 A JP14916790 A JP 14916790A JP H0442126 A JPH0442126 A JP H0442126A
- Authority
- JP
- Japan
- Prior art keywords
- selection lines
- terminal
- substrate
- spacers
- row selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 125000006850 spacer group Chemical group 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 239000011159 matrix material Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、アクティブマトリクス基板を用いた液晶表示
素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a liquid crystal display element using an active matrix substrate.
［従来の技術とその課題］
薄膜トランジスタをスイ・ソチング素子とするアクティ
ブマトリクス液晶表示素子は、共通電極が形成された基
板と、画素電極と薄膜トランジスタとの１組で構成され
る画素構成要素を多数マトリクス状に配置した基板とを
備え、スペーサを介して対面する２枚の基板間に液晶層
が形成されている。[Prior art and its problems] An active matrix liquid crystal display device that uses thin film transistors as switching elements has a matrix of many pixel components each consisting of a substrate on which a common electrode is formed, and a pair of pixel electrodes and thin film transistors. A liquid crystal layer is formed between two substrates that face each other with a spacer in between.
［発明が解決しようとする課題］
この液晶表示素子は、画素電極と薄膜トランジスタが形
成された基板上に、各薄膜トランジスタ間を繋ぐ配線部
が形成されており、その配線部の高さは、画素電極より
高く設けられている。従って、基板間の均一なギャップ
を形成するためには、スペーサを配線部の上に置く必要
がある。[Problems to be Solved by the Invention] In this liquid crystal display element, a wiring portion connecting each thin film transistor is formed on a substrate on which a pixel electrode and a thin film transistor are formed, and the height of the wiring portion is equal to or smaller than that of the pixel electrode. It is set higher. Therefore, in order to form a uniform gap between the substrates, it is necessary to place a spacer on the wiring part.
ところが、スペーサを基板上に散布した場合に、スペー
サの散布密度に応じて、基板間にギャップムラが生じな
り、あるいは、画素電極上にスペーサが乗ることで、画
面品位を悪くする課題を有していた。However, when the spacers are spread on the substrate, depending on the density of the spacers, uneven gaps may occur between the substrates, or the spacers may ride on the pixel electrodes, resulting in poor screen quality. was.
本発明は上記事情に基づいてなされたもので、その目的
は、基板間のギャップムラをなくすとともに、画素電極
上に乗るスペーサを減らすことで、画面品位の悪化を防
止することのできる液晶表示素子の製造方法分提供する
ことにある。The present invention has been made based on the above-mentioned circumstances, and an object of the present invention is to provide a liquid crystal display element that can prevent the deterioration of screen quality by eliminating uneven gaps between substrates and reducing the number of spacers placed on pixel electrodes. The purpose is to provide a manufacturing method.
［課題を解決するための手段］
本発明は上記目的を達成するために、画素電極と薄膜ト
ランジスタとで構成される画素構成要素が多数マトリク
ス状に配置されて、前記各薄膜トランジスタを接続する
複数の行選択線および列選択線が形成された一方の基板
と、共通電極が形成された他方の基板とを備え、前記一
方の基板上に散布されたスペーサを介して対面する前記
一方の基板と前記他方の基板との間に液晶層が設けられ
た液晶表示素子において、
前記複数の行選択線が一括して接続された第１の端子、
および前記複数の列選択線が一括して接続された第２の
端子を設け、前記第１の端子および前記第２の端子を、
それぞれ正電位とアース電位およびアース電位と正電位
とに、前記薄膜トランジスタの動作速度より遅い速度で
交互に切り換え接続して前記複数の行選択線および列選
択線を交互に正に帯電させながら、負に帯電させた前記
スペーサを前記一方の基板上に散布することにより、正
に帯電した前記複数の行選択線および列選択線上に、負
に帯電した前記スペーサを乗せることを技術的手段とす
る。[Means for Solving the Problems] In order to achieve the above object, the present invention has a plurality of pixel components each consisting of a pixel electrode and a thin film transistor arranged in a matrix, and a plurality of rows connecting each of the thin film transistors. one substrate on which a selection line and a column selection line are formed, and another substrate on which a common electrode is formed, the one substrate and the other substrate facing each other through spacers scattered on the one substrate; In a liquid crystal display element in which a liquid crystal layer is provided between a substrate and a substrate, a first terminal to which the plurality of row selection lines are collectively connected;
and a second terminal to which the plurality of column selection lines are collectively connected, and the first terminal and the second terminal are connected to each other.
The plurality of row selection lines and column selection lines are alternately charged positively by being alternately connected to a positive potential and a ground potential, and between a ground potential and a positive potential at a speed slower than the operating speed of the thin film transistor, respectively. The technical means is to place the negatively charged spacers on the plurality of positively charged row selection lines and column selection lines by scattering the spacers charged as above on the one substrate.
［作用コ
上記構成よりなる本発明は、複数の行選択線および列選
択線（配線部）を正に帯電させることで、負に帯電され
たスペーサは、一方の基板上に散布された際に、各行選
択線および列選択線上に引き寄せられて、各行選択線お
よび列選択線」、に乗ることになる。[Function] The present invention having the above configuration positively charges a plurality of row selection lines and column selection lines (wiring portions), so that negatively charged spacers can be scattered on one substrate. , are drawn onto each row selection line and column selection line, and ride on each row selection line and column selection line.
なお、行選択線と列選択線とを同時に正に帯電させると
、薄膜トランジスタが導通状態となり、その結果、画素
を極も配線部と同じ電位に帯電さｔしる。従って、本発
明では、第１の端子および第２の端子を、それぞれ正電
位とアース電位およびアース電位と正電位とに交互に切
り換えて接続することにより、各行選択線および列選択
線は、交互に正に帯電され、画素電極は正に帯電されな
いため、負に帯電されたスペーサは、高い確率で画素電
極より各行選択線および列選択線上に乗ることになる。Note that when the row selection line and the column selection line are positively charged at the same time, the thin film transistor becomes conductive, and as a result, the pixel is charged to the same potential as the wiring portion. Therefore, in the present invention, by alternately switching and connecting the first terminal and the second terminal to a positive potential and a ground potential, and a ground potential and a positive potential, respectively, each row selection line and column selection line can be connected alternately. Since the pixel electrode is not positively charged, the negatively charged spacer will more likely be placed on each row selection line and column selection line than the pixel electrode.
［発明の効果］
本発明によれば、正に帯電された各行選択線および列選
択線上に、負に帯電されたスペーサが引き寄せられるた
め、散布されたスペーサを、高い確率で、画素電極より
行選択線および列選択線上に乗せることができる。この
結果、画素電極上に乗るスペーサを極力少なくすること
ができるとともに、基板間のギャップムラをなくすこと
がて・きるため、画面品位の低下を抑えることができる
。[Effects of the Invention] According to the present invention, negatively charged spacers are attracted onto each positively charged row selection line and column selection line, so that the scattered spacers are more likely to be attached to a row than the pixel electrode. Can be placed on the selection line and column selection line. As a result, the number of spacers placed on the pixel electrodes can be minimized, and uneven gaps between substrates can be eliminated, so that deterioration in screen quality can be suppressed.
［実施例］
次に、本発明の液晶表示素子の製造方法を図面に示す一
実施例に基づき説明する。[Example] Next, a method for manufacturing a liquid crystal display element of the present invention will be described based on an example shown in the drawings.
第１図は画素電極および配線部を含む基板の断面図、第
２図は液晶表示素子の製造方法を示す説明図である。FIG. 1 is a sectional view of a substrate including a pixel electrode and a wiring section, and FIG. 2 is an explanatory diagram showing a method of manufacturing a liquid crystal display element.
本実施例の液晶表示素子は、３膜トランジスタ（図示し
ない）をスイッチ７ゲ素子とするもので、その薄膜トラ
ンジスタと画素電極１とで構成される多数の画素構成要
素をマトリクス状に配置したアクティブマトリクス基板
２ （本発明の一方の基板）牙備え、共通電極が形成さ
れた他方の基板（図示しない）との間に液晶層が形成さ
れている。The liquid crystal display element of this example uses a 3-film transistor (not shown) as a switch 7-gear element, and is an active matrix in which a large number of pixel components made up of the thin film transistor and the pixel electrode 1 are arranged in a matrix. A liquid crystal layer is formed between the substrate 2 (one substrate of the present invention) and the other substrate (not shown) on which a common electrode is formed.
基板２上には、各薄膜トランジスタ間を接続する複数の
行選択線３および列選択線４ （第２図参照）より成る
配線部が形成され、静電気による特性低下を防止するた
めに、各行選択＃！３および列選択線４がそれぞれ一括
して接続されている。A wiring section consisting of a plurality of row selection lines 3 and column selection lines 4 (see FIG. 2) is formed on the substrate 2 to connect each thin film transistor. ! 3 and column selection line 4 are connected together.
液晶層を挟む基板２と他方の基板とのギャップは、基板
２上に散布されたスペーサ５により一様に保たれている
。The gap between the substrate 2 and the other substrate sandwiching the liquid crystal layer is kept uniform by spacers 5 spread over the substrate 2.
このスペーサ５は、配線部の高さが基板２上の画素電極
１より高く設けられているため、配線部の上に置く必要
がある。また、画素電極１の上に置かれたスペーサ５は
、画面品位を悪くする要因となる。従って、スペーサ５
を基板２上に散布した際に、配線部の上に集中して乗せ
る必要がある。This spacer 5 needs to be placed above the wiring part because the height of the wiring part is higher than the pixel electrode 1 on the substrate 2. Furthermore, the spacer 5 placed on the pixel electrode 1 becomes a factor that deteriorates the screen quality. Therefore, spacer 5
When it is sprinkled on the substrate 2, it is necessary to concentrate it on the wiring parts.
そこで、本実施例では、高い確率で配線部の上にスペー
サ５を乗せることのできる以下の方法を採用しな。Therefore, in this embodiment, the following method is adopted which allows the spacer 5 to be placed on the wiring portion with high probability.
まず、基板２は、スペーサ５を散布するために、アース
された金属ケース６内に収容される。First, the substrate 2 is housed in a grounded metal case 6 in order to spread the spacers 5 thereon.
そして、−括して接続された各行選択線３および列選択
線４に、それぞれリード線７．８を接続し、各リード線
７．８を金属ケース６の外部に取り出して、各々第１の
端子９および第２の端子１０に接続する。Then, each lead wire 7.8 is connected to each row selection line 3 and column selection line 4 which are connected together, and each lead wire 7.8 is taken out from the metal case 6, and each lead wire 7.8 is connected to the first row selection line 3 and column selection line 4. Connected to terminal 9 and second terminal 10.
第１の端子９は、スイ・γチ１１により、電源１２の正
極に接続された第１のプラス接点１３と、アースされた
第１のアース接点１４との間で交互に切り換えて接続さ
れるように設けられ、第２の端子１０は、スイッチ１５
により、アースされた第２のアース接点１６と、電源１
２の正極に接続された第２のプラス接点１７との間で交
互に切り換えて接続されるように設けられている。The first terminal 9 is connected by switching alternately between a first positive contact 13 connected to the positive pole of the power supply 12 and a grounded first ground contact 14 by a switch 11. The second terminal 10 is connected to the switch 15.
, the second ground contact 16 which is grounded and the power supply 1
The second positive contact 17 connected to the second positive electrode is connected to the second positive contact 17 alternately.
この第１の端子９および第２の端子１０は、第１の端子
９が第１のプラス接点１３に接続された場合には、第２
の端子１０が第２のアース接点１６に接続され、第１の
端子９が第１のアース接点１４に接続された場合には、
第２の端子１０が第２のプラス接点１７に接続されるよ
うに切り換え操作が行われる。The first terminal 9 and the second terminal 10 are connected to each other when the first terminal 9 is connected to the first positive contact 13.
When the terminal 10 of is connected to the second earth contact 16 and the first terminal 9 is connected to the first earth contact 14,
A switching operation is performed such that the second terminal 10 is connected to the second positive contact 17.
つまり、この切り換え操作により、行選択線３と列選択
線４とが同時に正電位になることはなく、交互に電圧が
印加されることになる。従って、画素電極１の電位は常
にＯｔ位で、金属ケース６と同じアース電位となる。な
お５行選択線３と列選択線４とを同時に正に帯電させる
と、薄膜トランジスタが導通状態となり、その結果、画
素電極１も配線部と同じ電位に帯電されることになる。In other words, due to this switching operation, the row selection line 3 and the column selection line 4 do not have a positive potential at the same time, but voltages are applied alternately. Therefore, the potential of the pixel electrode 1 is always around Ot, which is the same ground potential as the metal case 6. Note that when the 5th row selection line 3 and the column selection line 4 are positively charged at the same time, the thin film transistor becomes conductive, and as a result, the pixel electrode 1 is also charged to the same potential as the wiring section.
上記の切り換え操作は、スペーサ５を散布する間５少な
くとも１回は切り換える必要があり、また、薄膜トラン
ジスタの動作速度より遅い速度で行う必要がある。そこ
で、〒導体リレーなどを使用して、鍜秒５〜３０回の速
度で切り換えるのが適当て′ある。The above switching operation needs to be performed at least once while dispersing the spacers 5, and needs to be performed at a speed slower than the operating speed of the thin film transistor. Therefore, it is appropriate to use a conductor relay or the like to switch at a speed of 5 to 30 times per second.
また、印加する電圧は、薄膜トランジスタの耐圧より低
い値で、一般には２０Ｖぐらいが良い。Further, the voltage to be applied is a value lower than the withstand voltage of the thin film transistor, and is generally about 20V.
上記の切り換え操作を行いながら、負に帯電したスペー
サ５を基板２上に散布することにより、正に帯電した配
線部と負に帯電したスペーサ５とが電気的に引き合うた
め、散布されたスペーサ５は、配線部上に集中して乗る
ことになる。つまり、上記の切り換え操作を行うことに
より、画素電極１はアース電位であり、配線部のみ正に
帯電するため、散布されたスペーサ５を、高い確率で、
画素電極１上より配線部１の方に乗せることができる。By scattering negatively charged spacers 5 on the substrate 2 while performing the above switching operation, the positively charged wiring section and the negatively charged spacers 5 are electrically attracted to each other, so that the scattered spacers 5 will be concentrated on the wiring section. In other words, by performing the above switching operation, the pixel electrode 1 is at ground potential and only the wiring portion is positively charged, so that the scattered spacers 5 can be
It can be placed on the wiring part 1 rather than on the pixel electrode 1.
このような方法により、基板間（基板２と他方の基板と
の間）のギヤツブを正確に制御して、基板間のギャップ
ムラをなくすとともに、画素電極１上に乗るスペーサ５
を極力少なくすることができるため、画面品位の低下を
抑えることができる。By such a method, the gear between the substrates (between the substrate 2 and the other substrate) can be accurately controlled to eliminate uneven gaps between the substrates, and the spacer 5 placed on the pixel electrode 1 can be accurately controlled.
Since it is possible to reduce as much as possible, deterioration in screen quality can be suppressed.
第１図は画素電極および配線部を含む基板の断面図、第
２図は液晶表示素子の製造方法を示す説明図である。
図中
１・・・画素電極
２・・アクティブマトリクス基板（一方の基板）３・・
・行選択線 ４・・列選択線
５・・・スペーサ ９・・・第１の端子１０・・・第
２の端子FIG. 1 is a sectional view of a substrate including a pixel electrode and a wiring section, and FIG. 2 is an explanatory diagram showing a method of manufacturing a liquid crystal display element. In the figure 1... Pixel electrode 2... Active matrix substrate (one substrate) 3...
- Row selection line 4... Column selection line 5... Spacer 9... First terminal 10... Second terminal
Claims (1)
成要素が多数マトリクス状に配置されて、前記各薄膜ト
ランジスタを接続する複数の行選択線および列選択線が
形成された一方の基板と、共通電極が形成された他方の
基板とを備え、前記一方の基板上に散布されたスペーサ
を介して対面する前記一方の基板と前記他方の基板との
間に液晶層が設けられた液晶表示素子において、前記複
数の行選択線が一括して接続された第１の端子、および
前記複数の列選択線が一括して接続された第２の端子を
設け、 前記第１の端子および前記第２の端子を、それぞれ正電
位とアース電位およびアース電位と正電位とに、前記薄
膜トランジスタの動作速度より遅い速度で交互に切り換
え接続して前記複数の行選択線および列選択線を交互に
正に帯電させながら、負に帯電させた前記スペーサを前
記一方の基板上に散布することにより、正に帯電した前
記複数の行選択線および列選択線上に、負に帯電した前
記スペーサを乗せることを特徴とする液晶表示素子の製
造方法。[Scope of Claims] 1) A plurality of pixel components each consisting of a pixel electrode and a thin film transistor are arranged in a matrix, and a plurality of row selection lines and column selection lines are formed to connect each of the thin film transistors. A liquid crystal layer is provided between the one substrate and the other substrate facing each other with spacers dispersed on the one substrate. In the liquid crystal display element, a first terminal to which the plurality of row selection lines are collectively connected and a second terminal to which the plurality of column selection lines are collectively connected are provided, the first terminal and The plurality of row selection lines and column selection lines are alternately connected by alternately switching and connecting the second terminals to a positive potential and a ground potential, and a ground potential and a positive potential, respectively, at a speed slower than an operating speed of the thin film transistor. Placing the negatively charged spacer on the plurality of positively charged row selection lines and column selection lines by scattering the negatively charged spacer on the one substrate while being positively charged. A method for manufacturing a liquid crystal display element characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14916790A JPH0442126A (en) | 1990-06-07 | 1990-06-07 | Production of liquid crystal display element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14916790A JPH0442126A (en) | 1990-06-07 | 1990-06-07 | Production of liquid crystal display element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442126A true JPH0442126A (en) | 1992-02-12 |
Family
ID=15469262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14916790A Pending JPH0442126A (en) | 1990-06-07 | 1990-06-07 | Production of liquid crystal display element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442126A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577373B1 (en) | 1997-06-13 | 2003-06-10 | Sekisui Chemical Co., Ltd. | Liquid crystal display and method of manufacturing the same |
| US7223817B2 (en) | 1998-09-02 | 2007-05-29 | Kaneka Corporation | Polymer, processes for producing polymer and composition |
-
1990
- 1990-06-07 JP JP14916790A patent/JPH0442126A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6577373B1 (en) | 1997-06-13 | 2003-06-10 | Sekisui Chemical Co., Ltd. | Liquid crystal display and method of manufacturing the same |
| US7223817B2 (en) | 1998-09-02 | 2007-05-29 | Kaneka Corporation | Polymer, processes for producing polymer and composition |
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