JPH0441524B2 - - Google Patents
Info
- Publication number
- JPH0441524B2 JPH0441524B2 JP57184496A JP18449682A JPH0441524B2 JP H0441524 B2 JPH0441524 B2 JP H0441524B2 JP 57184496 A JP57184496 A JP 57184496A JP 18449682 A JP18449682 A JP 18449682A JP H0441524 B2 JPH0441524 B2 JP H0441524B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- phase shifter
- absolute value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 7
- 230000005236 sound signal Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/18—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by means of synchronous gating arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Networks Using Active Elements (AREA)
- Circuits Of Receivers In General (AREA)
- Television Receiver Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、FM受信機におけるFM検波器、特
にクオードラチヤ検波器に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM detector in an FM receiver, and particularly to a quadrature detector.
クオードラチヤ検波器は、第１図に示すよう
に、FM中間周波信号と、周波数が変ると入力の
位相に対して出力の位相が変化する移相器１を通
つた信号との掛算を乗算器２で行い、ローパスフ
イルタ３で中間周波数（10.7MHz）以上の周波数
成分を減衰させてオーデイオ信号を取り出すよう
にしたもので、そのリニアリテイは移相器１の位
相特性で決まる。ところで乗算器２は一般にダブ
ルバランス型差動増幅器により構成され、外付け
回路が移相器１のみでよいので、この検波器は
IC化するのに適する。 As shown in Figure 1, the quadrature detector uses a multiplier 2 to multiply an FM intermediate frequency signal by a signal passed through a phase shifter 1 whose output phase changes with respect to the input phase when the frequency changes. The low-pass filter 3 attenuates frequency components above the intermediate frequency (10.7 MHz) to extract the audio signal, and its linearity is determined by the phase characteristics of the phase shifter 1. By the way, the multiplier 2 is generally composed of a double-balanced differential amplifier, and the only external circuit required is the phase shifter 1, so this detector
Suitable for IC.
第２図は、このようなクオードラチヤ検波器の
従来の具体的回路例を示し、移相器１の入力側に
は、トランジスタQ1〜Q3、抵抗R1及びR2、コン
デンサC1からなる、移相器１を駆動するための
差動アンプ４が接続されている。移相器１はイン
ダクタンスコイルL1及びL2、抵抗R3、コンデン
サC2からなり、R3，C2，L2は簡単な単同調回路
を構成している。この移相器１は、差動アンプ４
を含めて第３図に示すような等価回路で表わさ
れ、第４図に示すように、入力への信号の中心周
波数0において出力の信号に90゜の移相が生じ、
0から外れることによつて移相量が変化するよう
になつている。 FIG. 2 shows a conventional specific circuit example of such a quadrature detector. The input side of the phase shifter 1 consists of transistors Q 1 to Q 3 , resistors R 1 and R 2 , and capacitor C 1. , a differential amplifier 4 for driving the phase shifter 1 is connected. The phase shifter 1 consists of inductance coils L 1 and L 2 , a resistor R 3 , and a capacitor C 2 , and R 3 , C 2 , and L 2 constitute a simple single-tuned circuit. This phase shifter 1 includes a differential amplifier 4
It is represented by an equivalent circuit as shown in Figure 3 including
The amount of phase shift changes as the value deviates from 0 .
移相器１の出力信号とIF信号が入力される乗
算器２としてのダブルバランス型差動増幅器は、
トランジスタQ4〜Q10、抵抗R4〜R7、定電圧源
V81，V82からなり、元のIF信号と移相器１を通
過した信号を掛算し、そのビート成分から復調さ
れたオーデイオ信号を得る。そしてこの乗算器２
の出力には、オーデイオ信号の増幅のため、オペ
アンプＡ、抵抗R8，R9からなるアンプ５が接続
されている。 A double-balanced differential amplifier as a multiplier 2 to which the output signal of the phase shifter 1 and the IF signal are input is:
Transistors Q4 to Q10 , resistors R4 to R7 , constant voltage source
The original IF signal is multiplied by the signal passed through the phase shifter 1 , and a demodulated audio signal is obtained from the beat component. And this multiplier 2
An amplifier 5 consisting of an operational amplifier A and resistors R 8 and R 9 is connected to the output of the amplifier 5 for amplifying the audio signal.
なお、第２図では、アンプ５の出力側に接続さ
れうるローパスフイルタが省略されている。 Note that in FIG. 2, a low-pass filter that may be connected to the output side of the amplifier 5 is omitted.
ところが、第２図に示すように、移相量１とし
て、インダクタンスコイルL1と単同調回路（R3，
C2，L2）を用いたクオードラチヤ検波器では、
第５図に示すように検波出力の直線範囲が狭く、
また歪特性も良くないという欠点があつた。この
欠点を解消するには、移相器を複同調にすればよ
いが、このようにすると調整が複雑になるという
別の問題が生じるようになる。 However, as shown in FIG .
In the quadrature detector using C 2 , L 2 ),
As shown in Figure 5, the linear range of the detection output is narrow.
Another drawback was that the distortion characteristics were not good. This drawback can be overcome by making the phase shifter double-tuned, but this creates another problem in that the adjustment becomes complicated.
本発明は上述した従来の問題点を解消するため
になされたもので、その目的とするところは、移
相器として調整の簡単な単同調回路を用いたもの
において、その歪特性を改善したクオードラチヤ
検波器を提供することにある。 The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to improve the distortion characteristics of a phase shifter using a single-tuned circuit that is easy to adjust. The purpose is to provide a wave detector.
以下本発明を第６図以降を参照しながら説明す
る。 The present invention will be explained below with reference to FIG. 6 and subsequent figures.
第６図は本発明の一実施例を示す回路図で、第
２図と同等の部分には同一符号を付してある。 FIG. 6 is a circuit diagram showing an embodiment of the present invention, in which the same parts as in FIG. 2 are given the same reference numerals.
図において、１０及び１１は本発明により付加
された絶対値回路及び電流加算回路である。絶対
値回路１０は、オペアンプA2，A3、抵抗R12〜
R17、ダイオードD2，D3からなり、オペアンプA2
などによつて直線検波回路が、オペアンプA3な
どによつて加算回路がそれぞれ構成されていて、
入力信号の極性に係わらず常に正の出力電圧を出
力するように働く。すなわち、入力電圧とオペア
ンプA2の出力との加算したものが、後段のオペ
アンプA3の反転入力端子に加えられてオペアン
プA3の出力に入力電圧の絶対値に応じた信号を
出力する。 In the figure, numerals 10 and 11 are an absolute value circuit and a current addition circuit added according to the present invention. The absolute value circuit 10 includes operational amplifiers A 2 , A 3 and resistors R 12 .
Consisting of R 17 , diodes D 2 and D 3 , and operational amplifier A 2
A linear detection circuit is constructed by such as, and an adder circuit is constructed by operational amplifier A3 .
It always works to output a positive output voltage regardless of the polarity of the input signal. That is, the sum of the input voltage and the output of operational amplifier A2 is applied to the inverting input terminal of operational amplifier A3 at the subsequent stage, and a signal corresponding to the absolute value of the input voltage is output to the output of operational amplifier A3 .
このような絶対値回路１０の入力には、アンプ
５の出力が接続されてFM検波により得られる
FM検波出力信号が入力されており、その出力に
得られるFM検波出力信号の絶対値に応じた信号
が電流加算回路１１に印加される。 The output of the amplifier 5 is connected to the input of such an absolute value circuit 10, and the output is obtained by FM detection.
An FM detection output signal is input, and a signal corresponding to the absolute value of the FM detection output signal obtained as the output is applied to the current addition circuit 11.
電流加算回路１１は、トランジスタQ11、抵抗
R10，R11、ダイオードD1からなるカレントミラ
ー回路によつて構成されていて、その入力に加え
られる絶対値回路１０からの信号に応じた電流が
トランジスタQ11のコレクタに流され、この電流
がダブルバランス型増幅器２の定電流源の電流に
加算される。 The current adding circuit 11 includes a transistor Q 11 and a resistor.
It is composed of a current mirror circuit consisting of R 10 , R 11 and a diode D 1 , and a current corresponding to the signal from the absolute value circuit 10 applied to its input is passed through the collector of the transistor Q 11 . is added to the current of the constant current source of the double-balanced amplifier 2.
以上のような構成により、今FM検波出力（オ
ーデイオ）信号の振幅が正又は負に大きく振れる
と、これに応じて絶対値回路１０の出力信号が大
きくなつて電流加算回路１１に流れる電流が増大
されるため、ダブルバランス型増幅器２の電流源
の電流が大きくなり、この結果ダブルバランス型
増幅器２の利得が増大されるようになる。このた
め、IF信号の周波数が中心周波数0から＋又は−
側に変化したとき、これに応じてダブルバランス
型増幅器２の利得が上げられ、検波出力レベルの
増大が計られることになる。 With the above configuration, when the amplitude of the FM detection output (audio) signal swings significantly in the positive or negative direction, the output signal of the absolute value circuit 10 increases accordingly, and the current flowing into the current addition circuit 11 increases. Therefore, the current of the current source of the double-balanced amplifier 2 increases, and as a result, the gain of the double-balanced amplifier 2 increases. Therefore, the frequency of the IF signal is + or - from the center frequency 0 .
When the signal changes to the side, the gain of the double-balanced amplifier 2 is increased accordingly, and the detection output level is increased.
このことによつて、第７図に示すように、検波
出力特性が従来に比べ改善され、その歪特性は歪
の絶対値が良く、かつその良好な範囲が拡大され
るようになる。 As a result, as shown in FIG. 7, the detection output characteristic is improved compared to the conventional one, and the distortion characteristic has a good absolute value of distortion and a good range is expanded.
なお、第６図中の絶対値回路及び電流加算回路
は図示の具体的回路以外の回路構成であつてもよ
く、また絶対値回路のリニアリテイはそれ程良い
ものでなくてもよい。例えば電流加算回路は、ト
ランジスタQ10のベースに抵抗を介して直接接続
することも可能である。しかし、この場合は、そ
の抵抗値の設定には注意を要する。 Note that the absolute value circuit and the current addition circuit in FIG. 6 may have a circuit configuration other than the specific circuit shown, and the linearity of the absolute value circuit may not be so good. For example, the current addition circuit can also be directly connected to the base of transistor Q10 via a resistor. However, in this case, care must be taken in setting the resistance value.
第８図は他の実施例を示すブロツク図で、FM
検波出力に電圧制御増幅器VCAを接続し、その
ゲインをFM検波出力の絶対値で制御するように
しても、第６図の場合と同様の歪改善効果が得ら
れる。なお、この場合、後段へのFM検波出力は
電圧制御増幅器VCAの出力に得られる。 FIG. 8 is a block diagram showing another embodiment, in which the FM
Even if a voltage control amplifier VCA is connected to the detection output and its gain is controlled by the absolute value of the FM detection output, the same distortion improvement effect as in the case of FIG. 6 can be obtained. In this case, the FM detection output to the subsequent stage is obtained as the output of the voltage control amplifier VCA.
以上のように、本発明によれば、乗算器の出力
に得られるFM検波出力の絶対値に応じた信号に
応じて乗算器の利得を制御しているため、調整が
簡単なように移相器に単同調回路を用いたもので
あつても、歪特性の良好なものを得ることができ
る。 As described above, according to the present invention, the gain of the multiplier is controlled according to the signal corresponding to the absolute value of the FM detection output obtained at the output of the multiplier, so that the phase shift is performed for easy adjustment. Even if a single tuning circuit is used in the device, good distortion characteristics can be obtained.
第１図はクオードラチヤ検波器の一般的な構成
を示すブロツク図、第２図は従来のクオードラチ
ヤ検波器の回路例を示す回路図、第３図は第１図
中の移相器の等価回路図、第４図は第３図に示す
移相器の入出力特性を示すグラフ、第５図は第２
図に示す回路の欠点を説明するためのグラフ、第
６図は本発明の一実施例を示す回路図、第７図は
第６図に示す回路の特性を従来と比較して示すグ
ラフ、第８図は本発明の他の実施例を示すブロツ
ク図である。
１……移相器、２……乗算器、１０……絶対値
回路、１１……電流加算回路。
Figure 1 is a block diagram showing the general configuration of a quadrature detector, Figure 2 is a circuit diagram showing a circuit example of a conventional quadrature detector, and Figure 3 is an equivalent circuit diagram of the phase shifter in Figure 1. , Figure 4 is a graph showing the input/output characteristics of the phase shifter shown in Figure 3, and Figure 5 is a graph showing the input/output characteristics of the phase shifter shown in Figure 3.
6 is a circuit diagram showing an embodiment of the present invention; FIG. 7 is a graph showing the characteristics of the circuit shown in FIG. 6 in comparison with the conventional circuit; FIG. 8 is a block diagram showing another embodiment of the present invention. 1... Phase shifter, 2... Multiplier, 10... Absolute value circuit, 11... Current addition circuit.
Claims (1)
FM中間周波信号と元のFM中間周波信号とを乗
算器に加え、その出力にFM検波出力を得るよう
にしたクオードラチヤ検波器であつて、前記FM
検波出力の絶対値に応じた応号を得、この信号に
より前記乗算器の利得を制御するようになしたこ
とを特徴とするクオードラチヤ検波器。1 Obtained at the output of a phase shifter with a single tuned circuit
A quadrature detector which adds an FM intermediate frequency signal and an original FM intermediate frequency signal to a multiplier to obtain an FM detection output as its output, the FM
A quadrature detector characterized in that a signal corresponding to the absolute value of the detection output is obtained, and the gain of the multiplier is controlled by this signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18449682A JPS5974710A (en) | 1982-10-22 | 1982-10-22 | Quadrature detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18449682A JPS5974710A (en) | 1982-10-22 | 1982-10-22 | Quadrature detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5974710A JPS5974710A (en) | 1984-04-27 |
| JPH0441524B2 true JPH0441524B2 (en) | 1992-07-08 |
Family
ID=16154195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18449682A Granted JPS5974710A (en) | 1982-10-22 | 1982-10-22 | Quadrature detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5974710A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6070804A (en) * | 1983-09-28 | 1985-04-22 | Hitachi Ltd | Fm demodulation circuit |
| GB8414452D0 (en) * | 1984-06-06 | 1984-07-11 | Motorola Inc | Automatic gain control circuit |
| JPS6133002A (en) * | 1984-07-25 | 1986-02-15 | Mitsubishi Electric Corp | Multiplier |
| US4926132A (en) * | 1989-08-28 | 1990-05-15 | Motorola Inc. | FM detector with reduced distortion |
| JP2507681B2 (en) * | 1990-07-10 | 1996-06-12 | 株式会社東芝 | FM demodulation circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6241442Y2 (en) * | 1979-02-15 | 1987-10-23 |
-
1982
- 1982-10-22 JP JP18449682A patent/JPS5974710A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5974710A (en) | 1984-04-27 |
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