JPH04370930A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04370930A JPH04370930A JP14890291A JP14890291A JPH04370930A JP H04370930 A JPH04370930 A JP H04370930A JP 14890291 A JP14890291 A JP 14890291A JP 14890291 A JP14890291 A JP 14890291A JP H04370930 A JPH04370930 A JP H04370930A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- sulfur
- layer
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 49
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 28
- 239000011593 sulfur Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 150000001875 compounds Chemical class 0.000 claims abstract description 24
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052711 selenium Inorganic materials 0.000 claims abstract description 12
- 239000011669 selenium Substances 0.000 claims abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 14
- 239000012212 insulator Substances 0.000 abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 125000004434 sulfur atom Chemical group 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 231100000331 toxic Toxicity 0.000 description 2
- 230000002588 toxic effect Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- -1 GaAs compound Chemical class 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- UYJXRRSPUVSSMN-UHFFFAOYSA-P ammonium sulfide Chemical compound [NH4+].[NH4+].[S-2] UYJXRRSPUVSSMN-UHFFFAOYSA-P 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000002526 synchrotron radiation photoelectron spectroscopy Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、化合物半導体基板上に
電子デバイスおよび光デバイス等の半導体装置を製造す
る方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices such as electronic devices and optical devices on a compound semiconductor substrate.
【０００２】0002
【従来の技術】従来、例えばＧａＡｓ等の化合物半導体
基板上に半導体装置を形成する場合、その製造工程にお
いて、金属、絶縁物、半導体等の薄層を形成する前に、
清浄かつ安定な化合物半導体基板表面を得ることが困難
であった。2. Description of the Related Art Conventionally, when forming a semiconductor device on a compound semiconductor substrate such as GaAs, in the manufacturing process, before forming a thin layer of metal, insulator, semiconductor, etc.
It has been difficult to obtain a clean and stable compound semiconductor substrate surface.
【０００３】0003
【発明が解決しようとする課題】このため、このような
充分に制御されていない化合物半導体基板表面上に形成
した半導体装置では、（１）ショットキー障壁の高さが
金属の種類に強く依存しないため、デバイス設計上の自
由度が少ない、（２）良好なＭＩＳ（メタル インシュ
レータ セミコンダクタ（Ｍｅｔａｌ Ｉｎｓｕｌａｔ
ｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ））デバイス特性を
示さない、（３）大出力での安定なレーザ発振動作を行
なわない等の問題があった。[Problems to be Solved by the Invention] Therefore, in a semiconductor device formed on the surface of such a compound semiconductor substrate that is not sufficiently controlled, (1) the height of the Schottky barrier does not strongly depend on the type of metal; (2) Good MIS (Metal Insulator Semiconductor)
(3) does not exhibit stable laser oscillation operation at high output.
【０００４】これは、化合物半導体基板表面の自然酸化
膜を完全に除去した上で、その表面を表面準位密度の少
ない状態に保つことが困難であったので、その表面上に
金属、絶縁物、半導体等の薄層を形成した場合、これら
の接合界面の界面準位密度を低減することが困難だった
からである。[0004] This is because it is difficult to completely remove the natural oxide film on the surface of a compound semiconductor substrate and then keep the surface state in a state with a low density of surface states. This is because, when a thin layer of semiconductor or the like is formed, it is difficult to reduce the interface state density at the junction interface.
【０００５】このような問題を解決するための一つの方
法として、予め自然酸化膜を除去した化合物半導体基板
表面上に約１原子層の硫黄層またはセレン層を形成して
安定化させ、その上に金属、絶縁物、半導体等の薄層を
形成することにより、界面準位密度の低い金属（上層）
／半導体（下層）、絶縁物／半導体、半導体／半導体界
面を実現する手法が本発明者等により提案されている。
具体的には、（ａ）例えば硫化アンモニウム溶液にウェ
ハ（基板）を浸すことにより、自然酸化膜を除去すると
同時に硫黄層を形成するウェット処理と、（ｂ）超高真
空中で砒素ビームを照射しつつウェハを加熱することに
より、ウェハ表面クリーニングを行なって自然酸化膜を
除去した後に電気化学セル等により生成した硫黄原子を
表面に吸着させるドライ処理に大別することができる。
一般には、ドライ処理の方が硫黄原子の厚さの均一性が
よく、基板の不純物汚染が少ない等の点で優れている。One method for solving these problems is to form and stabilize a sulfur or selenium layer of approximately one atomic layer on the surface of a compound semiconductor substrate from which the native oxide film has been removed, and then to stabilize the surface of the compound semiconductor substrate. By forming a thin layer of metal, insulator, semiconductor, etc. on the metal (upper layer) with low interface state density,
The present inventors have proposed methods for realizing interfaces such as /semiconductor (lower layer), insulator/semiconductor, and semiconductor/semiconductor interface. Specifically, (a) a wet process in which a wafer (substrate) is immersed in an ammonium sulfide solution to remove a natural oxide film and simultaneously form a sulfur layer, and (b) irradiation with an arsenic beam in an ultra-high vacuum. The dry process can be roughly divided into a dry process in which sulfur atoms generated by an electrochemical cell or the like are adsorbed onto the surface of the wafer after cleaning the wafer surface and removing a natural oxide film by heating the wafer while heating the wafer. In general, dry processing is superior in that it provides better uniformity in the thickness of sulfur atoms and less contamination of the substrate with impurities.
【０００６】しかし、従来のドライ処理では、予め基板
表面クリーニングにより自然酸化膜を除去する必要があ
るので、工程が増加するという問題があった。また、従
来のクリーニング工程では、基板中の砒素の抜け（蒸発
）を防ぐため、砒素雰囲気中で基板温度を上げる必要が
あるので、有毒な砒素を含む原料を用いなければならず
、安全面で問題があり、さらに砒素の供給手段が必要な
ので、製造装置が複雑になるという問題があった。However, in the conventional dry processing, since it is necessary to remove the natural oxide film by cleaning the substrate surface in advance, there is a problem that the number of steps increases. Furthermore, in the conventional cleaning process, it is necessary to raise the temperature of the substrate in an arsenic atmosphere in order to prevent arsenic from escaping (evaporating) from the substrate, which necessitates the use of raw materials containing toxic arsenic, which poses safety concerns. Furthermore, since a means for supplying arsenic is required, the production equipment becomes complicated.
【０００７】本発明の目的は、上記の課題を解決し、工
程が簡単で、安全で、製造装置も簡単で、清浄かつ安定
な化合物半導体基板表面を得ることができ、その結果、
高性能で信頼性の高い半導体装置を実現することができ
る半導体装置の製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems, to obtain a clean and stable surface of a compound semiconductor substrate with a simple and safe manufacturing process, and as a result,
An object of the present invention is to provide a method for manufacturing a semiconductor device that can realize a high-performance and highly reliable semiconductor device.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の製造方法は、化合物半導体
基板（絶縁物等の他の基板上に形成した化合物半導体層
を含む）上に半導体装置を製造する方法において、上記
基板上へ金属層、絶縁物層もしくは半導体層またはこれ
らの化合物層等、種々の所定の層を形成する前に、硫黄
、セレンの一方を含む（両方含んでいてもよい）雰囲気
中で上記基板の熱処理を行なうことを特徴とする。[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention is provided on a compound semiconductor substrate (including a compound semiconductor layer formed on another substrate such as an insulator). In a method for manufacturing a semiconductor device, before forming various predetermined layers such as a metal layer, an insulating layer, a semiconductor layer, or a compound layer thereof on the substrate, a method containing one of sulfur and selenium (but not both) is used. The method is characterized in that the substrate is heat-treated in an atmosphere (which may be exposed).
【０００９】[0009]
【作用】本発明では、硫黄またはセレンを含む雰囲気中
で熱処理を行なうことにより、化合物半導体基板表面の
自然酸化膜を除去した後、硫黄またはセレン層を形成し
、これにより化合物半導体の構成元素の蒸発を防止し、
従来よりも単純かつ安全な工程、製造装置により高性能
、高信頼性の半導体装置を得ることができる。[Operation] In the present invention, a natural oxide film on the surface of a compound semiconductor substrate is removed by heat treatment in an atmosphere containing sulfur or selenium, and then a sulfur or selenium layer is formed, thereby removing the constituent elements of the compound semiconductor. prevent evaporation,
A high-performance, highly reliable semiconductor device can be obtained using simpler and safer processes and manufacturing equipment than conventional ones.
【００１０】0010
【実施例】図１は、本発明の半導体装置の製造方法を実
施するのに用いる製造装置の一構成例を示す断面図であ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing an example of the structure of a manufacturing apparatus used to carry out the method of manufacturing a semiconductor device of the present invention.
【００１１】本実施例は、化合物半導体基板をＧａＡｓ
、熱処理雰囲気を硫黄、ＧａＡｓ基板上に金属電極を形
成する場合の実施例である。In this example, the compound semiconductor substrate is made of GaAs.
This is an example in which the heat treatment atmosphere is sulfur and a metal electrode is formed on a GaAs substrate.
【００１２】１１は前処理室、１２は電極形成用スパッ
タ室、１３はＧａＡｓウェハ、１４は硫黄生成用電気化
学セル、１５は基板加熱ヒータ、１６は排気手段、１７
はゲートバルブである。11 is a pretreatment chamber, 12 is a sputtering chamber for electrode formation, 13 is a GaAs wafer, 14 is an electrochemical cell for sulfur generation, 15 is a heater for heating the substrate, 16 is an exhaust means, 17
is a gate valve.
【００１３】図２は、本実施例の処理における基板温度
Ｔと時間ｔとの関係、および電気化学セルの動作状態を
示すダイアグラムである。FIG. 2 is a diagram showing the relationship between substrate temperature T and time t and the operating state of the electrochemical cell in the process of this embodiment.
【００１４】図１に示すように、まず、前処理室１１に
ＧａＡｓウェハ１３を装填し、排気手段１６を用いて前
処理室１１内を高真空雰囲気にし（真空度：１×１０￣
９〜１×１０￣１０Ｔｏｒｒ）、電気化学セル１４を用
いて硫黄を発生させながら（真空度：１×１０￣７Ｔｏ
ｒｒ）、ＧａＡｓウェハ１３の温度（基板温度）を６０
０℃程度（図２のＴ０）まで昇温し、一定時間（図２の
ｔ０、例えば１０分間）保持する。次に、ＧａＡｓウェ
ハ１３の温度を一定温度（図２のＴ１、例えば３００℃
）まで下げた後、電気化学セル１４の電源を切って硫黄
の供給を中止し、さらに一定時間（ｔ１、例えば１０分
間）保持する。その後、ＧａＡｓウェハ１３を徐々に冷
却して室温にまで下げた後、隣のスパッタ室１２にＧａ
Ａｓウェハ１３を移して例えばＷＳｉＸ等の電極膜の形
成を行なう。本工程は、例えばＧａＡｓＭＥＳＦＥＴの
ゲート電極の形成工程に適用できる。As shown in FIG. 1, first, a GaAs wafer 13 is loaded into the pretreatment chamber 11, and the interior of the pretreatment chamber 11 is made into a high vacuum atmosphere using the exhaust means 16 (degree of vacuum: 1×10°).
9 to 1×10￣10 Torr) while generating sulfur using the electrochemical cell 14 (degree of vacuum: 1×10￣7 Torr).
rr), the temperature of the GaAs wafer 13 (substrate temperature) was set to 60
The temperature is raised to about 0° C. (T0 in FIG. 2) and maintained for a certain period of time (t0 in FIG. 2, for example, 10 minutes). Next, the temperature of the GaAs wafer 13 is set to a constant temperature (T1 in FIG. 2, for example, 300°C).
), the electrochemical cell 14 is turned off, the supply of sulfur is stopped, and the temperature is further maintained for a certain period of time (t1, for example, 10 minutes). After that, the GaAs wafer 13 is gradually cooled down to room temperature, and then the GaAs wafer 13 is placed in the adjacent sputtering chamber 12.
The As wafer 13 is transferred and an electrode film, such as WSiX, is formed thereon. This process can be applied, for example, to the process of forming a gate electrode of a GaAs MESFET.
【００１５】このように本実施例によれば、硫黄雰囲気
中でＧａＡｓ化合物半導体基板の熱処理を行なうため、
基板表面の自然酸化膜のみが除去された後、基板表面を
約１原子層の硫黄原子が覆うので、該基板の構成元素で
ある砒素（あるいはＩｎＰ基板のリン等）等が基板表面
から蒸発、脱離することを防止すると共に、表面が安定
化するという作用がある。なお、このような基板表面の
硫黄層の存在は、放射光光電子分光解析により確認した
。As described above, according to this embodiment, since the GaAs compound semiconductor substrate is heat-treated in a sulfur atmosphere,
After only the natural oxide film on the substrate surface is removed, the substrate surface is covered with approximately one atomic layer of sulfur atoms, so that the constituent elements of the substrate, such as arsenic (or phosphorus in InP substrates, etc.), evaporate from the substrate surface. It has the effect of preventing desorption and stabilizing the surface. The presence of such a sulfur layer on the surface of the substrate was confirmed by synchrotron radiation photoelectron spectroscopy analysis.
【００１６】なお、硫黄の圧力、熱処理時間を増加する
と、基板表面の硫黄層の厚さは、わずかに増える方向に
変化するが、元来硫黄の蒸気圧は高いため、最終的に安
定な硫黄層厚は１〜２原子層程度であり、大幅な層厚増
加には至らない。したがって、このような条件下におい
ても本発明は有効である。Note that when the sulfur pressure and heat treatment time are increased, the thickness of the sulfur layer on the substrate surface changes slightly, but since the vapor pressure of sulfur is originally high, stable sulfur eventually becomes The layer thickness is about 1 to 2 atomic layers, and the layer thickness does not increase significantly. Therefore, the present invention is effective even under such conditions.
【００１７】また、従来砒素雰囲気で行なっていた基板
表面のクリーニング工程を硫黄雰囲気中で行なうことに
より、クリーニングと基板表面安定化処理とを１つの工
程で行なうことができるので、処理工程を簡単化するこ
とができると共に、有毒な砒素を用いないので、より安
全に半導体装置を製造することができる。さらに、砒素
供給手段が不要なので、製造装置も単純化することがで
きる。Furthermore, by performing the substrate surface cleaning process in a sulfur atmosphere, which was conventionally performed in an arsenic atmosphere, cleaning and substrate surface stabilization treatment can be performed in one process, simplifying the processing process. In addition, since toxic arsenic is not used, semiconductor devices can be manufactured more safely. Furthermore, since no arsenic supply means is required, the manufacturing equipment can also be simplified.
【００１８】さらに、保持温度Ｔ１を適当に設定するこ
とにより、例えば５００℃程度の高温処理では４×１、
３００℃程度の低温処理では２×１等の表面超構造が得
られ、極めて精密に制御された化合物半導体基板表面を
任意に形成することができる。Furthermore, by appropriately setting the holding temperature T1, for example, 4×1,
A surface superstructure of 2×1 or the like can be obtained by low-temperature treatment at about 300° C., and an extremely precisely controlled surface of a compound semiconductor substrate can be arbitrarily formed.
【００１９】なお、本実施例では、電気化学セルを用い
て硫黄を発生させたが、電気化学セルを用いないで、例
えばＨ２Ｓガス等の硫黄を含むガスを導入して処理して
もよく、この場合も上記実施例と同様の効果が得られた
。[0019] In this example, sulfur was generated using an electrochemical cell, but the treatment may be performed by introducing a gas containing sulfur such as H2S gas without using an electrochemical cell. In this case as well, the same effects as in the above example were obtained.
【００２０】また、本実施例では、硫黄雰囲気を用いた
が、セレン雰囲気を用いた場合、さらに硫黄およびセレ
ンの両方を含む雰囲気を用いた場合においても同様の効
果が得られた。Further, in this example, a sulfur atmosphere was used, but similar effects were obtained when a selenium atmosphere was used, and when an atmosphere containing both sulfur and selenium was used.
【００２１】また、本実施例では、化合物半導体基板と
してＧａＡｓを用いたが、ＡｌＧａＡｓ、ＩｎＧａＡｓ
、ＩｎＰ系等の化合物半導体を用いる場合も、同様の効
果が得られ、本発明は有効である。Furthermore, although GaAs was used as the compound semiconductor substrate in this example, AlGaAs, InGaAs
, InP-based compound semiconductors and the like can also provide similar effects and the present invention is effective.
【００２２】また、本実施例では、ＭＥＳＦＥＴ等の金
属／半導体接合の形成工程への適用例を示したが、これ
以外に、ＭＩＳＦＥＴの絶縁物（例えばＳｉＯ２、Ｃａ
Ｆ２等）／ＧａＡｓ半導体接合形成工程、レーザ・ダイ
オード等の光デバイスの半導体／半導体接合、および絶
縁物／半導体接合形成工程等にも適用することができ、
それらの場合も同様の効果が得られ、本発明は有効であ
る。また、本発明をＭＩＳＦＥＴの絶縁物／ＧａＡｓ界
面に応用した場合、界面準位密度を大幅に低減できるた
め、従来実現が困難とされていた良好な特性を有するＭ
ＩＳＦＥＴを実現できる。Further, in this example, an example of application to the formation process of a metal/semiconductor junction such as a MESFET was shown, but in addition to this, it is also possible to
F2 etc.)/GaAs semiconductor junction formation process, semiconductor/semiconductor junction of optical devices such as laser diodes, insulator/semiconductor junction formation process, etc.
Similar effects can be obtained in those cases, and the present invention is effective. Furthermore, when the present invention is applied to the insulator/GaAs interface of a MISFET, the interface state density can be significantly reduced, so M
ISFET can be realized.
【００２３】また、上述のＭＥＳＦＥＴ、ＭＩＳＦＥＴ
、および光デバイス等を同一基板上に集積化した場合に
おいても同様の効果が得られ、本発明が有効であること
は言うまでもない。[0023] Furthermore, the above-mentioned MESFET, MISFET
, an optical device, etc. are integrated on the same substrate, similar effects can be obtained, and it goes without saying that the present invention is effective.
【００２４】また、本発明によれば、多様なしきい値お
よび障壁高さを有するＭＥＳＦＥＴ、ショットキー・ダ
イオード等を同一基板上に集積化でき、デバイス設計の
自由度を大幅に拡大することができる上、ＭＥＳＦＥＴ
のしきい値を制御するためのイオン注入工程の回数を減
らすことが可能となり、高性能なデバイスを容易に実現
できると同時に、従来にない新しい機能を有する半導体
装置を実現できる。Furthermore, according to the present invention, MESFETs, Schottky diodes, etc. having various threshold values and barrier heights can be integrated on the same substrate, and the degree of freedom in device design can be greatly expanded. Top, MESFET
It becomes possible to reduce the number of ion implantation steps for controlling the threshold value of , and it is possible to easily realize a high-performance device, and at the same time, it is possible to realize a semiconductor device having new functions not previously seen.
【００２５】さらに、本発明によれば、イオン注入およ
び活性化工程まで終了した段階で、活性層のキャリア濃
度分布をモニター用素子により把握し、そのデータに基
づいて所望のしきい値を実現する上での最適なショット
キー・ゲート金属をいくつかの材料の中から選択するこ
とにより、従来以上に精密にＭＥＳＦＥＴのしきい値を
制御することができるため、より高性能、高動作マージ
ンの半導体装置を容易に実現できる。Furthermore, according to the present invention, at the stage where the ion implantation and activation steps are completed, the carrier concentration distribution in the active layer is grasped by a monitoring element, and a desired threshold value is realized based on the data. By selecting the optimal Schottky gate metal from among several materials, it is possible to control the threshold of MESFET more precisely than before, resulting in semiconductors with higher performance and higher operating margins. The device can be easily realized.
【００２６】また、本発明をレーザ・ダイオード等の光
デバイスの半導体／半導体界面および絶縁物／半導体界
面等に応用した場合、安定に大出力動作を行なう高信頼
光デバイスを実現できる。この場合化合物半導体として
、ＧａＡｓ系のみでなく、ＩｎＰ系の混晶半導体および
ＺｎＳｅ系等に対しても同様の表面安定化効果が得られ
有効である。Furthermore, when the present invention is applied to the semiconductor/semiconductor interface, insulator/semiconductor interface, etc. of an optical device such as a laser diode, a highly reliable optical device that stably performs high output operation can be realized. In this case, the same surface stabilizing effect can be obtained and is effective not only for GaAs-based compound semiconductors but also for InP-based mixed crystal semiconductors, ZnSe-based, and the like.
【００２７】また、化合物半導体基板は絶縁物等の他の
基板上にエピタキシャル成長等により形成した化合物半
導体層の場合でもよい。さらに、半導体層や金属層を多
段に積層した場合における金属と半導体との界面、絶縁
物と半導体との界面、半導体と半導体との界面に硫黄層
またはセレン層を設けることも可能である。例えば、化
合物半導体基板上に硫黄層を形成し、その上に半導体層
をエピタキシャル成長により形成し、その上にセレン層
を形成し、その上に金属層を形成した構造等を形成して
もよい。Further, the compound semiconductor substrate may be a compound semiconductor layer formed by epitaxial growth or the like on another substrate such as an insulator. Furthermore, it is also possible to provide a sulfur layer or a selenium layer at the interface between a metal and a semiconductor, an interface between an insulator and a semiconductor, or an interface between a semiconductor and a semiconductor when semiconductor layers or metal layers are laminated in multiple stages. For example, a structure may be formed in which a sulfur layer is formed on a compound semiconductor substrate, a semiconductor layer is formed on it by epitaxial growth, a selenium layer is formed on it, and a metal layer is formed on it.
【００２８】[0028]
【発明の効果】以上説明したように、本発明の半導体装
置の製造方法によれば、従来よりも単純かつ安全な手法
により清浄かつ安定な化合物半導体基板表面上に約１原
子層の硫黄またはセレンの界面層を制御性良く形成する
ことができるため、安定な金属／半導体、絶縁物／半導
体、半導体／半導体界面を含む高性能でかつ信頼性の高
い半導体装置を容易に実現することができる。As explained above, according to the method for manufacturing a semiconductor device of the present invention, about one atomic layer of sulfur or selenium can be formed on the surface of a clean and stable compound semiconductor substrate using a simpler and safer method than before. Since the interface layer can be formed with good controllability, a high-performance and highly reliable semiconductor device including stable metal/semiconductor, insulator/semiconductor, and semiconductor/semiconductor interfaces can be easily realized.
【図１】本発明の半導体装置の製造方法を実施するのに
用いる製造装置の一構成例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of the configuration of a manufacturing apparatus used to carry out the method of manufacturing a semiconductor device of the present invention.
【図２】本発明の一実施例の処理における基板温度Ｔと
時間ｔとの関係、および電気化学セルの動作状態を示す
ダイアグラムである。FIG. 2 is a diagram showing the relationship between substrate temperature T and time t and the operating state of an electrochemical cell in a process according to an embodiment of the present invention.
１１…前処理室、１２…電極形成用スパッタ室、１３…
ＧａＡｓウェハ、１４…硫黄生成用電気化学セル、１５
…基板加熱ヒータ、１６…排気手段、１７…ゲートバル
ブ。11... Pretreatment chamber, 12... Sputtering chamber for electrode formation, 13...
GaAs wafer, 14... Electrochemical cell for sulfur production, 15
...Substrate heating heater, 16...Exhaust means, 17...Gate valve.
Claims (1)
る方法において、上記基板上へ所定の層を形成する前に
、硫黄、セレンの少なくとも一方を含む雰囲気中で上記
基板の熱処理を行なうことを特徴とする半導体装置の製
造方法。1. A method for manufacturing a semiconductor device on a compound semiconductor substrate, which includes heat-treating the substrate in an atmosphere containing at least one of sulfur and selenium before forming a predetermined layer on the substrate. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890291A JPH04370930A (en) | 1991-06-20 | 1991-06-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890291A JPH04370930A (en) | 1991-06-20 | 1991-06-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04370930A true JPH04370930A (en) | 1992-12-24 |
Family
ID=15463228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14890291A Pending JPH04370930A (en) | 1991-06-20 | 1991-06-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04370930A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207976B1 (en) | 1997-12-17 | 2001-03-27 | Fujitsu Limited | Semiconductor device with ohmic contacts on compound semiconductor and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04181731A (en) * | 1990-11-16 | 1992-06-29 | Hitachi Ltd | Method of processing surface of compound semiconductor crystal |
-
1991
- 1991-06-20 JP JP14890291A patent/JPH04370930A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04181731A (en) * | 1990-11-16 | 1992-06-29 | Hitachi Ltd | Method of processing surface of compound semiconductor crystal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207976B1 (en) | 1997-12-17 | 2001-03-27 | Fujitsu Limited | Semiconductor device with ohmic contacts on compound semiconductor and manufacture thereof |
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