JPH04369264A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04369264A
JPH04369264A JP3297138A JP29713891A JPH04369264A JP H04369264 A JPH04369264 A JP H04369264A JP 3297138 A JP3297138 A JP 3297138A JP 29713891 A JP29713891 A JP 29713891A JP H04369264 A JPH04369264 A JP H04369264A
Authority
JP
Japan
Prior art keywords
capacitor
film
sic
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3297138A
Other languages
Japanese (ja)
Inventor
Geun-Ha Jang
張　根夏
Okyu Ri
李　央九
Yusan Chin
陳　裕讚
Taikei Cho
張　泰奎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH04369264A publication Critical patent/JPH04369264A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: To provide a method for manufacturing a semiconductor device increasing capacitor capacitance of memory elements. CONSTITUTION: A method for manufacturing a semiconductor device comprises a step of forming an α-type silicon carbide layer 12 on a first conductive layer 10 used for a first electrode of a capacitor and a step for forming a second conductive layer 20 used for a second electrode of the capacitor on the α-type silicon carbide layer. By using SiC(α) being a high dielectric substance as a dielectric film of the capacitor, capacitance of the capacitor in a memory device can be increased. Further, it is not required to be formed thinner than the case where a substance having a low dielectric constant is used on the dielectric film, and it is possible to have a margin on the steps and contrive to increase yield of a more excellent element than in the prior art.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特にメモリ素子のキャパシタ容量を増加させう
る半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that can increase the capacitance of a memory element.

【０００２】0002

【従来の技術】近年、半導体装置製造技術の発達とメモ
リ素子の応用分野が拡張されていくにしたがって、大容
量のメモリ素子の開発が進まれているが、特に１個のメ
モリセルを１個のキャパシタと１個のトランジスタより
構成することにより高集積化に有利なＤＲＡＭ（Ｄｙｎ
ａｍｉｃ　Ｒａｎｄｏｍ　ＡｃｃｅｓｓＭｅｍｏｒｙ）
の目立つ発展がなされてきた。[Background Art] In recent years, with the development of semiconductor device manufacturing technology and the expansion of the application fields of memory devices, the development of large-capacity memory devices is progressing. DRAM (Dyn
amic Random AccessMemory)
Significant developments have been made.

【０００３】このＤＲＡＭの開発は３年に４倍の高集積
化を達成することになったが、現在ＤＲＡＭの集積度は
４ＭｂＤＲＡＭが量産段階に入り、１６Ｍｂは量産に向
かって速い速度で開発されつつあり、６４Ｍｂおよび２
５６Ｍｂは開発のための研究が活発に進んでいる。[0003] The development of this DRAM has resulted in a four-fold increase in the integration density in three years, but the current density of DRAM is that the 4Mb DRAM has entered the mass production stage, and the 16Mb DRAM is being developed at a rapid pace toward mass production. 64Mb and 2
Research for the development of 56Mb is actively progressing.

【０００４】この半導体メモリ装置は、情報の読み出し
と貯蔵のために大きい静電容量を有するべきであるが、
集積度が４倍増加するとき、チップ（ｃｈｉｐ）面積が
１．４倍の増加に止まることにより、相対的にメモリセ
ルの面積は１／３倍減少され、既存のキャパシタ構造を
もっては限定された面積内で十分に大きいセルキャパシ
タンスを確保することができない。This semiconductor memory device should have a large capacitance for reading and storing information, but
When the integration density increases by 4 times, the chip area only increases by 1.4 times, so the memory cell area is relatively reduced by 1/3 times, which is limited by the existing capacitor structure. A sufficiently large cell capacitance cannot be secured within the area.

【０００５】したがって、小さい面積でより大きいキャ
パシタンスを得るための方法の研究が要求されるが、こ
の方法は通常、次ぎの３種類に分かれる。すなわち、第
１は誘電体膜の厚さの減少、第２はキャパシタの有効面
積の増加、第３は誘電常数の大きい物質の使用である。[0005]Therefore, there is a need to research methods for obtaining larger capacitance in a smaller area, and these methods are generally divided into the following three types. The first is to reduce the thickness of the dielectric film, the second is to increase the effective area of the capacitor, and the third is to use a material with a large dielectric constant.

【０００６】この中で、第１の場合、誘電体膜の厚さが
１００オングストローム以下の場合ファウラーノードハ
イム（Ｆｏｗｌｅｒ−Ｎｏｒｄｈｅｉｍ）　電流により
使用が制限され、信頼性問題が深刻なので大容量メモリ
素子が適用しにくい。In the first case, when the thickness of the dielectric film is 100 angstroms or less, the use of large-capacity memory elements is limited due to Fowler-Nordheim current, and reliability problems are serious. Difficult to apply.

【０００７】第２の場合が今まで一番多くの開発がなさ
れた方法で、集積度の向上のためのメモリセル構造によ
り、従来のプレーナ（ｐｌａｎａｒ）型キャパシタセル
からスタック（ａｔａｃｋ）　型キャパシタセルとトレ
ンチ（ｔｒｅｎｃｈ）型キャセルの３次元的な構造が考
案され、４ＭｂＤＲＡＭに適用されているが、１６Ｍｂ
ＤＲＡＭを境としてその限界を露出させている。また、
スタック型キャパシタセルにおいては、トランジスタ上
に積層したキャパシタ構造のために激しい段差問題が生
じ、トレンチ型キャパシタセルにおいては、スケーリン
グダウン（ｓｃａｌｉｎｇ　ｄｏｗｎ）作業の進行によ
るトレンチ間洩れ電流問題が生じて６４ＭｂＤＲＡＭに
対応しにくくなった。The second case is the method that has been the most developed to date, and it is possible to change the memory cell structure from a conventional planar type capacitor cell to a stack type capacitor cell to improve the degree of integration. A three-dimensional trench-type cassell structure was devised and applied to 4Mb DRAM, but 16Mb
The limits of DRAM are exposed. Also,
In a stacked capacitor cell, a severe step problem occurs due to the capacitor structure stacked on a transistor, and in a trench type capacitor cell, a leakage current problem between trenches occurs due to the progress of scaling down work, resulting in a 64Mb DRAM. It became difficult to respond.

【０００８】したがって、この大容量ＤＲＡＭの問題点
を解決するための新たな構造のキャパシタとしてスタッ
ク−トレンチ併用型キャパシタ、フィン（ｆｉｎ）　構
造キャパシタ、ボックス（ｂｏｘ）　構造キャパシタお
よびスプレード（ｓｐｒｅａｄ）スタックキャパシタ等
が提案された。しかし、前述のようにストレージ電極の
構造を改善してキャパシタ容量を増加させようとする図
りはデザインルールの限界および複雑な工程上の問題点
等で、集積度がさらに増加する次世代デバイス開発に対
して制限を受けることになったし、この様な問題点を克
服する新たなキャパシタ構造に対する開発が要請された
。Therefore, new capacitor structures to solve the problems of large-capacity DRAMs include stack-trench combined capacitors, fin structure capacitors, box structure capacitors, and spread stack capacitors. Capacitors etc. were proposed. However, as mentioned above, attempts to increase capacitor capacitance by improving the structure of storage electrodes have limitations in design rules and problems in complicated processes, making it difficult to develop next-generation devices with ever-increasing integration density. However, there has been a need to develop a new capacitor structure that overcomes these problems.

【０００９】この要求に応じて、キャパシタ容量の増加
をストレージ電極の構造改善によらず、前記ストレージ
電極を形成する物質自体の特性を用いて、キャパシタ容
量を増加させる方法が提案されたが、この新たな方法は
日本電気株式会社で発表した”Ａ　Ｎｅｗ　Ｓｔａｃｋ
ｅｄ　Ｃａｐａｃｉｔｏｒ　Ｓｔｒｕｃｔｕｒｅ　Ｕｓ
ｉｎｇ　Ｈｅｍｉｓｐｈｅｒｉｃａｌ−Ｇｒａｉｎ（Ｈ
ＳＧ）Ｐｏｌｙ−Ｓｉｌｉｃｏｎ　Ｅｌｅｃｔｒｏｄｅ
ｓ”　（Ｈ．Ｗａｔａｎａｂｅ，Ｎ．Ａｏｔｏ，Ｓ．Ａ
ｄａｃｈｉ，Ｔ．Ｉｓｈｉｊｉｍａ，Ｅ．Ｉｋａｗａ，
　ａｎｄ　Ｋ．Ｔｅｒａｄａ，ＳＳＤＭ，１９９０，Ｐ
Ｐ．８７３　〜８７６）、あるいは、三菱電機株式会社
で発表した”Ｆａｂｒｉｃａｔｉｏｎ　ｏｆ　Ｓｔｏｒ
ａｒｅ　Ｃａｐａｃｉｔａｎｃｅ−Ｅｎｈａｎｃｅｄ　
Ｃａｐａｃｉｔｏｒｓ　ｗｉｔｈ　ａ　Ｒｏｕｇｈ　Ｅ
ｌｅｃｔｒｏｄｅ”（Ｙｏｓｈｉｏ　Ｈａｙａｓｈｉｄ
ｅ，Ｈｉｒｏｓｈｉ　Ｍｉｙａｔａｋｅ，Ｊｕｎｉｃｈ
ｉ　Ｍｉｔｓｕｈａｓｈｉ，Ｍａｋｏｔｏ　Ｈｉｒａｙ
ａｍａ，Ｔａｋａｓｈｉ　Ｈｉｇａｋｉ　ａｎｄ　Ｈａ
ｒｕｈｉｋｏ　Ａｂｅ，ＳＳＤＭ，ＰＰ．８６９〜８７
２）を通じて理解できる。前記二つの論文の報告による
キャパシタの製造方法においては、キャパシタの容量の
増加のためにストレージ電極の表面的増大を図り、この
表面的増大は前記ストレージ電極で使われる多結晶シリ
コン物質自体の起伏度（ｍｏｒｐｈｏｌｏｇｙ）を増大
させることにより得られる。すなわち、低圧化学気相成
長（Ｌｏｗ　Ｐｒｅｓｓｕｒｅ　ＣｈｅｍｉｃａｌＶａ
ｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ；ＬＰＣＶＤ）装置を用
いてストレージ電極で使用される多結晶シリコンを沈積
するとき、沈積温度が非晶質シリコンから多結晶シリコ
ンに変わる相変換温度（ｐｈａｓｅ　ｔｒａｎｓｉｔｉ
ｏｎ　ｔｅｍｐｅｒａｔｕｒｅ）で多結晶シリコンの表
面の起伏度が一番大幅に増加するという点に着眼した。 しかし、この場合、多結晶シリコンの沈積温度と圧力以
外にも多結晶シリコンの厚さが表面の形態に影響を与え
る主要因として作用するので、多様なキャパシタ構造に
適用できない問題点がある。In response to this demand, a method has been proposed in which the capacitor capacitance is increased by using the characteristics of the material forming the storage electrode itself, rather than by improving the structure of the storage electrode. The new method is “A New Stack” announced by NEC Corporation.
ed Capacitor Structure Us
ing Hemispherical-Grain (H
SG) Poly-Silicon Electrode
s” (H. Watanabe, N. Aoto, S.A.
dachi, T. Ishijima, E. Ikawa,
and K. Terada, SSDM, 1990, P
P. 873 to 876), or “Fabrication of Stor” announced by Mitsubishi Electric Corporation.
are Capacitance-Enhanced
Capacitors with a Rough E
Yoshio Hayashid
e, Hiroshi Miyatake, Junich
i Mitsuhashi, Makoto Hiray
ama, Takashi Higaki and Ha
ruhiko Abe, SSDM, PP. 869-87
It can be understood through 2). In the capacitor manufacturing method reported in the above two papers, the surface of the storage electrode is increased in order to increase the capacitance of the capacitor, and this surface increase is caused by the unevenness of the polycrystalline silicon material itself used in the storage electrode. (morphology). That is, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition)
When depositing polycrystalline silicon used in storage electrodes using a por deposition (LPCVD) device, the deposition temperature is a phase transition temperature at which the deposition temperature changes from amorphous silicon to polycrystalline silicon.
We focused on the fact that the degree of roughness of the surface of polycrystalline silicon increases most significantly under the conditions of temperature. However, in this case, in addition to the deposition temperature and pressure of the polycrystalline silicon, the thickness of the polycrystalline silicon acts as a main factor that affects the surface morphology, so there is a problem that it cannot be applied to various capacitor structures.

【００１０】また、ストレージ電極表面の凹凸に現れる
ＨＳＧ間の変曲点で電界集中が生じ、この電界集中によ
って誘電体膜の電気的特性および信頼性を低下させる問
題点が生ずる。[0010] Furthermore, electric field concentration occurs at the inflection points between the HSGs that appear on the uneven surface of the storage electrode, and this electric field concentration causes a problem of deteriorating the electrical characteristics and reliability of the dielectric film.

【００１１】[0011]

【発明が解決しようとする課題】したがって、本発明の
目的は、前述したような従来の技術の問題点を解決する
ために、高誘電物質を用いてキャパシタの容量が増加で
きるキャパシタの製造方法を提供することである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a capacitor in which the capacitance of the capacitor can be increased using a high dielectric material in order to solve the problems of the conventional technology as described above. It is to provide.

【００１２】0012

【課題を解決するための手段】前述した目的を達成する
ために、本発明によるキャパシタの製造方法は、キャパ
シタの第１電極で使われる第１導電層上にα型炭化ケイ
素層を形成する工程と、前記α型炭化ケイ素層上にキャ
パシタの第２電極で使われる第２導電層を形成する工程
よりなることを特徴とする。[Means for Solving the Problems] In order to achieve the above-mentioned object, a method for manufacturing a capacitor according to the present invention includes a step of forming an α-type silicon carbide layer on a first conductive layer used in a first electrode of a capacitor. and forming a second conductive layer used as a second electrode of a capacitor on the α-type silicon carbide layer.

【００１３】[0013]

【作用】本発明の製造方法は、キャパシタの誘電体膜と
して高誘電物質である炭化ケイ素（ＳｉＣ（α））を用
いることにより、メモリ装置においてキャパシタの容量
を増加させ得る。The manufacturing method of the present invention can increase the capacitance of a capacitor in a memory device by using silicon carbide (SiC(α)), which is a high dielectric material, as the dielectric film of the capacitor.

【００１４】[0014]

【実施例】以下、添付した図面に基づいて本発明を詳細
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

【００１５】α型炭化ケイ素ＳｉＣ（以下、ＳｉＣ（α
）と称する）は誘電率が１０．２程度あって、酸化膜よ
り２．６倍、窒化膜よりは１，３６倍程度優れる。 したがって、等しい厚さのＳｉＣ（α）誘電体膜を採択
すれば、酸化膜より２．６倍、窒化膜より１．３６倍キ
ャパシタを増大させうる。α-type silicon carbide SiC (hereinafter referred to as SiC (α
) has a dielectric constant of about 10.2, which is 2.6 times better than an oxide film and about 1.36 times better than a nitride film. Therefore, if a SiC(α) dielectric film of the same thickness is adopted, the capacitor can be increased by 2.6 times as compared with an oxide film and 1.36 times as compared with a nitride film.

【００１６】ＳｉＣ（α）膜を作る方法は、下の（１）
式の反応式を通じて得られる。[0016] The method for making the SiC (α) film is as follows (1)
It is obtained through the reaction equation of Eq.

【００１７】[0017]

【化１】４塩化ケイ素（ＳｉＣｌ４　）＋メタン（ＣＨ
４　）→ＳｉＣ（α）＋塩酸（ＨＣｌ）　　　（１）前
記（１）式の反応式を通じて得られたＳｉＣ（α）膜を
キャパシタの誘電体膜として用いるには、図１および図
２に示した通り、ＳｉＣ（α）膜のみを用いる方法およ
びＳｉＣ（α）膜とこのＳｉＣ（α）膜上に前記ＳｉＣ
（α）膜を強制酸化させ形成されたＳｉＣｘ　Ｏｙ　膜
を共に用いる方法がある。[Chemical formula 1] Silicon tetrachloride (SiCl4) + methane (CH
4) → SiC(α) + Hydrochloric acid (HCl) (1) In order to use the SiC(α) film obtained through the reaction formula (1) above as a dielectric film of a capacitor, the steps shown in FIGS. As described above, the method using only the SiC(α) film and the method using the SiC(α) film and the SiC(α) film on the SiC(α) film
(α) There is a method of using a SiCx Oy film formed by forced oxidation of the film.

【００１８】図１を参照すれば、ＳｉＣ（α）膜のみを
用いる方法として、キャパシタの第１電極で使用される
第１導電層１０、例えば、不純物のドーピングされた多
結晶シリコン層上に１５オングストローム程度の自然酸
化膜１１が形成され、この自然酸化膜１１上に前記（１
）式を通じてＳｉＣ（α）膜１２を７０オングストロー
ム程度の厚さに形成し、前記ＳｉＣ（α）膜１２上にキ
ャパシタの第２電極で使用される第２導電層２０、例え
ば、不純物のドーピングされた多結晶シリコンを形成す
る。Referring to FIG. 1, in a method using only a SiC (α) film, a first conductive layer 10 used as a first electrode of a capacitor, for example, a layer 15 on a polycrystalline silicon layer doped with impurities, is used. A natural oxide film 11 of about angstrom is formed on this natural oxide film 11.
) A SiC(α) film 12 is formed to a thickness of about 70 angstroms, and a second conductive layer 20 used as a second electrode of a capacitor is doped with impurities, for example, on the SiC(α) film 12. Form polycrystalline silicon.

【００１９】図２を参照すれば、ＳｉＣ（α）膜および
ＳｉＣｘ　Ｏｙ　膜を共に用いる方法として、前記図１
の工程のように第１酸化膜１０、自然酸化膜１１および
前記７０オングストローム程度の厚さのＳｉＣ（α）膜
１２を形成後１２オングストローム程度の厚さに前記Ｓ
ｉＣ（α）膜を強制酸化させＳｉＣｘ　Ｏｙ　膜１３を
形成する工程をさらに含み、その上にやはり第２酸化膜
２０を形成する。ここで、未説明符号ｄは前記ＳｉＣ（
α）膜を強制酸化させるとき消費されたＳｉＣ（α）膜
の厚さである。Referring to FIG. 2, as a method of using both the SiC(α) film and the SiCx Oy film, the method shown in FIG.
After forming the first oxide film 10, the natural oxide film 11, and the SiC (α) film 12 with a thickness of about 70 angstroms as in the step of
The method further includes a step of forcibly oxidizing the iC(α) film to form a SiCx Oy film 13, and a second oxide film 20 is also formed thereon. Here, the unexplained code d is the SiC (
α) This is the thickness of the SiC(α) film consumed when the film is forcibly oxidized.

【００２０】下に示した表１は、本発明によるＳｉＣ（
α）膜を誘電体膜として形成したときと、従来の大容量
のメモリ素子で一般に使用される酸化膜（Ｏｘｉｄｅ）
　／窒化膜（Ｎｉｔｒｉｄｅ）　／酸化膜（Ｏｘｉｄｅ
）　（ＯＮＯ）構造で誘電体膜を形成したときのキャパ
シタンス値を測定値と予想値でそれぞれ比較整理したも
のである。ここで、下に示した表１のデータは、１６Ｍ
ｂＤＲＡＭにおいてスタック構造およびＳＳＷ（Ｓｉｎ
ｇｌｅ　ＳｔａｃｋＷｒａｏｏｅｄ）構造のキャパシタ
に適用されたものである。Table 1 shown below shows that SiC (
α) When the film is formed as a dielectric film, and when the film is formed as a dielectric film, and when the film is formed as an oxide film that is generally used in conventional large-capacity memory elements.
/Nitride film /Oxide film
) The capacitance values when a dielectric film is formed with the (ONO) structure are compared and arranged using measured values and expected values. Here, the data in Table 1 shown below is 16M
Stack structure and SSW (Sin
This method is applied to a capacitor having a StackWraooed structure.

【００２１】[0021]

【表１】[Table 1]

【００２２】前記表１で示した通り、本発明によるＳｉ
Ｃ（α）膜を誘電体で用いれば、従来のＯＮＯ構造より
遥かに良好なキャパシタが得られる。なお、表１中、Ｔ
（Ｎ）は窒化膜の厚さを、Ｔ（ＳｉＣ（α））はＳｉＣ
（α）膜の厚さを、Ｔ（誘電体膜）はキャパシタの第１
電極および第２電極との間に介在される誘電体膜の厚さ
をそれぞれ示す。また、Ｏ　　ＳｉＣ（α）構造は図１
に示した通り自然酸化膜とＳｉＣ（α）膜よりなる構造
を示し、Ｏ　　ＳｉＣ（α）ＳｉＣｘ　Ｏｙ　構造は図
２に示した通り自然酸化膜、ＳｉＣ（α）膜およびＳｉ
Ｃｘ　Ｏｙ　膜よりなる構造をそれぞれ示す。As shown in Table 1 above, Si according to the present invention
If a C(α) film is used as a dielectric, a much better capacitor can be obtained than the conventional ONO structure. In addition, in Table 1, T
(N) is the thickness of the nitride film, T(SiC(α)) is the thickness of the SiC
(α) is the thickness of the film, T (dielectric film) is the first
The thickness of the dielectric film interposed between the electrode and the second electrode is shown. In addition, the O SiC (α) structure is shown in Figure 1.
As shown in Figure 2, the structure consists of a natural oxide film and a SiC (α) film, and the O SiC (α) SiCx Oy structure consists of a natural oxide film, a SiC (α) film, and an Si
Each shows a structure made of a Cx Oy film.

【００２３】前記表１で従来のＯＮＯ構造のＴ（誘電体
膜）とキャパシタンス値は電気的に測定された値を示し
たもので、本発明によるＳｉＣ（α）膜構造に対する予
想値は下に示した計算法でそのそれぞれの値が得られる
。キャパシタンスを求める式がIn Table 1, the T (dielectric film) and capacitance values of the conventional ONO structure are electrically measured values, and the predicted values for the SiC (α) film structure according to the present invention are shown below. Each value can be obtained using the calculation method shown. The formula for calculating capacitance is

【００２４】[0024]

【数１】[Math 1]

【００２５】（ここで、ε＝ε０　×εｒである誘電常
数、Ａはキャパシタ電極の表面積をそれぞれ示す。）な
ので、Ｔ（誘電体膜）さえ分かれば、（ε＝ε０　×ε
ｒ×Ａはキャパシタ構造と誘電体膜の種類が決定されれ
ば一定した値なので）キャパシタンス値が求められる。(Here, the dielectric constant is ε=ε0 ×εr, and A indicates the surface area of the capacitor electrode.) Therefore, if T (dielectric film) is known, (ε=ε0 ×ε
Since r×A is a constant value once the capacitor structure and the type of dielectric film are determined, the capacitance value is determined.

【００２６】例として、（１）Ｏ　　ＳｉＣ（α）構造
において、スタック構造Ｔ（ＳｉＣ（α））＝７０オン
グストロームとすると、As an example, in (1) O SiC(α) structure, if the stack structure T(SiC(α))=70 angstroms,

【００２７】[0027]

【数２】[Math 2]

【００２８】（２）Ｏ　　ＳｉＣ（α）ＳｉＣｘ　Ｏｙ
　構造において（１２オングストローム程度で強制酸化
膜形成時）スタック構造Ｔ（ＳｉＣ（α））＝７０オン
グストロームとすると、(2)O SiC(α)SiCx Oy
In the structure, if the stack structure T (SiC (α)) = 70 angstroms (when forming a forced oxide film at about 12 angstroms),

【００２９】[0029]

【数３】[Math 3]

【００３０】（ここで、前記４．３２オングストローム
は前記ＳｉＣ（α）膜を強制酸化させるとき消費される
ＳｉＣ（α）膜の厚さである。）である。(Here, the 4.32 angstrom is the thickness of the SiC(α) film consumed when the SiC(α) film is forcibly oxidized.)

【００３１】前述した本発明の実施例は、キャパシタの
第２電極で使用される第２導電層を多結晶シリコン層沈
積後不純物イオン注入工程を経て不純物がドーピングさ
れた多結晶シリコン層を用いたが、前記不純物イオン注
入工程時不純物が誘電体膜上に浸透して誘電体膜の電気
的な特性低下を生ずることも有り得るので、これを防止
するために、多結晶シリコンを沈積する際、多結晶シリ
コンのソースガスと同時に、多結晶シリコン中にドープ
される不純物源を同時に導入しながら多結晶シリコンを
沈積する現場ドープ（ｉｎ−ｓｉｔｕ　ｄｏｐｅ）され
た多結晶シリコンを使用することもできる。The above-described embodiment of the present invention uses a polycrystalline silicon layer doped with impurities through an impurity ion implantation process after depositing a polycrystalline silicon layer for the second conductive layer used as the second electrode of the capacitor. However, during the impurity ion implantation process, impurities may penetrate onto the dielectric film and cause a deterioration in the electrical characteristics of the dielectric film. To prevent this, when depositing polycrystalline silicon, In-situ doped polycrystalline silicon can also be used in which polycrystalline silicon is deposited while simultaneously introducing a source gas of crystalline silicon and an impurity source to be doped into the polycrystalline silicon.

【００３２】[0032]

【発明の効果】以上述べたように、本発明によるキャパ
シタの製造方法はキャパシタの誘電体膜として高誘電物
質であるＳｉＣ（α）を用いることにより、メモリ装置
においてキャパシタの容量を増加させることができる。 また、誘電常数が低い物質を誘電体膜で用いる場合より
も厚さを薄くしなくてもよく、工程上のマージン（ｍａ
ｒｇｉｎ）を有することができて、従来の方法に比べて
さらに良好な素子の収率増大が図れる。As described above, the method for manufacturing a capacitor according to the present invention makes it possible to increase the capacitance of a capacitor in a memory device by using SiC (α), which is a high dielectric material, as the dielectric film of the capacitor. can. In addition, the thickness does not need to be made thinner than when using a material with a low dielectric constant for the dielectric film, and the process margin (ma
rgin), and the yield of devices can be increased even better than in conventional methods.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】　　本発明によるＯ　　ＳｉＣ（α）構造の誘
電体膜を採択したキャパシタを示した断面図である。FIG. 1 is a cross-sectional view of a capacitor employing a dielectric film having an O 2 SiC (α) structure according to the present invention.

【図２】　　本発明によるＯ　　ＳｉＣ（α）ＳｉＣｘ
　Ｏｙ　構造の誘電体膜を採択したキャパシタを示した
断面図である。FIG. 2 O SiC(α)SiCx according to the present invention
1 is a cross-sectional view showing a capacitor employing a dielectric film having an Oy structure.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】　　キャパシタの第１電極で使われる第１
導電層上にα型炭化ケイ素層を形成する工程と、前記α
型炭化ケイ素層上にキャパシタの第２電極で使われる第
２導電層を形成する工程よりなることを特徴とする半導
体装置の製造方法。[Claim 1] A first electrode used in a first electrode of a capacitor.
forming an α-type silicon carbide layer on the conductive layer;
A method for manufacturing a semiconductor device, comprising the step of forming a second conductive layer used as a second electrode of a capacitor on a silicon carbide layer. 【請求項２】　　前記α型炭化ケイ素層上にこの炭化ケ
イ素層を強制酸化させて強制酸化された炭化ケイ素層を
形成する工程をさらに含むことを特徴とする請求項１記
載の半導体装置の製造方法。2. Manufacturing the semiconductor device according to claim 1, further comprising the step of forcibly oxidizing the silicon carbide layer on the α-type silicon carbide layer to form a forcibly oxidized silicon carbide layer. Method. 【請求項３】　　前記α型炭化ケイ素層は４塩化ケイ素
とメタンを反応させて得られることを特徴とする請求項
１または請求項２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the α-type silicon carbide layer is obtained by reacting silicon tetrachloride with methane. 【請求項４】　　前記第２導電層は現場ドープされた多
結晶シリコン層よりなることを特徴とする請求項１また
は請求項２に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductive layer is made of an in-situ doped polycrystalline silicon layer.
JP3297138A 1991-06-12 1991-11-13 Manufacture of semiconductor device Pending JPH04369264A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1991-9682 1991-06-12
KR1019910009682A KR930001428A (en) 1991-06-12 1991-06-12 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
JPH04369264A true JPH04369264A (en) 1992-12-22

Family

ID=19315689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3297138A Pending JPH04369264A (en) 1991-06-12 1991-11-13 Manufacture of semiconductor device

Country Status (6)

Country Link
JP (1) JPH04369264A (en)
KR (1) KR930001428A (en)
DE (1) DE4136303A1 (en)
FR (1) FR2677810A1 (en)
GB (1) GB2256747A (en)
IT (1) IT1252285B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818071A (en) * 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
KR100360413B1 (en) 2000-12-19 2002-11-13 삼성전자 주식회사 Method of manufacturing capacitor of semiconductor memory device by two-step thermal treatment

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978553A (en) * 1982-10-27 1984-05-07 Hitachi Ltd Capacitor and manufacture thereof
JPS60242678A (en) * 1984-05-17 1985-12-02 Seiko Epson Corp Semiconductor memory device
JPS6347983A (en) * 1986-08-18 1988-02-29 Sharp Corp Silicon carbide field effect transistor

Also Published As

Publication number Publication date
ITMI913097A1 (en) 1993-05-20
GB2256747A (en) 1992-12-16
FR2677810A1 (en) 1992-12-18
IT1252285B (en) 1995-06-08
ITMI913097A0 (en) 1991-11-20
GB9124626D0 (en) 1992-01-08
DE4136303A1 (en) 1992-12-17
KR930001428A (en) 1993-01-16

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