JPH04355627A - Load protective circuit - Google Patents
Load protective circuitInfo
- Publication number
- JPH04355627A JPH04355627A JP3157632A JP15763291A JPH04355627A JP H04355627 A JPH04355627 A JP H04355627A JP 3157632 A JP3157632 A JP 3157632A JP 15763291 A JP15763291 A JP 15763291A JP H04355627 A JPH04355627 A JP H04355627A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- power
- load
- abnormality
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract 2
- 238000001514 detection method Methods 0.000 claims abstract description 118
- 230000005856 abnormality Effects 0.000 claims abstract description 109
- 230000000717 retained effect Effects 0.000 claims abstract description 4
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract description 7
- 239000003990 capacitor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000012544 monitoring process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、安定化電源回路を有し
交流電源から絶縁された状態で使用されるテレビジョン
受像機等の負荷を、負荷異常，電源異常から保護する負
荷保護回路に関する。[Field of Industrial Application] The present invention relates to a load protection circuit that protects a load such as a television receiver, which has a stabilized power supply circuit and is used insulated from an AC power supply, from load abnormalities and power supply abnormalities. .
【０００２】0002
【従来の技術】従来、この種負荷の１例であるテレビジ
ョン受像機は選局回路部等の常給電回路部に給電するた
め、図５に示すように、電源プラグ１の交流電源が電源
スイッチを介すことなく負荷（受像機）２の安定化電源
回路３に供給され、この電源回路３によりトランスを用
いて１次側と２次側とを絶縁して駆動用の直流電源を形
成する。そして、電源回路３の２次側の直流電源を回路
部４に供給し、この回路部４を常給電駆動する。また、
この種負荷に対しては、回路部４の故障等の負荷異常に
基づく過電流及び電源異常に基づく交流電源の過電圧か
ら保護するため、従来は、つぎに説明する負荷保護回路
が設けられる。2. Description of the Related Art Conventionally, a television receiver, which is an example of this type of load, supplies power to a regular power supply circuit such as a channel selection circuit, so as shown in FIG. It is supplied to the stabilized power supply circuit 3 of the load (receiver) 2 without going through a switch, and this power supply circuit 3 uses a transformer to insulate the primary side and the secondary side to form a DC power source for driving. do. Then, the DC power on the secondary side of the power supply circuit 3 is supplied to the circuit section 4, and the circuit section 4 is driven by regular power supply. Also,
Conventionally, a load protection circuit described below is provided for this type of load in order to protect it from overcurrent due to load abnormality such as a failure of the circuit section 4 and overvoltage of the AC power source due to power supply abnormality.
【０００３】この従来の負荷保護回路は図５に示すよう
に、負荷２内に前記両異常の監視検出用のマイクロコン
ピュータ（以下ＣＰＵという）５を設けるとともに、電
源プラグ１と電源回路３との間の１次側交流ライン６に
トライアック等の給電遮断用のスイッチ素子７を設け、
かつ、負荷２の絶縁を維持するため、ＣＰＵ５とスイッ
チ素子７との間にホトカプラ等の絶縁回路８を設けて形
成される。This conventional load protection circuit, as shown in FIG. A switch element 7 for cutting off the power supply such as a triac is provided on the primary side AC line 6 between the two,
In addition, in order to maintain insulation of the load 2, an insulating circuit 8 such as a photocoupler is provided between the CPU 5 and the switch element 7.
【０００４】そして、電源回路３の直流電源によりＣＰ
Ｕ５が駆動され、このＣＰＵ５により電源回路３の２次
側の電流，電圧等から前記両異常が監視検出される。[0004] Then, the DC power supply of the power supply circuit 3
U5 is driven, and both abnormalities are monitored and detected by the CPU 5 from the current, voltage, etc. on the secondary side of the power supply circuit 3.
【０００５】この監視検出に基づき、異常発生時はＣＰ
Ｕ５により絶縁回路８を介してスイッチ素子７がオフさ
れて開放され、この開放により負荷２への交流電源の給
電が自動的に遮断される。Based on this monitoring detection, when an abnormality occurs, the CP
U5 turns off and opens the switch element 7 via the insulating circuit 8, and this opening automatically cuts off the AC power supply to the load 2.
【０００６】[0006]
【発明が解決しようとする課題】前記図５の従来の負荷
保護回路の場合、電源回路３の２次側のＣＰＵ５により
、その１次側のスイッチ素子７を制御するため、ＣＰＵ
５とスイッチ素子７との間に必ず絶縁回路８を設ける必
要があり、その分複雑化するとともに高価になる問題点
がある。また、前記１次側と２次側との絶縁を図るため
、一定の沿面距離及び空間距離を必要とし、これらの距
離の制約に基づき、回路を小型化できない問題点もある
。In the case of the conventional load protection circuit shown in FIG. 5, the CPU 5 on the secondary side of the power supply circuit 3 controls the switch element 7 on the primary side.
Since it is necessary to provide an insulating circuit 8 between the switch element 5 and the switch element 7, there is a problem that the insulating circuit 8 becomes more complicated and expensive. Further, in order to insulate the primary side and the secondary side, a certain creepage distance and a certain spatial distance are required, and there is a problem that the circuit cannot be miniaturized based on restrictions on these distances.
【０００７】さらに、ＣＰＵ５が負荷２に設けられるた
め、複数の負荷の保護を行う場合は、ＣＰＵ５，スイッ
チ素子７，絶縁回路８等の全回路を負荷２の個数だけ設
ける必要があり、複雑かつ高価になる問題点がある。本
発明は、従来の絶縁回路８を省くとともに、絶縁のため
の沿面距離，空間距離の制約を解消し、簡素かつ安価で
小型にすることを目的とする。また、複数の負荷の保護
を行う場合に、一部を共用して一層簡素かつ安価で小型
に構成することも目的とする。Furthermore, since the CPU 5 is provided in the load 2, when protecting multiple loads, it is necessary to provide all the circuits such as the CPU 5, the switch element 7, the insulation circuit 8, etc. in the same number as the load 2, which is complicated and complicated. The problem is that it is expensive. The present invention aims to eliminate the conventional insulating circuit 8, eliminate constraints on creepage distance and spatial distance for insulation, and make it simple, inexpensive, and compact. Another object of the present invention is to share a portion of the load when protecting a plurality of loads, thereby making the structure simpler, cheaper, and more compact.
【０００８】[0008]
【課題を解決するための手段】前記の目的を達成するた
めに、本発明の負荷保護回路においては、請求項１の場
合、交流電源と負荷の安定化電源回路との間の１次側交
流ラインに挿入された給電遮断用のスイッチ素子と、前
記１次側交流ラインの電流を検出する電流検出回路と、
前記交流電源の電圧を検出する電圧検出回路と、前記両
検出回路の検出結果を監視して前記両異常それぞれの発
生を検出する異常検出手段と、前記異常検出手段の検出
情報が書込まれてリセットされるまで保持する不揮発性
のメモリと、前記検出情報及び前記メモリの保持情報に
基づき，前記交流電源の投入時は前記両異常のいずれで
もない状態を判別したときのみ前記スイッチ素子をオン
し，前記交流電源の供給中は前記両異常のいずれかの発
生により前記スイッチ素子をオフするとともに前記検出
情報を前記メモリに書込む制御処理手段と、前記交流電
源が供給されて前記両手段等に駆動電源を与える保護回
路専用の電源回路とを備える。[Means for Solving the Problems] In order to achieve the above object, in the load protection circuit of the present invention, in the case of claim 1, the primary side AC between the AC power supply and the stabilizing power supply circuit of the load. a switch element for cutting off the power supply inserted into the line; a current detection circuit that detects the current of the primary side AC line;
A voltage detection circuit that detects the voltage of the AC power supply, an abnormality detection means that monitors the detection results of both the detection circuits and detects the occurrence of each of the two abnormalities, and detection information of the abnormality detection means is written. Based on a nonvolatile memory held until reset, the detected information, and information held in the memory, when turning on the AC power, the switch element is turned on only when it is determined that neither of the above abnormalities occurs. , control processing means for turning off the switch element and writing the detection information into the memory when either of the above abnormalities occurs while the AC power is being supplied; It also includes a power supply circuit dedicated to a protection circuit that provides drive power.
【０００９】また、請求項２の場合は、交流電源と各負
荷の安定化電源回路との間の各１次側交流ラインに挿入
された複数の給電遮断用のスイッチ素子と、前記各１次
側交流ラインそれぞれの電流を検出する複数の電流検出
回路と、前記交流電源の電圧を検出する電圧検出回路と
、前記各負荷それぞれの前記両異常の検出情報が書込ま
れてリセットされるまで保持する不揮発性のメモリと、
異常検出及び前記メモリ，前記各スイッチ素子の制御を
行うＣＰＵと、前記交流電源が供給されて前記両手段等
に駆動電源を与える保護回路専用の電源回路とを備え、
前記ＣＰＵに、前記各電流検出回路及び前記電圧検出回
路の検出結果を監視して前記各負荷の前記両異常それぞ
れの発生を検出する異常検出手段と、前記異常検出手段
の前記各負荷の検出情報及び前記メモリの前記各負荷の
保持情報に基づき，前記交流電源の投入時は前記各負荷
の前記両異常のいずれでもない状態を判別したときのみ
前記各スイッチ素子それぞれをオンし，前記交流電源の
供給中は前記各負荷の前記両異常のいずれかの発生によ
り前記各スイッチ素子それぞれをオフするとともに前記
各負荷それぞれの前記検出情報を前記メモリに書込む制
御処理手段とを設ける。Further, in the case of claim 2, a plurality of switch elements for cutting off the power supply inserted in each primary side AC line between the AC power supply and the stabilizing power supply circuit of each load, and each of the primary side A plurality of current detection circuits that detect the current of each of the side AC lines, a voltage detection circuit that detects the voltage of the AC power supply, and detection information of both of the above-mentioned abnormalities of each of the loads are written and held until reset. non-volatile memory,
comprising a CPU that detects abnormality and controls the memory and each switch element, and a power supply circuit dedicated to a protection circuit to which the AC power is supplied and provides driving power to both the means, etc.,
The CPU includes an abnormality detection means for monitoring the detection results of each of the current detection circuits and the voltage detection circuit to detect the occurrence of each of the above-mentioned abnormalities in each of the loads, and detection information of each of the loads by the abnormality detection means. Based on the information held for each load in the memory, when turning on the AC power source, each switch element is turned on only when it is determined that each load is in a state that is neither of the above abnormalities, and the AC power source is turned on. During supply, control processing means is provided which turns off each of the switching elements when either of the two abnormalities occurs in each of the loads, and writes the detection information of each of the loads into the memory.
【００１０】0010
【作用】前記のように構成された本発明の負荷保護回路
の場合、請求項１の構成においては、スイッチ素子だけ
でなく電流検出回路，電圧検出回路が交流電源側，すな
わち負荷の１次側に設けられ、しかも、保護回路専用の
電源回路の給電により、異常検出手段，制御処理手段が
負荷から供給されることなく、メモリの保持情報及び両
検出回路の検出結果に基づいて負荷異常，電源異常の発
生を判別し、交流電源の投入時は両異常のいずれも発生
していないときのみスイッチ素子をオンして給電し、給
電中は両異常のいずれかの発生によりスイッチ素子をオ
フして給電を自動的に遮断する。そのため、回路全体が
前記１次側に設けられ、従来の絶縁回路が不要になると
ともに、沿面距離，空間距離が不要になり、簡素かつ安
価で小型に形成できる。[Operation] In the case of the load protection circuit of the present invention configured as described above, in the configuration of claim 1, not only the switching element but also the current detection circuit and the voltage detection circuit are connected to the AC power supply side, that is, to the primary side of the load. Moreover, by supplying power to a power supply circuit dedicated to the protection circuit, the abnormality detection means and control processing means are not supplied with power from the load, and detect load abnormalities and power supply based on the information held in memory and the detection results of both detection circuits. It determines whether an abnormality has occurred, and when turning on the AC power supply, the switch element is turned on and power is supplied only when neither of the two abnormalities occurs, and during power supply, the switch element is turned off when either of the two abnormalities occur. Automatically cut off power supply. Therefore, the entire circuit is provided on the primary side, eliminating the need for a conventional insulating circuit, as well as the creepage distance and spatial distance, making it simple, inexpensive, and compact.
【００１１】また、請求項２の構成においては、交流電
源側，すなわち各負荷の１次側の１個の電圧検出回路の
検出結果を各負荷それぞれの電源異常の検出に共用し、
しかも、１個のＣＰＵの異常検出手段，制御処理手段に
より、メモリの保持情報及び負荷毎の前記１次側の電流
検出回路，前記電圧検出回路の検出結果に基づき、各負
荷それぞれの負荷異常，電源異常の発生を判別し、負荷
毎に、交流電源の投入時は両異常のいずれかが発生して
いないときのみそれぞれのスイッチ素子をオンし、給電
中は両異常のいずれかの発生によりそれぞれのスイッチ
素子をオフして給電を自動的に遮断する。そのため、回
路全体を前記１次側に設け、しかも、負荷の個数によら
ず電圧検出回路，ＣＰＵ，メモリ等をそれぞれ１個だけ
用いて形成され簡単かつ安価で小型な構成により、複数
の負荷の保護が行える。Further, in the configuration of claim 2, the detection result of one voltage detection circuit on the AC power supply side, that is, on the primary side of each load is shared for detecting power supply abnormality of each load,
Moreover, the abnormality detection means and control processing means of one CPU detect the load abnormality of each load based on the information held in the memory and the detection results of the primary side current detection circuit and voltage detection circuit for each load. The occurrence of a power supply abnormality is determined, and for each load, when turning on the AC power, each switch element is turned on only when either of the two abnormalities does not occur, and during power supply, each switch element is turned on when either of the two abnormalities occurs. The switch element is turned off to automatically cut off the power supply. Therefore, the entire circuit is provided on the primary side, and it is formed using only one voltage detection circuit, CPU, memory, etc. regardless of the number of loads, and is simple, inexpensive, and compact, and can handle multiple loads. Can be protected.
【００１２】0012
【実施例】実施例について、図１ないし図４を参照して
説明する。
（第１の実施例）まず、１個の負荷の保護に適用した第
１の実施例について、図１及び図２を参照して説明する
。図１において、９は電源プラグ、１０はテレビジョン
受像機等の負荷、１１は図５の電源回路３と同様の安定
化電源回路、１２は負荷保護回路、１３は電源プラグと
電源回路１１との間の１次側交流ライン１４に図５のス
イッチ素子７と同様の給電遮断用のスイッチ素子１５を
設けた給電スイッチ回路である。Embodiment An embodiment will be described with reference to FIGS. 1 to 4. (First Embodiment) First, a first embodiment applied to protection of one load will be described with reference to FIGS. 1 and 2. In FIG. 1, 9 is a power plug, 10 is a load such as a television receiver, 11 is a stabilizing power supply circuit similar to the power supply circuit 3 in FIG. 5, 12 is a load protection circuit, and 13 is a power plug and a power supply circuit 11. This is a power supply switch circuit in which a switch element 15 for power supply cutoff similar to the switch element 7 of FIG. 5 is provided on the primary side AC line 14 between the two.
【００１３】１６は交流ライン１４のスイッチ素子１５
より電源側に設けられた電流検出回路、１７は電源プラ
グ９の交流電源が供給される保護回路専用の電源回路、
１８は電圧検出回路である。１９は異常検出手段及び制
御処理手段を形成するＣＰＵであり、給電端子Ｖｃｃが
電源回路１７に接続されている。２０は異常検出手段の
検出情報が書込まれる不揮発性のメモリである。16 is a switch element 15 of the AC line 14
A current detection circuit provided closer to the power supply side; 17 is a power supply circuit dedicated to a protection circuit to which AC power from the power plug 9 is supplied;
18 is a voltage detection circuit. A CPU 19 forms an abnormality detection means and a control processing means, and a power supply terminal Vcc is connected to the power supply circuit 17. Reference numeral 20 denotes a nonvolatile memory into which information detected by the abnormality detection means is written.
【００１４】そして、電源プラグ９がコンセントに挿入
されて交流電源が投入されると、この交流電源に基づく
電源回路１７の直流電源がＣＰＵ１９に供給されてＣＰ
Ｕ１９が起動される。この起動によりＣＰＵ１９の異常
検出手段が監視検出プログラムの実行を開始し、最初は
メモリ２０の記憶情報を読出す。When the power plug 9 is inserted into the outlet and AC power is turned on, the DC power of the power supply circuit 17 based on this AC power is supplied to the CPU 19.
U19 is activated. Upon this activation, the abnormality detection means of the CPU 19 starts executing the monitoring detection program, and first reads out the information stored in the memory 20.
【００１５】ところで、メモリ２０はＣＰＵ１９の制御
処理手段により、給電中に生じた負荷異常，給電異常の
情報が書込まれ、リセット操作等でリセット端子２１に
リセット信号が与えられ、ＣＰＵ１９により記憶内容が
リセットクリアされない限り、書込まれた情報を保持す
る。また、電圧検出回路１８は電源回路１７の２次側直
流出力の電圧から交流電源の電圧を監視して検出し、例
えば交流電源の電圧が設定された基準電圧以上の過電圧
になると、ＣＰＵ１９に供給する検出結果の信号がレベ
ル反転する。By the way, the control processing means of the CPU 19 writes information on load abnormalities and power supply abnormalities occurring during power supply into the memory 20, and a reset signal is applied to the reset terminal 21 by a reset operation, etc., and the memory contents are updated by the CPU 19. The written information is retained unless it is reset and cleared. Further, the voltage detection circuit 18 monitors and detects the voltage of the AC power supply from the voltage of the secondary side DC output of the power supply circuit 17, and, for example, when the voltage of the AC power supply becomes an overvoltage higher than a set reference voltage, the voltage is supplied to the CPU 19. The level of the detection result signal is inverted.
【００１６】そして、メモリ２０の情報及び異常検出手
段の検出結果に基づき、ＣＰＵ１９の制御処理手段がス
イッチ素子１５のオン，オフ及びメモリ２０の書込みを
制御する。このとき、メモリ２０に負荷異常，電源異常
のいずれの情報も書込まれていなければ、交流電源，負
荷１０のいずれもが正常であると判別してＣＰＵ１９の
制御処理手段がスイッチ素子１５をオンする。Based on the information in the memory 20 and the detection result of the abnormality detection means, the control processing means of the CPU 19 controls turning on and off of the switch element 15 and writing in the memory 20. At this time, if neither the load abnormality nor the power supply abnormality information is written in the memory 20, it is determined that both the AC power supply and the load 10 are normal, and the control processing means of the CPU 19 turns on the switch element 15. do.
【００１７】そして、、スイッチ素子１５のオンにより
電源プラグ９の交流電源が電流検出回路１６，スイッチ
素子１５を介して電源回路１１に供給され、負荷１０の
常給電回路部が給電駆動される。ところで、交流電源が
電源回路１１に供給されると、負荷１０に応じた交流ラ
イン１４の交流の負荷電流が電流検出回路１６により検
出され、負荷電流が設定された基準電流以上の過電流に
なると、検出回路１６は例えばＣＰＵ１９に供給する検
出結果の信号をレベル反転する。When the switch element 15 is turned on, the AC power from the power plug 9 is supplied to the power supply circuit 11 via the current detection circuit 16 and the switch element 15, and the normal power supply circuit section of the load 10 is driven. By the way, when AC power is supplied to the power supply circuit 11, the AC load current of the AC line 14 corresponding to the load 10 is detected by the current detection circuit 16, and if the load current becomes an overcurrent exceeding a set reference current, , the detection circuit 16 inverts the level of the detection result signal supplied to the CPU 19, for example.
【００１８】そして、負荷１０の給電中はＣＰＵ１９の
異常検出手段により、電圧検出回路１８が過電圧を検出
する電源異常及び電流検出回路１６が過電流を検出する
負荷異常の発生を監視する。なお、スイッチ素子１５が
オンした直後は、安定化電源回路１１の大容量の平滑コ
ンデンサの初期充電に基づく過大なラッシュ電流が瞬時
流れる。While power is being supplied to the load 10, the abnormality detection means of the CPU 19 monitors the occurrence of a power supply abnormality in which the voltage detection circuit 18 detects an overvoltage and the occurrence of a load abnormality in which the current detection circuit 16 detects an overcurrent. Immediately after the switch element 15 is turned on, an excessive rush current instantaneously flows due to the initial charging of the large-capacity smoothing capacitor of the stabilized power supply circuit 11.
【００１９】そして、このラッシュ電流に基づく負荷異
常の誤検出を防止するため、例えばスイッチ素子１５の
オン直後からの一定期間、電流検出回路１６又はＣＰＵ
１９の負荷異常の監視が不動作に保持される。つぎに、
給電中に負荷電流が過電流になって負荷異常の発生が検
出されると、ＣＰＵ１９の制御処理手段は、スイッチ素
子１５をオフにするとともにメモリ２０に負荷異常の情
報を書込む。In order to prevent erroneous detection of load abnormality based on this rush current, for example, the current detection circuit 16 or the CPU
19 load abnormality monitoring is held inactive. next,
When the load current becomes overcurrent during power supply and occurrence of a load abnormality is detected, the control processing means of the CPU 19 turns off the switch element 15 and writes information on the load abnormality into the memory 20.
【００２０】そして、スイッチ素子１５のオフにより負
荷１０への給電が自動的に遮断され、負荷１０が負荷異
常から保護される。また、メモリ２０に負荷異常の情報
が書込まれるため、異常の原因が除去される前に不用意
に電源プラグ９がコンセントに再投入されても、負荷異
常の情報が読出されてスイッチ素子１５はオンすること
がなく、負荷１０の給電が禁止され続ける。When the switch element 15 is turned off, the power supply to the load 10 is automatically cut off, and the load 10 is protected from load abnormality. In addition, since the information on the load abnormality is written to the memory 20, even if the power plug 9 is inadvertently re-inserted into the outlet before the cause of the abnormality is removed, the information on the load abnormality is read out and the switch element 15 is never turned on, and power supply to the load 10 continues to be prohibited.
【００２１】すなわち、交流電源の再投入によりＣＰＵ
１９が起動されたときに、メモリ２０から負荷異常の情
報が読出されると、負荷異常の原因が解消されていない
可能性が高いため、ＣＰＵ１９の制御処理手段は無条件
にスイッチ１５をオフに保持する。なお、負荷異常の原
因が除去されたときは、リセット端子２１にリセット信
号が与えられ、ＣＰＵ１９によりメモリ２０の情報がリ
セットクリアされる。That is, by turning on the AC power again, the CPU
If the load abnormality information is read from the memory 20 when the CPU 19 is started, it is highly likely that the cause of the load abnormality has not been resolved, so the control processing means of the CPU 19 unconditionally turns off the switch 15. Hold. Note that when the cause of the load abnormality is removed, a reset signal is applied to the reset terminal 21, and the information in the memory 20 is reset and cleared by the CPU 19.
【００２２】このリセットクリア後に電源プラグ９をコ
ンセントに挿入して交流電源を再投入すると、通常はス
イッチ素子１５がオンして負荷１０の給電が行われる。
つぎに、給電中に交流電源の電圧が過電圧になって電源
異常の発生が検出されると、交流電源が復旧している可
能性もあるため、ＣＰＵ１９の制御処理手段は、電圧検
出回路１８の検出結果から交流電源の現在の電圧状態を
検査する。After this reset clear, when the power plug 9 is inserted into the outlet and the AC power is turned on again, the switch element 15 is normally turned on and power is supplied to the load 10. Next, when the voltage of the AC power supply becomes overvoltage during power supply and occurrence of a power supply abnormality is detected, since the AC power supply may have been restored, the control processing means of the CPU 19 controls the voltage detection circuit 18. The current voltage status of the AC power supply is inspected from the detection results.
【００２３】そして、電圧が正常なときのみ、異常がな
いとしてスイッチ素子１５をオンし、負荷１０の常給電
回路部を給電駆動する。なお、メモリ２０の電源異常の
情報も、リセット端子２１にリセット信号が与えられた
ときにリセットクリアされる。Then, only when the voltage is normal, it is assumed that there is no abnormality, and the switch element 15 is turned on to drive the normal power supply circuit section of the load 10. Note that the information on power failure in the memory 20 is also reset and cleared when a reset signal is applied to the reset terminal 21.
【００２４】したがって、電源プラグ１９がコンセント
に挿入される電源投入時、メモリ２０の記憶情報と検出
回路１６，１８の検出情報とに基づき、負荷異常，電源
異常のいずれの恐れもないときのみスイッチ素子１５が
オンされて負荷１０に交流電源が供給され、しかも、給
電中のいずれかの異常の発生によりスイッチ素子１５が
オフして給電が自動的に遮断され、負荷１０が両異常か
ら確実に保護される。Therefore, when the power is turned on when the power plug 19 is inserted into the outlet, the switch is activated only when there is no risk of either a load abnormality or a power abnormality based on the information stored in the memory 20 and the detection information of the detection circuits 16 and 18. The element 15 is turned on and AC power is supplied to the load 10, and if any abnormality occurs during power supply, the switch element 15 is turned off and the power supply is automatically cut off, ensuring that the load 10 is protected from both abnormalities. protected.
【００２５】そして、保護回路１２が電源回路１７の直
流電源で動作し、保護回路１２全体が交流電源側，すな
わち電源回路１１の１次側に設けられるため、従来の絶
縁回路８等が不要になり、しかも、絶縁を図るための沿
面距離及び空間距離も省ける。そのため、保護回路１２
が簡素かつ安価な構成になり、例えばハイブリッドＩＣ
により形成し、極めて小型にすることも可能になる。[0025] Since the protection circuit 12 operates on the DC power supply of the power supply circuit 17 and the entire protection circuit 12 is provided on the AC power supply side, that is, on the primary side of the power supply circuit 11, the conventional insulation circuit 8 etc. is not required. Moreover, the creepage distance and space distance required for insulation can also be omitted. Therefore, the protection circuit 12
has become a simple and inexpensive configuration, such as hybrid IC.
It is also possible to make it extremely compact.
【００２６】ところで、図１の各回路１３，１６〜１８
をディスクリート構成としたときの１例は図２に示すよ
うになる。そして、電源回路１７は電源プラグ９の交流
電源をダイオードＤ１，抵抗Ｒ１，コンデンサＣ１によ
り整流平滑し、コンデンサＣ１の端子間の充電電圧に基
づき、チョッパ電源回路ＲＥＧによりＣＰＵ１９の電源
電圧としての５Ｖの直流電圧を発生する。By the way, each circuit 13, 16 to 18 in FIG.
An example of a discrete configuration is shown in FIG. Then, the power supply circuit 17 rectifies and smoothes the AC power from the power plug 9 using a diode D1, a resistor R1, and a capacitor C1. Based on the charging voltage between the terminals of the capacitor C1, the chopper power supply circuit REG outputs 5V as the power supply voltage for the CPU 19. Generates DC voltage.
【００２７】また、電圧検出回路１８はトランジスタＱ
１，ツェナーダイオードＤ２，抵抗Ｒ２〜Ｒ４，コンデ
ンサＣ２により形成され、交流電源の電圧としてのコン
デンサＣ１の充電電圧が抵抗Ｒ３，Ｒ４で分圧され、こ
の分圧がツェナーダイオードＤ２のツェナー電圧より高
くなり、交流電源の電圧が基準電圧以上の過電圧になる
と、トランジスタＱ１がオンしてこのトランジスタＱ１
のエミッタからＣＰＵ１９に供給される検出結果の信号
がローレベルからハイレベルに反転する。The voltage detection circuit 18 also includes a transistor Q.
1. Formed by Zener diode D2, resistors R2 to R4, and capacitor C2, the charging voltage of capacitor C1 as the voltage of the AC power supply is divided by resistors R3 and R4, and this divided voltage is higher than the Zener voltage of Zener diode D2. When the voltage of the AC power supply becomes an overvoltage higher than the reference voltage, the transistor Q1 turns on.
The detection result signal supplied from the emitter to the CPU 19 is inverted from low level to high level.
【００２８】さらに、電流検出回路１６は検出部として
のトランジスタＱ２，ダイオードＤ３，抵抗Ｒ５，Ｒ６
及び出力部としてのトランジスタＱ３，ツェナーダイオ
ードＤ４，抵抗Ｒ７〜Ｒ９，コンデンサＣ３により形成
され、交流ライン１４に挿入された抵抗Ｒ６を通流する
負荷電流が増加すると、トランジスタＱ２がオン状態に
なってコンデンサＣ３が負荷電流に応じた電圧に充電さ
れる。Furthermore, the current detection circuit 16 includes a transistor Q2, a diode D3, and resistors R5 and R6 as a detection section.
When the load current flowing through the resistor R6 formed by the transistor Q3, the Zener diode D4, the resistors R7 to R9, and the capacitor C3 and inserted into the AC line 14 increases, the transistor Q2 turns on. Capacitor C3 is charged to a voltage according to the load current.
【００２９】そして、負荷電流が基準電流以上の過電流
になると、ツェナーダイオードＤ４がオンしてトランジ
スタＱ３がオンし、このトランジスタＱ３のエミッタか
らＣＰＵ１９に供給される検出結果の信号がローレベル
からハイレベルに反転する。なお、抵抗Ｒ５，Ｒ７はト
ランジスタＱ２，Ｑ３の動作を安定化するために設けら
れ、ダイオードＤ３はトランジスタＱ２の逆バイアスを
防止するために設けられている。When the load current becomes an overcurrent exceeding the reference current, the Zener diode D4 is turned on and the transistor Q3 is turned on, and the detection result signal supplied from the emitter of the transistor Q3 to the CPU 19 changes from low level to high level. Flip to level. Note that resistors R5 and R7 are provided to stabilize the operation of transistors Q2 and Q3, and diode D3 is provided to prevent reverse bias of transistor Q2.
【００３０】また、スイッチ回路１３はスイッチ素子１
５としてのトライアックＤ５，ゲート駆動用のトランジ
スタＱ４，Ｑ５及び抵抗Ｒ１０，Ｒ１１，コンデンサＣ
４により形成され、ＣＰＵ１９からトランジスタＱ４の
ベースにハイレベルのオン信号が供給されると、トラン
ジスタＱ４，Ｑ５がオンしてトライアックＤ５のゲート
が負電位になり、この負電位によりトライアックＤ５が
オフからオンに反転する。なお、抵抗Ｒ１０はトランジ
スタＱ５の動作を安定化するために設けられ、抵抗Ｒ１
１，コンデンサＣ４はトライアックＤ５の動作を安定化
するために設けられている。The switch circuit 13 also includes the switch element 1
Triac D5 as 5, transistors Q4, Q5 and resistors R10, R11 for gate driving, capacitor C
When a high-level ON signal is supplied from the CPU 19 to the base of the transistor Q4, the transistors Q4 and Q5 are turned on and the gate of the triac D5 becomes a negative potential, and this negative potential turns the triac D5 from off to Flip on. Note that the resistor R10 is provided to stabilize the operation of the transistor Q5, and the resistor R10 is provided to stabilize the operation of the transistor Q5.
1. Capacitor C4 is provided to stabilize the operation of triac D5.
【００３１】そして、図２においては、例えば抵抗Ｒ６
の電圧降下を利用した極めて簡単な構成で電流検出を行
うため、構成が極めて簡単になる。また、抵抗Ｒ６の抵
抗値を負荷１０に応じて変更することにより、過電流値
の異なる種々の負荷につき、ＣＰＵ１９のプログラムを
変更することなく保護することができ、汎用性の高い負
荷保護回路を提供できる。In FIG. 2, for example, the resistor R6
Since current detection is performed with an extremely simple configuration that utilizes the voltage drop of , the configuration is extremely simple. In addition, by changing the resistance value of the resistor R6 according to the load 10, various loads with different overcurrent values can be protected without changing the program of the CPU 19, and a highly versatile load protection circuit can be realized. Can be provided.
【００３２】ところで、スイッチ素子１５はトライアッ
ク以外の半導体スイッチであってもよく、各部の構成は
実施例に限定されるものではなく、例えば、異常検出手
段，制御処理手段はコンピュータ構成でなくてもよい。
また、安定化電源回路を有する種々の負荷に適用できる
のは勿論である。By the way, the switch element 15 may be a semiconductor switch other than a triac, and the configuration of each part is not limited to the embodiment. For example, the abnormality detection means and control processing means do not have to be computer configurations. good. Moreover, it goes without saying that the present invention can be applied to various loads having a stabilized power supply circuit.
【００３３】（第２の実施例）つぎに、図１の構成を改
良した第２の実施例について、図３を参照して説明する
。図３において、図１と同一符号は同一もしくは相当す
るものを示し、異なる点は負荷保護回路１２にゼロクロ
ス回路２２を付加するとともに、負荷１０からＣＰＵ１
９に負荷１０の局部的な短絡等の電流増加が少ない異常
の発生を通知し、この異常の発生時にもスイッチ素子１
５のオフ及びメモリ２０の書込みを行うようにした点で
ある。(Second Embodiment) Next, a second embodiment in which the configuration of FIG. 1 is improved will be described with reference to FIG. 3. In FIG. 3, the same reference numerals as in FIG.
9 is notified of the occurrence of an abnormality in which the current increase is small, such as a local short circuit in the load 10, and even when this abnormality occurs, the switching element 1
5 and the memory 20 is written.
【００３４】そして、ＣＰＵ２２からスイッチ素子１５
のオン信号が出力されると、ゼロクロス回路２２は１次
側交流ライン１４の負荷電流のゼロクロスタイミングに
同期してスイッチ素子１５をオンし、オン直後のラッシ
ュ電流の急増を防止して緩やかに増加させる。そのため
、ラッシュ電流による故障，ノイズの発生等が防止され
る。しかも、電流検出回路１６では検出困難な負荷１０
内の局部的な異常（負荷異常）の発生時にも、負荷１０
内の短絡検出回路，異常検出回路等の通知により、交流
電源の給電を遮断して負荷１０が保護される。そのため
、第１の実施例の場合より保護性能が向上する利点があ
る。[0034] Then, from the CPU 22 to the switch element 15
When the on signal is output, the zero cross circuit 22 turns on the switch element 15 in synchronization with the zero cross timing of the load current of the primary side AC line 14, preventing the rush current from rapidly increasing immediately after turning on, and gradually increasing the current. let Therefore, failures, noise generation, etc. due to rush current are prevented. Moreover, the load 10 is difficult to detect with the current detection circuit 16.
Even if a local abnormality (load abnormality) occurs within the
The load 10 is protected by cutting off the AC power supply based on the notification from the short circuit detection circuit, abnormality detection circuit, etc. Therefore, there is an advantage that the protection performance is improved compared to the case of the first embodiment.
【００３５】（第３の実施例）つぎに、複数の負荷の保
護に適用した第３の実施例について、図４を参照して説
明する。図４において、図１，図３と同一符号は同一も
しくは相当するものを示し、１０ａ，１０ｂは安定化電
源回路１１ａ，１１ｂを有する２個の負荷、１３ａ，１
３ｂは電源プラグ９と電源回路１１ａ，１１ｂとの間の
１次側交流ライン１４ａ，１４ｂそれぞれにスイッチ素
子１５を設けた給電スイッチ回路、１６ａ，１６ｂは電
源プラグ９と両スイッチ回路１６ａ，１６ｂのスイッチ
素子１５との間それぞれに設けられた電流検出回路、２
３は負荷保護回路である。なお、負荷１０ａ，１０ｂは
例えばテレビジョン受像機，ＶＴＲからなる。(Third Embodiment) Next, a third embodiment applied to protection of a plurality of loads will be described with reference to FIG. In FIG. 4, the same reference numerals as those in FIGS. 1 and 3 indicate the same or equivalent components, and 10a and 10b are two loads having stabilized power supply circuits 11a and 11b;
3b is a power supply switch circuit in which a switch element 15 is provided on each of the primary AC lines 14a and 14b between the power plug 9 and the power supply circuits 11a and 11b; a current detection circuit provided between the switch element 15 and the current detection circuit 2;
3 is a load protection circuit. Note that the loads 10a and 10b include, for example, a television receiver and a VTR.
【００３６】そして、負荷保護回路２３のＣＰＵ１９は
、電圧検出回路１８の検出結果を負荷１０ａ，１０ｂの
電源異常の検出に共用して負荷１０ａ，１０ｂをそれぞ
れの負荷異常及び電源異常から保護する。すなわち、Ｃ
ＰＵ１９の異常検出手段は電流検出回路１６ａ，１６ｂ
の検出結果及び電圧検出回路１８の検出結果を監視し、
両電流検出回路１６ａ，１６ｂの検出結果から負荷１０
ａ，１０ｂそれぞれの負荷異常を検出するとともに、電
圧検出回路１８の検出結果から電源異常を検出する。The CPU 19 of the load protection circuit 23 protects the loads 10a and 10b from the respective load abnormalities and power supply abnormalities by commonly using the detection results of the voltage detection circuit 18 for detecting power supply abnormalities of the loads 10a and 10b. That is, C
The abnormality detection means of the PU 19 is the current detection circuits 16a and 16b.
monitor the detection results of the voltage detection circuit 18 and the detection results of the voltage detection circuit 18;
From the detection results of both current detection circuits 16a and 16b, the load 10
In addition to detecting load abnormalities in each of a and 10b, a power supply abnormality is detected from the detection result of the voltage detection circuit 18.
【００３７】さらに、ＣＰＵ１９の制御処理手段は負荷
１０ａ，１０ｂそれぞれの負荷異常，電源異常の情報の
メモリ２０への書込み，読出しを行うとともに、負荷１
０ａ，１０ｂにつき、メモリ２０から読出された情報と
異常検出手段の負荷異常，電源異常の検出結果とに基づ
き、第１，第２の実施例の場合と同様の手法でスイッチ
素子１５のオン，オフ及びメモリ２０の書込み，読出し
を行う。そして、電圧検出回路１８の検出結果を共用す
るとともに１個のＣＰＵ１９，メモリ２０を用いた簡素
かつ安価で小型な構成により、２個の負荷１０ａ，１０
ｂの保護が行える。Further, the control processing means of the CPU 19 writes and reads information on load abnormalities and power supply abnormalities of the loads 10a and 10b to and from the memory 20.
0a and 10b, the switch element 15 is turned on and off in the same manner as in the first and second embodiments based on the information read from the memory 20 and the detection results of load abnormality and power supply abnormality by the abnormality detection means. Turns off and writes and reads data in the memory 20. By sharing the detection results of the voltage detection circuit 18 and using a simple, inexpensive, and compact configuration using one CPU 19 and memory 20, the two loads 10a and 10
b) can be protected.
【００３８】しかも、負荷１０ａ，１０ｂ毎にスイッチ
素子１５を設けるため、負荷１０ａ，１０ｂそれぞれの
負荷異常が発生しても、正常な負荷１０ｂ又は１０ａは
給電される利点がある。そして、負荷をＮ個としたとき
も、電源検出回路と給電スイッチ回路はＮ個要するが、
電圧検出回路１８，ＣＰＵ１９，メモリ２０はそれぞれ
１個設ければよい。なお、第２の実施例のようにゼロク
ロス回路を付加して形成してもよいのは勿論である。Moreover, since the switching element 15 is provided for each of the loads 10a and 10b, there is an advantage that even if a load abnormality occurs in each of the loads 10a and 10b, power is supplied to the normal load 10b or 10a. Even when the number of loads is N, N power supply detection circuits and N power supply switch circuits are required.
One voltage detection circuit 18, one CPU 19, and one memory 20 may be provided. Note that, of course, a zero-cross circuit may be added and formed as in the second embodiment.
【００３９】[0039]
【発明の効果】本発明は、以上説明したように構成され
ているため、以下に記載する効果を奏する。まず、請求
項１の構成の場合は、給電遮断用のスイッチ素子１５だ
けでなく、電流検出回路１６，電圧検出回路１８が交流
電源側，すなわち負荷１０の１次側に設けられ、しかも
、保護回路専用の電源回路１７の給電により、異常検出
手段，制御処理手段が負荷から給電されることなく、メ
モリ２０の保持情報及び両検出回路１６，１８の検出結
果に基づいて負荷異常，電源異常の発生を判別し、交流
電源の投入時は両異常のいずれも発生していないときの
みスイッチ素子１５をオンして給電し、給電中は両異常
のいずれかの発生によりスイッチ素子をオフして負荷の
給電を自動的に遮断したため、回路全体が前記１次側に
設けられ、従来の絶縁回路が不要になるとともに、沿面
距離，空間距離が不要になり、簡素かつ安価で小型な構
成により、負荷１０を交流電源から絶縁分離した状態で
異常から保護することができる。[Effects of the Invention] Since the present invention is configured as described above, it produces the effects described below. First, in the case of the configuration of claim 1, not only the switch element 15 for cutting off the power supply, but also the current detection circuit 16 and the voltage detection circuit 18 are provided on the AC power supply side, that is, on the primary side of the load 10, and furthermore, the protection By supplying power to the power supply circuit 17 dedicated to the circuit, the abnormality detection means and control processing means are not supplied with power from the load, and detect load abnormalities and power supply abnormalities based on the information held in the memory 20 and the detection results of both detection circuits 16 and 18. When turning on the AC power supply, the switch element 15 is turned on and power is supplied only when neither of the two abnormalities occurs, and during power supply, when either of the two abnormalities occurs, the switch element 15 is turned off and the load is turned off. Since the power supply is automatically cut off, the entire circuit is installed on the primary side, eliminating the need for conventional insulation circuits, creepage distances, and clearance distances. 10 can be protected from abnormalities by insulating and separating it from the AC power source.
【００４０】また、請求項２の構成の場合は、交流電源
側，すなわち各負荷１０ａ，１０ｂの１次側の１個の電
圧検出回路１８の検出結果を各負荷１０ａ，１０ｂにつ
いての電源異常の検出に共用し、しかも、１個のＣＰＵ
１９の異常検出手段，制御処理手段により、メモリ２０
の保持情報及び負荷１０ａ，１０ｂ毎の前記１次側の電
流検出回路１６ａ，１６ｂ，電圧検出回路１８の検出結
果に基づき、各負荷１０ａ，１０ｂそれぞれの負荷異常
，電源異常の発生を判別して各負荷１０ａ，１０ｂのス
イッチ素子１５をオンし、給電中は両異常のいずれかの
発生によりそれぞれのスイッチ素子をオフして給電を自
動的に遮断するため、回路全体を前記１次側に設け、し
かも、負荷の個数によらず電圧検出回路１８，ＣＰＵ１
９，メモリ２０をそれぞれ１個だけ設ければよく、極め
て簡単かつ安価で小型な構成により、複数の負荷１０ａ
，１０ｂを交流電源から絶縁した状態で，他の負荷１０
ｂ，１０ａの給電に影響を与えることなく、それぞれ異
常から保護することができる。Further, in the case of the configuration of claim 2, the detection result of one voltage detection circuit 18 on the AC power supply side, that is, on the primary side of each load 10a, 10b, is used to detect power supply abnormality for each load 10a, 10b. Commonly used for detection, and one CPU
19 abnormality detection means and control processing means, the memory 20
Based on the retained information and the detection results of the primary side current detection circuits 16a, 16b and voltage detection circuit 18 for each load 10a, 10b, it is determined whether a load abnormality or power supply abnormality has occurred in each load 10a, 10b. The entire circuit is provided on the primary side in order to turn on the switch elements 15 of each load 10a and 10b, and turn off the respective switch elements when either of the two abnormalities occurs during power supply to automatically cut off the power supply. , and the voltage detection circuit 18 and CPU 1 regardless of the number of loads.
9. It is only necessary to provide one memory 20 for each, and the configuration is extremely simple, inexpensive, and compact, and multiple loads 10a
, 10b are insulated from the AC power supply, and other loads 10
It is possible to protect each of them from abnormalities without affecting the power supply to the terminals b and 10a.
【図１】本発明の負荷保護回路の第１の実施例の結線図
である。FIG. 1 is a wiring diagram of a first embodiment of a load protection circuit of the present invention.
【図２】図１の詳細な結線図である。FIG. 2 is a detailed wiring diagram of FIG. 1;
【図３】本発明の第２の実施例のブロック図である。FIG. 3 is a block diagram of a second embodiment of the invention.
【図４】本発明の第３の実施例のブロック図である。FIG. 4 is a block diagram of a third embodiment of the invention.
【図５】従来例のブロック図である。FIG. 5 is a block diagram of a conventional example.
９ 電源プラグ
１０，１０ａ，１０ｂ 負荷
１１，１１ａ，１１ｂ 安定化電源回路１４，１４ａ
，１４ｂ １次側交流ライン１５ スイッチ素子
１６，１６ａ，１６ｂ 電流検出回路１７ 保護回
路専用の電源回路
１８ 電圧検出回路
１９ ＣＰＵ
２０ メモリ9 Power plug 10, 10a, 10b Load 11, 11a, 11b Stabilized power supply circuit 14, 14a
, 14b Primary AC line 15 Switch elements 16, 16a, 16b Current detection circuit 17 Power supply circuit dedicated to protection circuit 18 Voltage detection circuit 19 CPU 20 Memory
Claims (2)
動用の安定化電源回路に交流電源が供給される負荷を、
前記交流電源から絶縁分離した状態で負荷異常，電源異
常に基づく過電流，過電圧を検出して前記両異常から保
護する負荷保護回路において、前記交流電源と前記安定
化電源回路との間の１次側交流ラインに挿入された給電
遮断用のスイッチ素子と、前記１次側交流ラインの電流
を検出する電流検出回路と、前記交流電源の電圧を検出
する電圧検出回路と、前記両検出回路の検出結果を監視
して前記両異常それぞれの発生を検出する異常検出手段
と、前記異常検出手段の検出情報が書込まれてリセット
されるまで保持する不揮発性のメモリと、前記検出情報
及び前記メモリの保持情報に基づき，前記交流電源の投
入時は前記両異常のいずれでもない状態を判別したとき
のみ前記スイッチ素子をオンし，前記交流電源の供給中
は前記両異常のいずれかの発生により前記スイッチ素子
をオフするとともに前記検出情報を前記メモリに書込む
制御処理手段と、前記交流電源が供給されて前記両手段
等に駆動電源を与える保護回路専用の電源回路とを備え
たことを特徴とする負荷保護回路。[Claim 1] A load to which AC power is supplied to a stabilized power supply circuit for driving in which the primary side and the secondary side are insulated and separated,
In the load protection circuit that detects load abnormality, overcurrent, and overvoltage due to power abnormality in a state insulated and separated from the AC power supply, and protects from both abnormalities, a primary circuit between the AC power supply and the stabilizing power supply circuit is provided. A switch element for cutting off the power supply inserted into the side AC line, a current detection circuit that detects the current of the primary side AC line, a voltage detection circuit that detects the voltage of the AC power supply, and detection of both of the detection circuits. an abnormality detection means that monitors the results and detects the occurrence of each of the above-mentioned abnormalities; a nonvolatile memory that retains the detection information of the abnormality detection means until it is written and reset; and a non-volatile memory that stores the detection information and the memory. Based on the retained information, when the AC power is turned on, the switch element is turned on only when it is determined that neither of the above abnormalities occurs, and while the AC power is being supplied, the switch element is turned on when either of the above abnormalities occurs. The device is characterized by comprising a control processing means for turning off the element and writing the detection information into the memory, and a power supply circuit dedicated to a protection circuit to which the alternating current power is supplied and which provides driving power to both the means and the like. Load protection circuit.
動用の安定化電源回路に交流電源が供給される複数の負
荷を、それぞれ前記交流電源から絶縁分離した状態で負
荷異常，電源異常に基づく過電流，過電圧を検出して前
記両異常から保護する負荷保護回路において、前記交流
電源と前記各負荷の前記安定化電源回路との間の各１次
側交流ラインに挿入された複数の給電遮断用のスイッチ
素子と、前記各１次側交流ラインそれぞれの電流を検出
する複数の電流検出回路と、前記交流電源の電圧を検出
する電圧検出回路と、前記各負荷それぞれの前記両異常
の検出情報が書込まれてリセットされるまで保持する不
揮発性のメモリと、異常検出及び前記メモリ，前記スイ
ッチ素子の制御を行うマイクロコンピュータと、前記交
流電源が供給されて前記両手段等に駆動電源を与える保
護回路専用の電源回路とを備え、前記マイクロコンピュ
ータに、前記各電流検出回路及び前記電圧検出回路の検
出結果を監視して前記各負荷の前記両異常それぞれの発
生を検出する異常検出手段と、前記異常検出手段の前記
各負荷の検出情報及び前記メモリの前記各負荷の保持情
報に基づき，前記交流電源の投入時は前記各負荷の前記
両異常のいずれでもない状態を判別したときのみ前記各
スイッチ素子それぞれをオンし，前記交流電源の供給中
は前記各負荷の前記両異常のいずれかの発生により前記
各スイッチ素子それぞれをオフするとともに前記各負荷
それぞれの前記検出情報を前記メモリに書込む制御処理
手段とを設けたことを特徴とする負荷保護回路。2. A plurality of loads to which AC power is supplied to a stabilizing power supply circuit for driving in which the primary side and the secondary side are insulated and separated from each other are isolated from the AC power supply when the load abnormality occurs. In a load protection circuit that detects overcurrent and overvoltage caused by a power supply abnormality and protects from both of the above abnormalities, the load protection circuit is inserted into each primary side AC line between the AC power supply and the stabilizing power supply circuit of each of the loads. a plurality of switch elements for cutting off the power supply; a plurality of current detection circuits that detect the currents of the respective primary side AC lines; a voltage detection circuit that detects the voltage of the AC power supply; and the voltage detection circuits of the respective loads. a non-volatile memory in which abnormality detection information is written and held until reset; a microcomputer that detects the abnormality and controls the memory and the switch element; a power supply circuit dedicated to a protection circuit for supplying driving power, and the microcomputer is configured to monitor detection results of the current detection circuit and the voltage detection circuit to detect the occurrence of each of the two abnormalities in each of the loads. Based on the detecting means, the detection information of the respective loads of the abnormality detecting means, and the information held for each of the loads in the memory, it is determined that each of the loads is in a state that is neither of the above abnormalities when the AC power source is turned on. Each of the switching elements is turned on only when the AC power is being supplied, and each of the switching elements is turned off when either of the two abnormalities occurs in each of the loads, and the detection information of each of the loads is A load protection circuit comprising a control processing means for writing into a memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3157632A JPH04355627A (en) | 1991-05-31 | 1991-05-31 | Load protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3157632A JPH04355627A (en) | 1991-05-31 | 1991-05-31 | Load protective circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04355627A true JPH04355627A (en) | 1992-12-09 |
Family
ID=15653969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3157632A Pending JPH04355627A (en) | 1991-05-31 | 1991-05-31 | Load protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04355627A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011680A (en) * | 1996-01-19 | 2000-01-04 | Siemens Ag | Connector, in particular a plug-in connector for TT and TN networks |
| US6034447A (en) * | 1996-01-19 | 2000-03-07 | Siemens Ag | Connector for consumer networks |
| CN106712640A (en) * | 2015-11-12 | 2017-05-24 | 发那科株式会社 | Motor drive apparatus |
-
1991
- 1991-05-31 JP JP3157632A patent/JPH04355627A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011680A (en) * | 1996-01-19 | 2000-01-04 | Siemens Ag | Connector, in particular a plug-in connector for TT and TN networks |
| US6034447A (en) * | 1996-01-19 | 2000-03-07 | Siemens Ag | Connector for consumer networks |
| CN106712640A (en) * | 2015-11-12 | 2017-05-24 | 发那科株式会社 | Motor drive apparatus |
| JP2017093190A (en) * | 2015-11-12 | 2017-05-25 | ファナック株式会社 | Motor drive device having abnormality determination function of main power supply voltage |
| US10122316B2 (en) | 2015-11-12 | 2018-11-06 | Fanuc Corporation | Motor drive apparatus having function for determining abnormality of main power supply voltage |
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