JPH043532A - Agc control circuit - Google Patents
Agc control circuitInfo
- Publication number
- JPH043532A JPH043532A JP10554190A JP10554190A JPH043532A JP H043532 A JPH043532 A JP H043532A JP 10554190 A JP10554190 A JP 10554190A JP 10554190 A JP10554190 A JP 10554190A JP H043532 A JPH043532 A JP H043532A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- control signal
- control
- variable gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims abstract 2
- 230000002238 attenuated effect Effects 0.000 abstract description 6
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 230000007257 malfunction Effects 0.000 abstract description 6
- 230000001052 transient effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、メタリックケーブルを用いたディジタル伝
送におけるＡＧＣ制御回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AGC control circuit in digital transmission using a metallic cable.
伝送路の線路損失のために出力信号は減衰した信号とな
る。この減衰した信号を高速に自動等化するためにＡＧ
Ｃ制御回路が必要となる。The output signal becomes an attenuated signal due to line loss in the transmission line. AG is used to automatically equalize this attenuated signal at high speed.
A C control circuit is required.
第４図は、例えば特公平１−１３２５０号公報に示され
た従来のＡ ｃ、 Ｃ＠御回路である。この図において
、１は伝送路で減衰した信号を入力する入力端子、２は
可変利得アンプ、３は前記可変利得アンプ２からの等化
信号８を出力する出力端子、４は前記等化信号８の出力
が一定のしきい値を越えるかどうかを判定する判定回路
、５は前記可変利得アンプ２の伝達特性を制御する制御
回路、７は入力信号、９は判定信号、１ｏは制御信号、
１２はゲート回路、１３は制御回路駆動信号、１４はタ
イマ駆動信号、１６は一定時間前記制御回路駆動信号１
３を禁止するための禁止信号、］５は前記タイマ駆動信
号１４を受信して禁止信号１６を一定時間送信するため
のタイマ回路である。FIG. 4 shows a conventional A c, C @ control circuit shown in, for example, Japanese Patent Publication No. 1-13250. In this figure, 1 is an input terminal for inputting a signal attenuated by the transmission path, 2 is a variable gain amplifier, 3 is an output terminal for outputting an equalized signal 8 from the variable gain amplifier 2, and 4 is an output terminal for outputting the equalized signal 8 from the variable gain amplifier 2. 5 is a control circuit that controls the transfer characteristic of the variable gain amplifier 2; 7 is an input signal; 9 is a judgment signal; 1o is a control signal;
12 is a gate circuit, 13 is a control circuit drive signal, 14 is a timer drive signal, and 16 is the control circuit drive signal 1 for a certain period of time.
[3] is a timer circuit for receiving the timer drive signal 14 and transmitting the prohibition signal 16 for a certain period of time.
また、第５図は、第４図の各信号（タイマ駆動信号１４
は除く）の波形図である。In addition, FIG. 5 shows each signal in FIG. 4 (timer drive signal 14
(excluding).
次に、動作を第４図、第５図によって説明する。Next, the operation will be explained with reference to FIGS. 4 and 5.
伝送路の線路損失によって減衰した入力信号７（第５図
（ａ））を入力端子１より入力し、可変利得アンプ２に
よってこの線路損失分を補償し、等化信号８（第５図（
Ｃ））を出力端子３より出力する。判定回路４は、等化
信号８がある一定のしきい値以上か否かを判定し、しき
い値以上であれば判定信号９（第５図（ｄ））を送信す
る。この時ゲート回路１２に入力される禁止信号１６（
第５図（ｅ））が“Ｌ”ならデー１〜回路１２は制御回
路駆動信号１３（第５図（ｆ））を送信し、制御回路５
はこれを受信すると制御信号１０（第５図（ｂ））を送
信し、可変利得アンプ２の伝達特性を切り換えて所望の
等化信号８を得る。The input signal 7 (Fig. 5(a)) attenuated by the line loss of the transmission line is input from the input terminal 1, and the variable gain amplifier 2 compensates for this line loss, and the equalized signal 8 (Fig. 5(a)) is inputted from the input terminal 1.
C)) is output from output terminal 3. The determination circuit 4 determines whether the equalized signal 8 is equal to or greater than a certain threshold value, and if it is equal to or greater than the threshold value, transmits a determination signal 9 (FIG. 5(d)). At this time, the prohibition signal 16 (
If the signal 1 (e) in FIG.
Upon receiving this, it transmits a control signal 10 (FIG. 5(b)), switches the transfer characteristic of the variable gain amplifier 2, and obtains a desired equalized signal 8.
次に、タイマ回路１５を使用する理由を説明する。可変
利得アンプ２は制御信号１０（第５図（ｂ））によって
コンデンサや抵抗値を切り換えるので、それによってス
イッチングノイズが生じて（第５図（ｅ）） 、判定回
路４はこのノイズによって誤った判定をしてしまう（第
５図（ｄ））それを防ぐためにタイマ回路１５によって
禁止信号１６（第５図（ｅ））を一定時間送信して、判
定信号９（第５図（ｄ））からノイズを除去した制卸回
路駆動信号１３（第５図（ｆ））を制御回路５に送信し
、誤動作しないＡＧｃｉｌＪｔｆ１１１回路を得ている
。Next, the reason for using the timer circuit 15 will be explained. Since the variable gain amplifier 2 switches the capacitor and resistance values according to the control signal 10 (Fig. 5 (b)), switching noise is generated (Fig. 5 (e)), and the judgment circuit 4 is caused to make errors due to this noise. In order to prevent the judgment from occurring (Fig. 5(d)), the timer circuit 15 transmits the prohibition signal 16 (Fig. 5(e)) for a certain period of time, and the judgment signal 9 (Fig. 5(d)) is transmitted. The control circuit drive signal 13 (FIG. 5(f)) from which noise has been removed is transmitted to the control circuit 5, thereby obtaining an AGcilJtf111 circuit that does not malfunction.
従来のＡＧＣ制御回路は以上のように構成されているの
で、タイマ回路１５やゲー）−回路１２を設けなければ
ならず、回路が複雑になるなどの問題点があった。Since the conventional AGC control circuit is constructed as described above, it is necessary to provide a timer circuit 15 and a game circuit 12, which causes problems such as the circuit becoming complicated.
この発明は、上記のような問題点を解消するためになさ
れたもので、簡単な回路構成で過度的な雑音によるフィ
ルタの誤動作を防止できるＡＧＣ制御回路を得ることを
目的とする。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an AGC control circuit that can prevent malfunction of a filter due to excessive noise with a simple circuit configuration.
この発明に係るＡＧＣ制御回路は、制御回路から送信さ
れる制Ｗ信号を波形成形してスイッチングノイズが発生
しにくい波形としてから可変利得アンプに送出する制御
信号調整回路を設けたものである。The AGC control circuit according to the present invention is provided with a control signal adjustment circuit that shapes the waveform of a control signal transmitted from the control circuit to create a waveform in which switching noise is less likely to occur, and then sends the waveform to a variable gain amplifier.
この発明におけるＡＧｃｔＪＪＩ！１回路は、制御回路
から送信される制御信号をゆるやかに立ち上げることに
より過度的な雑音を低減させ、ＡＧＣ制御回路の誤動作
を防ぐ。AGctJJI in this invention! The first circuit reduces excessive noise by gently rising the control signal transmitted from the control circuit, thereby preventing malfunction of the AGC control circuit.
以下、乙の発明の一実施例を図面について説明する。 An embodiment of the invention of B will be described below with reference to the drawings.
第１図はこの発明の一実施例を示すＡ、 Ｇ Ｃ制御回
路のブロック図である。この図ζｒおいて、第４図と同
一符号は同一構成部分を示し、６は前記制御信号１０の
信号の立ち上がりを調整する制御信号調整回路、１１は
その調整制御信号である。第２図は、第１図における各
信号の波形図である。FIG. 1 is a block diagram of an A, GC control circuit showing an embodiment of the present invention. In this figure ζr, the same reference numerals as in FIG. 4 indicate the same components, 6 is a control signal adjustment circuit for adjusting the rise of the control signal 10, and 11 is the adjustment control signal. FIG. 2 is a waveform diagram of each signal in FIG. 1.
次に、上記実施例の動作を第１図、第２図を参照して説
明する。Next, the operation of the above embodiment will be explained with reference to FIGS. 1 and 2.
伝送路によって減衰した入力信号７（第２図（ａ））が
入力端子１より入力され、可変利得アンプ２によってこ
の線路損失分を補償し、等化信号８（第２図（ｄ））を
出力端子３より出力する。The input signal 7 (Fig. 2 (a)) attenuated by the transmission line is input from the input terminal 1, and the variable gain amplifier 2 compensates for this line loss to generate an equalized signal 8 (Fig. 2 (d)). Output from output terminal 3.
判定回路４は、等化信号８がある一定のしきい値以上か
否かを判定し、しきい値以上であると、判定信号９（第
２図（ｅ））を送イ８し、制御回路５はこれを受信して
制御信号１０（第２図（ｂ））を送信する。しかし、こ
の信号のままであると可変利得アップ２内の伝達特性を
切り換える際、スイッチング５ノイズが発生しく第２図
（ｄ）） 、それが判定回路４のしきい値を越えると誤
った判定をしＣしまうので、制御信号１０（第２図（ｂ
））を−度制御イ３号調整回路６に入力して、信号の立
ち上がりをゆるやかｔζすることによって（第２図（Ｃ
）） このノイズを低減させて誤動作しないようにし７
ている。制御信号調整回路６は、例えば第３図に示すよ
うにコンデンサ１個で簡単に実現できる。The determination circuit 4 determines whether the equalized signal 8 is equal to or greater than a certain threshold value, and if it is equal to or greater than the threshold value, it sends a determination signal 9 (FIG. 2(e)) to control the The circuit 5 receives this and transmits a control signal 10 (FIG. 2(b)). However, if this signal remains as it is, switching noise will occur when switching the transfer characteristics in variable gain up 2 (Fig. 2 (d)), and if it exceeds the threshold of judgment circuit 4, an incorrect judgment will occur. Since the control signal 10 (Fig. 2(b)
)) is input to the -degree control A3 adjustment circuit 6, and the rise of the signal is gradually tζ (Fig. 2 (C)).
)) Reduce this noise to prevent malfunction7
ing. The control signal adjustment circuit 6 can be easily realized with one capacitor, for example, as shown in FIG.
なお、上記実施例では１つの制御信号についての場合を
示したが、複数の刷部イ１号の場合であってもよく、上
記実施例と同様の効果を奏する。In addition, although the case with one control signal was shown in the said Example, the case with a plurality of printing parts A1 may be sufficient, and the same effect as the said Example is produced.
以上説明したように、この発明は、ディジクルの制御信
号によって利得を切り換える可変利得アンプと、この可
変利得アンプの出力信号と所定のしきい値を比較２判定
する判定回路と、この判定回路の出力信号によって利得
制御信号を生成する刷部回路と、利得制御信号の波形成
形を行い波形成形された利得制御信号を可変利得アンプ
に送出する制御信号調整回路とを備えたので、フィルタ
の伝達特性切換え時の雑音による回路全体の誤動作を、
制御信号のみを調整することによって防ぐことができ、
少ない部品数で安価で精度の高いＡＧＣ制御回路を得ら
れる効果がある。As explained above, the present invention provides a variable gain amplifier whose gain is switched by a digital control signal, a determination circuit that compares the output signal of the variable gain amplifier with a predetermined threshold value, and an output of the determination circuit. Equipped with a printing circuit that generates a gain control signal based on the signal, and a control signal adjustment circuit that shapes the waveform of the gain control signal and sends the waveformed gain control signal to the variable gain amplifier, it is easy to change the transfer characteristics of the filter. The malfunction of the entire circuit due to noise during
can be prevented by adjusting only the control signal,
This has the effect of providing an inexpensive and highly accurate AGC control circuit with a small number of parts.
第１図はこの発明の一実施例によるＡＧＣ制御回路の回
路構成を示すブロック図、第２図は、第１図における各
信号の波形図、第３図は制御信号調整回路の回路図、第
４図は従来のＡＧＣ制御回路の回路構成を示すブロック
図、第５図は、第４図の各信号の波形図である。
図において、１は入力端子、２は可変利得アンプ、３は
出力端子、４は判定回路、５は制御回路、６は制御信号
調整回路、７は入力信号、８は等化信号、９は判定信号
、１０は制御信号、１１は調整制御信号である。
なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a block diagram showing the circuit configuration of an AGC control circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each signal in FIG. 1, FIG. 3 is a circuit diagram of a control signal adjustment circuit, and FIG. FIG. 4 is a block diagram showing the circuit configuration of a conventional AGC control circuit, and FIG. 5 is a waveform diagram of each signal in FIG. 4. In the figure, 1 is an input terminal, 2 is a variable gain amplifier, 3 is an output terminal, 4 is a judgment circuit, 5 is a control circuit, 6 is a control signal adjustment circuit, 7 is an input signal, 8 is an equalization signal, and 9 is a judgment 10 is a control signal, and 11 is an adjustment control signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
得アンプと、この可変利得アンプの出力信号と所定のし
きい値を比較、判定する判定回路と、この判定回路の出
力信号によって利得制御信号を生成する制御回路と、利
得制御信号の波形成形を行い波形成形された利得制御信
号を前記可変利得アンプに送出する制御信号調整回路と
を備えたことを特徴とするＡＧＣ制御回路。A variable gain amplifier whose gain is switched by a digital control signal, a judgment circuit which compares and judges the output signal of this variable gain amplifier with a predetermined threshold value, and a control circuit which generates a gain control signal from the output signal of this judgment circuit. and a control signal adjustment circuit that performs waveform shaping of a gain control signal and sends the waveform-shaped gain control signal to the variable gain amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10554190A JPH043532A (en) | 1990-04-19 | 1990-04-19 | Agc control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10554190A JPH043532A (en) | 1990-04-19 | 1990-04-19 | Agc control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH043532A true JPH043532A (en) | 1992-01-08 |
Family
ID=14410448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10554190A Pending JPH043532A (en) | 1990-04-19 | 1990-04-19 | Agc control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043532A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008220223A (en) * | 2007-03-09 | 2008-09-25 | Mitsubishi Agricult Mach Co Ltd | Device for raising up reaping and harvesting machine |
-
1990
- 1990-04-19 JP JP10554190A patent/JPH043532A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008220223A (en) * | 2007-03-09 | 2008-09-25 | Mitsubishi Agricult Mach Co Ltd | Device for raising up reaping and harvesting machine |
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