JPH04350967A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPH04350967A JPH04350967A JP3152560A JP15256091A JPH04350967A JP H04350967 A JPH04350967 A JP H04350967A JP 3152560 A JP3152560 A JP 3152560A JP 15256091 A JP15256091 A JP 15256091A JP H04350967 A JPH04350967 A JP H04350967A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- gate electrode
- effect transistor
- gate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims description 15
- 230000008018 melting Effects 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 18
- 238000009825 accumulation Methods 0.000 abstract 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 239000010936 titanium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910017920 NH3OH Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体記憶装置に関し、
特に、ゲート電極の配線抵抗を減らし、信号遅延を小さ
くするためにポリサイドゲートを使用したスタックト型
キャパシタを備えた半導体記憶装置に関する。[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to a semiconductor memory device equipped with a stacked capacitor using a polycide gate to reduce wiring resistance of gate electrodes and signal delay.
【0002】0002
【従来の技術】図11,図12は従来のスタックト型キ
ャパシタセルを有するダイナミック・ランダム・アクセ
ス・メモリ(Dynamic Random Ac
cessMemory、以下、DRAMという)の構造
を示す縦断面図である。図11はメモリセル部を、図1
2は周辺回路部をそれぞれ示している。2. Description of the Related Art FIGS. 11 and 12 show a conventional dynamic random access memory (Dynamic Random Access Memory) having stacked capacitor cells.
FIG. 2 is a vertical cross-sectional view showing the structure of cessMemory (hereinafter referred to as DRAM). Figure 11 shows the memory cell section.
Reference numerals 2 and 2 respectively indicate peripheral circuit sections.
【0003】図において、1は半導体基板、2はフィー
ルド酸化膜、3はゲート酸化膜、4はゲートポリシリコ
ン膜、5は不純物拡散層、6は層間絶縁膜、7は容量蓄
積電極、8は容量絶縁膜、9は容量対向電極、10は高
融点金属シリサイド膜、11は層間絶縁膜、12はビッ
ト線、13は層間絶縁膜、14はアルミ配線をそれぞれ
示している。In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate polysilicon film, 5 is an impurity diffusion layer, 6 is an interlayer insulating film, 7 is a capacitor storage electrode, and 8 is a capacitor storage electrode. A capacitive insulating film, 9 a capacitive counter electrode, 10 a refractory metal silicide film, 11 an interlayer insulating film, 12 a bit line, 13 an interlayer insulating film, and 14 an aluminum wiring.
【0004】この従来のDRAMでは、メモリセル部の
トランジスタ及び周辺回路部のトランジスタはゲート電
極の低抵抗化を図るために高融点金属シリサイド膜10
とポリシリコン膜4とを積層したシリサイド構造のゲー
ト電極を備えている。In this conventional DRAM, the transistors in the memory cell section and the transistors in the peripheral circuit section are coated with a high melting point metal silicide film 10 in order to reduce the resistance of the gate electrode.
The gate electrode has a silicide structure in which a polysilicon film 4 and a polysilicon film 4 are laminated.
【0005】[0005]
【発明が解決しようとする課題】この従来の半導体記憶
装置では、ゲートポリシリコン膜4の膜厚は、ゲート酸
化膜の耐圧及び信頼性の劣化を起こさないという条件で
下限が決まり、また、高融点金属シリサイド膜10の膜
厚は、ポリサイドゲート電極の抵抗値が回路設計上許容
できる範囲となるように下限が決まる。[Problems to be Solved by the Invention] In this conventional semiconductor memory device, the lower limit of the film thickness of the gate polysilicon film 4 is determined on the condition that the withstand voltage and reliability of the gate oxide film are not deteriorated. The lower limit of the thickness of the melting point metal silicide film 10 is determined so that the resistance value of the polycide gate electrode falls within an allowable range in terms of circuit design.
【0006】例えば、ゲートポリシリコン膜4の膜厚が
1500オングストローム以上で、高融点金属シリサイ
ド膜10の膜厚が1000オングストローム以上必要だ
とすると、ポリサイドゲート電極の合計膜厚は2500
オングストローム以上になる。この場合、メモリセルの
占有面積を例えば4平方ミクロン以下にしようとすると
、メモリセル内のゲート電極間の配線間隔は0.5μm
以下にしなければならず、微細加工が困難になるという
問題点があった。For example, if the thickness of the gate polysilicon film 4 is 1,500 angstroms or more, and the refractory metal silicide film 10 is required to have a thickness of 1,000 angstroms or more, the total thickness of the polycide gate electrode is 2,500 angstroms or more.
angstrom or more. In this case, if the area occupied by the memory cell is to be 4 microns or less, the wiring interval between the gate electrodes in the memory cell is 0.5 μm.
There was a problem that microfabrication became difficult.
【0007】例えば、スタックト型キャパシタを有する
メモリセルでは、容量蓄積電極7を異方性ドライエッチ
ングにより加工するが、ゲート電極の膜厚が厚ければ厚
いほど、ゲート電極の側壁に沿ってエッチング残渣が生
じやすくなり、上述のようにゲート電極の間隙が狭くな
ると、微細加工不良によるエッチング残渣が不良品を発
生させていた。For example, in a memory cell having a stacked capacitor, the capacitance storage electrode 7 is processed by anisotropic dry etching, but the thicker the gate electrode, the more etching residue is formed along the sidewalls of the gate electrode. When the gap between the gate electrodes narrows as described above, etching residue due to poor microfabrication causes defective products.
【0008】[0008]
【課題を解決するための手段】本発明の要旨は、半導体
基板上に電界効果型トランジスタと該電界効果トランジ
スタのゲート電極上に蓄積電極を有する容量体で構成さ
れるメモリセルと、該メモリセルの情報へのアクセスを
図る周辺回路とを形成した半導体記憶装置において、上
記メモリセルの電界効果型トランジスタのゲート電極を
多結晶シリコン膜のみで形成し、上記周辺回路を構成す
る電界効果トランジスタのゲート電極を多結晶シリコン
膜と高融点金属シリサイド膜とを積層したポリサイド構
造にしたことである。[Means for Solving the Problems] The gist of the present invention is to provide a memory cell comprising a field effect transistor on a semiconductor substrate and a capacitor having a storage electrode on the gate electrode of the field effect transistor; In a semiconductor memory device in which a peripheral circuit for accessing information of the memory cell is formed, the gate electrode of the field effect transistor of the memory cell is formed only of a polycrystalline silicon film, and the gate electrode of the field effect transistor constituting the peripheral circuit is The electrode has a polycide structure in which a polycrystalline silicon film and a high melting point metal silicide film are laminated.
【0009】[0009]
【発明の作用】周辺回路を構成する電界効果トランジス
タのゲート電極は厚くても微細加工の不良には結び付か
ないので、信号伝達の高速化をポリサイド構造にして図
る。Effects of the Invention Even if the gate electrode of the field effect transistor constituting the peripheral circuit is thick, it will not lead to defects in microfabrication, so a polycide structure is used to increase the speed of signal transmission.
【0010】一方、メモリセルの電界効果トランジスタ
のゲートは、多結晶シリコン膜のみで形成されており、
膜厚を薄くできるので、上方に蓄積電極を設けても正確
に微細加工することができる。On the other hand, the gate of the field effect transistor of the memory cell is formed only from a polycrystalline silicon film.
Since the film thickness can be reduced, accurate microfabrication can be performed even if a storage electrode is provided above.
【0011】[0011]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
【0012】図1,図2は本発明の第1実施例に係る半
導体記憶装置の断面図である。図1はメモリセル部を、
図2は周辺回路部を示している。FIGS. 1 and 2 are cross-sectional views of a semiconductor memory device according to a first embodiment of the present invention. Figure 1 shows the memory cell section.
FIG. 2 shows the peripheral circuit section.
【0013】図において1は半導体基板、2はフィール
ド酸化膜、3はゲート酸化膜、4はゲートポリシリコン
膜、5は不純物拡散層、6,11,13は層間絶縁膜、
7は容量蓄積電極、8は容量絶縁膜、9は容量対向電極
、10は高融点金属シリサイド膜、12はビット線、1
4はアルミ配線をそれぞれ示している。In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate polysilicon film, 5 is an impurity diffusion layer, 6, 11, 13 are interlayer insulating films,
7 is a capacitor storage electrode, 8 is a capacitor insulating film, 9 is a capacitor counter electrode, 10 is a high melting point metal silicide film, 12 is a bit line, 1
4 indicates aluminum wiring.
【0014】周辺回路部では、回路動作上抵抗による信
号遅延の影響が大きいので、電界効果トランジスタ10
0のゲート電極は低抵抗化のためにゲートポリシリコン
膜4と高融点金属シリサイド膜10からなるポリサイド
構造をしており、メモリセル部の電界効果トランジスタ
101はゲート電極の段差を低減し加工しやすいように
ゲートポリシリコン膜4のみでゲート電極を形成してい
る。図3〜図6は第1実施例に係る半導体記憶装置を形
成するための主要工程を示す断面図である。In the peripheral circuit section, since signal delay due to resistance has a large effect on circuit operation, the field effect transistor 10
The gate electrode of 0 has a polycide structure consisting of a gate polysilicon film 4 and a high melting point metal silicide film 10 to reduce resistance, and the field effect transistor 101 in the memory cell part is processed to reduce the step difference in the gate electrode. For simplicity, the gate electrode is formed only from the gate polysilicon film 4. 3 to 6 are cross-sectional views showing the main steps for forming the semiconductor memory device according to the first embodiment.
【0015】まず、図3に示すようにシリコン等の半導
体基板1の所定の領域を選択酸化法により酸化してフィ
ールド酸化膜2を形成し、続いてゲート酸化膜4、さら
に、多結晶シリコンからなるゲートポリシリコン膜4、
例えばタングステンシリサイドからなる高融点金属シリ
サイド10を順次形成する。First, as shown in FIG. 3, a predetermined region of a semiconductor substrate 1 made of silicon or the like is oxidized by a selective oxidation method to form a field oxide film 2, followed by a gate oxide film 4 and then a polycrystalline silicon film. A gate polysilicon film 4,
Refractory metal silicide 10 made of tungsten silicide, for example, is sequentially formed.
【0016】もちろんチタン(Ti)、モリブデン(M
o)、白金(Pt)等、他の高融点金属のシリサイドも
使用できる。Of course, titanium (Ti), molybdenum (M
o) Silicides of other high melting point metals such as platinum (Pt) can also be used.
【0017】次に、図4に示すように周辺回路部のみレ
ジスト15で覆う。Next, as shown in FIG. 4, only the peripheral circuit portion is covered with a resist 15.
【0018】次に、図5に示すように、例えば反応性イ
オンエッチング(R.I.E)を用いてメモリセル部の
高融点貴族シリサイド10をエッチング除去する。Next, as shown in FIG. 5, the high melting point noble silicide 10 in the memory cell portion is etched away using, for example, reactive ion etching (R.I.E.).
【0019】続いて、図6に示すようにフォトリソグラ
フィ法を用いてゲート電極のレジストパターン16を形
成後、R.I.Eにより高融点金属シリサイド10及び
ゲートポリシリコン4をエッチングしてゲート電極を形
成する。Subsequently, as shown in FIG. 6, after forming a resist pattern 16 for the gate electrode using photolithography, the R.I. I. The high melting point metal silicide 10 and gate polysilicon 4 are etched using E to form a gate electrode.
【0020】その後、不純物拡散層5、容量素子部、コ
ンタクト、ビット線12、アルミ配線14などを順次形
成して、図1,図2に示す半導体記憶装置の構造を得る
。Thereafter, the impurity diffusion layer 5, the capacitive element section, the contact, the bit line 12, the aluminum wiring 14, etc. are sequentially formed to obtain the structure of the semiconductor memory device shown in FIGS. 1 and 2.
【0021】図7〜図10は本発明の第2実施例の主要
工程を示す縦断面図である。FIGS. 7 to 10 are longitudinal sectional views showing the main steps of a second embodiment of the present invention.
【0022】第1実施例と同様に半導体基板1上にフィ
ールド酸化膜2、ゲート絶縁膜3、ゲートポリシリコン
4を形成後、図7に示すように全体に酸化膜17を例え
ばCVD法により形成する。レジスト15をマスクとし
て周辺回路部のみドライエッチングあるいは弗化水素酸
(HF)によるウェットエッチングにより酸化膜17を
除去する。After forming a field oxide film 2, a gate insulating film 3, and a gate polysilicon 4 on a semiconductor substrate 1 in the same manner as in the first embodiment, an oxide film 17 is formed on the entire surface by, for example, the CVD method, as shown in FIG. do. Using the resist 15 as a mask, the oxide film 17 is removed only from the peripheral circuit portion by dry etching or wet etching using hydrofluoric acid (HF).
【0023】次いで図8に示すようにレジスト15を除
去後、例えばタングステン(W)やチタン(Ti)等の
高融点金属18をスパッタ法により形成した後に、赤外
線ランプを用いたランプアニールにより高融点金属18
とゲートポリシリコン4とを反応させポリシリコン化を
させる。この時、酸化膜上の高融点金属18はシリサイ
ド化せず未反応のタングステン(W)またはチタン(T
i)のまま残る。Next, as shown in FIG. 8, after removing the resist 15, a high melting point metal 18 such as tungsten (W) or titanium (Ti) is formed by sputtering, and then a high melting point metal 18 is formed by lamp annealing using an infrared lamp. metal 18
and gate polysilicon 4 are reacted to form polysilicon. At this time, the refractory metal 18 on the oxide film is not silicided and remains unreacted, such as tungsten (W) or titanium (T).
i) remains.
【0024】次に、図9に示すように未反応の高融点金
属18(タングステンまたはチタン)は例えばアンモニ
ア水(NH3OH)と過酸化水素(H2O2)の混合液
や弗化水素酸(HF)によりエッチング除去する。さら
に酸化膜17を弗化水素酸(HF)により除去する。Next, as shown in FIG. 9, the unreacted high melting point metal 18 (tungsten or titanium) is treated with, for example, a mixed solution of aqueous ammonia (NH3OH) and hydrogen peroxide (H2O2) or hydrofluoric acid (HF). Remove by etching. Furthermore, the oxide film 17 is removed using hydrofluoric acid (HF).
【0025】その後、フォトリソグラフィ法により、ゲ
ート電極のレジストパターン16を形成する(図10)
。Thereafter, a resist pattern 16 for the gate electrode is formed by photolithography (FIG. 10).
.
【0026】その後、第1実施例と同様にしてゲート電
極、容量素子部、ビット線12、コンタクト、アルミ配
線14などを形成して図1,図2に示す半導体記憶装置
を完成する。Thereafter, gate electrodes, capacitor elements, bit lines 12, contacts, aluminum interconnections 14, etc. are formed in the same manner as in the first embodiment to complete the semiconductor memory device shown in FIGS. 1 and 2.
【0027】[0027]
【発明の効果】以上説明したように本発明は、周辺回路
部ではゲート電極を高融点金属シリサイド10とゲート
ポリシリコン4とのポリサイド構造とし、メモリセル部
では高融点金属シリサイド10を除いてゲートポリシリ
コン4での形成することにより、周辺回路部ではゲート
抵抗を下げることができ、回路動作の高速化が図れると
同時に、メモリセル部ではゲート電極の段差を低減する
ことができるので、スタックト型キャパシタセルの容量
蓄積電極7などの加工が容易になる。As explained above, in the present invention, the gate electrode in the peripheral circuit part has a polycide structure of high melting point metal silicide 10 and gate polysilicon 4, and in the memory cell part, the gate electrode has a polycide structure of high melting point metal silicide 10 and gate polysilicon 4. By forming polysilicon 4, it is possible to lower the gate resistance in the peripheral circuit area, increasing the speed of circuit operation, and at the same time, reducing the step difference in the gate electrode in the memory cell area, making it possible to reduce the gate resistance in the peripheral circuit area. This facilitates processing of the capacitance storage electrode 7 of the capacitor cell.
【図1】第1実施例のメモリセル部を示す断面図である
。FIG. 1 is a cross-sectional view showing a memory cell portion of a first embodiment.
【図2】第1実施例の周辺回路部を示す断面図である。FIG. 2 is a sectional view showing a peripheral circuit section of the first embodiment.
【図3】第1実施例の構造を得る製造方法の第1工程を
示す断面図である。FIG. 3 is a cross-sectional view showing the first step of the manufacturing method for obtaining the structure of the first example.
【図4】第1実施例の構造を得る製造方法の第2工程を
示す断面図である。FIG. 4 is a cross-sectional view showing the second step of the manufacturing method for obtaining the structure of the first embodiment.
【図5】第1実施例の構造を得る製造方法の第3工程を
示す断面図である。FIG. 5 is a sectional view showing the third step of the manufacturing method for obtaining the structure of the first example.
【図6】第1実施例の構造を得る製造方法の第4工程を
示す断面図である。FIG. 6 is a sectional view showing the fourth step of the manufacturing method for obtaining the structure of the first example.
【図7】第1実施例の構造を得る他の製造方法の第1工
程を示す断面図である。FIG. 7 is a sectional view showing the first step of another manufacturing method for obtaining the structure of the first embodiment.
【図8】第1実施例の構造を得る他の製造方法の第2工
程を示す断面図である。FIG. 8 is a cross-sectional view showing the second step of another manufacturing method for obtaining the structure of the first embodiment.
【図9】第1実施例の構造を得る他の製造方法の第3工
程を示す断面図である。FIG. 9 is a sectional view showing the third step of another manufacturing method for obtaining the structure of the first embodiment.
【図10】第1実施例の構造を得る他の製造方法の第4
工程を示す断面図である。FIG. 10: Fourth example of another manufacturing method for obtaining the structure of the first embodiment.
It is a sectional view showing a process.
【図11】従来例のメモリセル部を示す断面図である。FIG. 11 is a cross-sectional view showing a conventional memory cell section.
【図12】従来例の周辺回路部を示す断面図である。FIG. 12 is a sectional view showing a peripheral circuit section of a conventional example.
1 半導体基板2 フィールド酸化膜3 ゲート
酸化膜
4 ゲートポリシリコン
5 不純物拡散層
6 層間絶縁膜
7 容量蓄積電極
8 容量絶縁膜
9 容量対向電極
10 高融点金属シリサイド
11 層間絶縁膜
12 ビット線
13 層間絶縁膜
14 アルミ配線
15,16 レジスト
17 酸化膜
18 高融点金属1 Semiconductor substrate 2 Field oxide film 3 Gate oxide film 4 Gate polysilicon 5 Impurity diffusion layer 6 Interlayer insulating film 7 Capacitive storage electrode 8 Capacitive insulating film 9 Capacitive counter electrode 10 Refractory metal silicide 11 Interlayer insulating film 12 Bit line 13 Interlayer insulation Film 14 Aluminum wiring 15, 16 Resist 17 Oxide film 18 High melting point metal
Claims (1)
タと該電界効果トランジスタのゲート電極上に蓄積電極
を有する容量体で構成されるメモリセルと、該メモリセ
ルの情報へのアクセスを図る周辺回路とを形成した半導
体記憶装置において、上記メモリセルの電界効果型トラ
ンジスタのゲート電極を多結晶シリコン膜のみで形成し
、上記周辺回路を構成する電界効果トランジスタのゲー
ト電極を多結晶シリコン膜と高融点金属シリサイド膜と
を積層したポリサイド構造にしたことを特徴とする半導
体記憶装置。1. A memory cell comprising a field effect transistor on a semiconductor substrate and a capacitor having a storage electrode on the gate electrode of the field effect transistor, and a peripheral circuit for accessing information in the memory cell. In the semiconductor memory device in which the field effect transistor of the memory cell is formed, the gate electrode of the field effect transistor is formed only of a polycrystalline silicon film, and the gate electrode of the field effect transistor constituting the peripheral circuit is formed of a polycrystalline silicon film and a high melting point metal. A semiconductor memory device characterized by having a polycide structure in which a silicide film is laminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3152560A JPH04350967A (en) | 1991-05-28 | 1991-05-28 | Semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3152560A JPH04350967A (en) | 1991-05-28 | 1991-05-28 | Semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04350967A true JPH04350967A (en) | 1992-12-04 |
Family
ID=15543149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3152560A Pending JPH04350967A (en) | 1991-05-28 | 1991-05-28 | Semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04350967A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9275618B2 (en) | 2012-10-15 | 2016-03-01 | Universite Pierre Et Marie Curie (Paris 6) | Haptic controller suitable for controlling a sound characteristic |
-
1991
- 1991-05-28 JP JP3152560A patent/JPH04350967A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9275618B2 (en) | 2012-10-15 | 2016-03-01 | Universite Pierre Et Marie Curie (Paris 6) | Haptic controller suitable for controlling a sound characteristic |
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