JPH04346477A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04346477A JPH04346477A JP3119918A JP11991891A JPH04346477A JP H04346477 A JPH04346477 A JP H04346477A JP 3119918 A JP3119918 A JP 3119918A JP 11991891 A JP11991891 A JP 11991891A JP H04346477 A JPH04346477 A JP H04346477A
- Authority
- JP
- Japan
- Prior art keywords
- well
- mos
- peripheral
- semiconductor substrate
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 230000002093 peripheral effect Effects 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims description 19
- 239000000969 carrier Substances 0.000 abstract description 19
- 238000011084 recovery Methods 0.000 abstract description 15
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 22
- 230000003071 parasitic effect Effects 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 239000002344 surface layer Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 101150015217 FET4 gene Proteins 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- -1 Boron ions Chemical class 0.000 description 1
- 101150073536 FET3 gene Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、パワーＭＯＳＦＥＴを
有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a power MOSFET.
【０００２】0002
【従来の技術】パワーＭＯＳＦＥＴは、周波数特性が優
れ、スイッチングスピードが速く、かつ低電力で駆動で
きる等多くの特徴を有することから、近年多くの産業分
野で使用されている。たとえば、日経ＢＰ社発行「日経
エレクトロニクス」１９８６年５月１９日号、Ｐ１６５
〜Ｐ１８８には、パワーＭＯＳＦＥＴをＨ型ブリッジに
組んでモータを駆動する例、ＭＯＳＦＥＴとバイポーラ
・トランジスタをカスケード接続してモータを駆動する
例が示されている。前者の場合では、内蔵ダイオードの
逆回復時間を短くしてフリーホイール・ダイオードに使
い、後者の場合ではターンオン・スナバが保護回路とし
て使用されている。また、この文献には、解説コラムに
おいて、内蔵ダイオードの逆回復時間についての説明が
ある。この欄では、Ｈ型ブリッジ回路において、モータ
オフ時に、パワーＭＯＳＦＥＴの内蔵ダイオードを通っ
てモータ電流が還流（回生）する現象について説明され
ている。また、同文献には、「内蔵ダイオードの逆回復
時間を減らすには，ダイオード部のｎ− エピタキシャ
ル層の少数キャリヤ・ライフタイムを短くすればよい。
これには重金属をドープしたり，電子線や陽子を照射す
る方法がある。」と記載され、以後メーカ各社の対処方
法が記述されている。一方、縦型のパワーＭＯＳＦＥＴ
の構造については、たとえば特開昭６３−３１１７６６
号公報，特開昭６２−７６６７１号公報，特願平１−１
４６８１４号公報に開示されている。特願平１−１４６
８１４号公報には、荷電粒子としての正孔がｐウェルに
流れ込む現象について説明されている。2. Description of the Related Art Power MOSFETs have been used in many industrial fields in recent years because they have excellent frequency characteristics, high switching speed, and can be driven with low power. For example, "Nikkei Electronics" May 19, 1986 issue, published by Nikkei BP, P165.
~P188 shows an example in which power MOSFETs are assembled into an H-type bridge to drive a motor, and an example in which a MOSFET and a bipolar transistor are connected in cascade to drive a motor. In the former case, the internal diode's reverse recovery time is shortened and used as a freewheeling diode, while in the latter case a turn-on snubber is used as a protection circuit. This document also includes an explanation about the reverse recovery time of the built-in diode in the commentary column. This column describes a phenomenon in which motor current circulates (regenerates) through a built-in diode of a power MOSFET when the motor is off in an H-type bridge circuit. The same document also states that ``In order to reduce the reverse recovery time of the built-in diode, it is possible to shorten the minority carrier lifetime of the n- epitaxial layer in the diode section. There is a method of irradiating protons,'' and the countermeasures taken by each manufacturer are described below. On the other hand, vertical power MOSFET
Regarding the structure of
Publication No. 62-76671, Japanese Patent Application No. 1-1
It is disclosed in Japanese Patent No. 46814. Patent application Hei 1-146
No. 814 describes a phenomenon in which holes as charged particles flow into a p-well.
【０００３】0003
【発明が解決しようとする課題】従来のｎチャネル縦型
パワーＭＯＳＦＥＴは、図７および図８に示されるよう
な構造となっている。図７は半導体基体の主面に多数設
けられるＭＯＳＦＥＴセルと、これらＭＯＳＦＥＴセル
群の周辺部、すなわちチップ周辺部の一部を示す模式的
断面図である。シリコンからなる半導体基体１はドレイ
ン（Ｄ）を構成する。半導体基体１はｎ＋ 形となると
ともに、その主面は一定厚さのｎ− 形のエピタキシャ
ル層２により形成されている。前記半導体基体１の表層
部には、ｐ形からなる多数のＭＯＳ部ウェル３と、これ
らＭＯＳ部ウェル３の周辺に延在するｐ形からなる周辺
ウェル４が設けられる。周辺ウェル４は、ＦＬＲ（フィ
ールド・リミッティング・リング）を構成したり、ある
いはワイヤボンディングパッド下に設けられる。前記半
導体基体１の主面には、厚い絶縁膜（フィールド絶縁膜
）６および薄い絶縁膜（ゲート酸化膜）７が選択的に設
けられている。このゲート酸化膜７は、前記ＭＯＳ部ウ
ェル３の表層部に設けられたｎ＋ 形のソース（Ｓ）領
域１０と、隣接する周辺ウェル４のソース領域１０間に
亘って設けられ、その上にはゲート（Ｇ）電極１１が配
設されている。したがって、前記ゲート電極１１に所定
の電圧が印加されると、前記周辺ウェル４の外側のエピ
タキシャル層２とソース領域１０との間の表層部がチャ
ネルとなり、ソース・ドレイン間に電流が流れる。また
、前記半導体基体１とＭＯＳ部ウェル３および周辺ウェ
ル４との間には、ダイオード（内蔵ダイオード）１２が
形成される。また、図８に示すように、ＭＯＳ部ウェル
３においては、前記ソース領域１０，ＭＯＳ部ウェル３
，エピタキシャル層２によって寄生バイポーラトランジ
スタ１５が形成される。なお、同図中１７は層間絶縁膜
、１９はソース電極、２０はゲート配線層、２１はソー
ス配線層、２２はドレイン電極である。A conventional n-channel vertical power MOSFET has a structure as shown in FIGS. 7 and 8. FIG. 7 is a schematic cross-sectional view showing a large number of MOSFET cells provided on the main surface of a semiconductor substrate and a peripheral part of a group of these MOSFET cells, that is, a part of a chip peripheral part. The semiconductor substrate 1 made of silicon constitutes a drain (D). The semiconductor substrate 1 is of n+ type, and its main surface is formed by an n- type epitaxial layer 2 having a constant thickness. A large number of p-type MOS wells 3 and a p-type peripheral well 4 extending around the MOS wells 3 are provided in the surface layer of the semiconductor substrate 1 . The peripheral well 4 constitutes an FLR (field limiting ring) or is provided under a wire bonding pad. A thick insulating film (field insulating film) 6 and a thin insulating film (gate oxide film) 7 are selectively provided on the main surface of the semiconductor substrate 1. This gate oxide film 7 is provided between the n+ type source (S) region 10 provided in the surface layer part of the MOS section well 3 and the source region 10 of the adjacent peripheral well 4, and is A gate (G) electrode 11 is provided. Therefore, when a predetermined voltage is applied to the gate electrode 11, the surface layer between the epitaxial layer 2 outside the peripheral well 4 and the source region 10 becomes a channel, and a current flows between the source and drain. Furthermore, a diode (built-in diode) 12 is formed between the semiconductor substrate 1 and the MOS section well 3 and peripheral well 4. Further, as shown in FIG. 8, in the MOS part well 3, the source region 10, the MOS part well 3
, a parasitic bipolar transistor 15 is formed by the epitaxial layer 2. In the figure, 17 is an interlayer insulating film, 19 is a source electrode, 20 is a gate wiring layer, 21 is a source wiring layer, and 22 is a drain electrode.
【０００４】このようなパワーＭＯＳＦＥＴの内蔵ダイ
オードを、モータ制御等において回生電流回路に積極的
に使用する場合、Ｈ型ブリッジ回路では、上アームのト
ランジスタがオンすると、下アームのトランジスタ中の
内蔵ダイオードが短絡状態となり、破壊し易くなること
から、ユーザではスナバー回路等の保護回路が必要であ
った。図９は、ＦＥＴ１ ，ＦＥＴ２ ，ＦＥＴ３ ，
ＦＥＴ４ なる４個のパワーＭＯＳＦＥＴをＨ型ブリッ
ジ回路に組み込んでモータ制御を行う例を示すものであ
る。この回路において、上アームのＦＥＴ１ と下アー
ムのＦＥＴ４ をオンさせると、モータ（Ｍ）２５には
二点鎖線で示すように電流Ａが流れてモータ２５が駆動
する。モータ２５の速度を制御するために、上アームの
ＦＥＴ１ をオンからオフに切り換えると、点線で示さ
れるようにモータ電流Ｂは、下アームのＦＥＴ２ の内
蔵ダイオード１２を通って還流（回生）する。このとき
、パワーＭＯＳＦＥＴにおいては、図７に示すようにＭ
ＯＳ部ウェル３および周辺ウェル４から半導体基体１に
荷電粒子の正孔（ホール）２７が注入される。つぎに、
再び上アームのＦＥＴ１ がオンされると、下アームの
ＦＥＴ２ には電源電圧が掛かるため、内蔵ダイオード
１２に蓄積されていた過剰キャリア（ホール２７）は、
矢印のようにホール電流２９となってＭＯＳ部ウェル３
および周辺ウェル４に掃き出される。この過剰キャリア
が掃き出される時間が逆回復時間ｔｒｒとなる。また、
この過剰キャリアの掃き出し状態下ではＦＥＴ２ は短
絡状態となり、破壊し易くなる。When the built-in diode of such a power MOSFET is actively used in a regenerative current circuit for motor control, etc., in an H-type bridge circuit, when the upper arm transistor is turned on, the built-in diode in the lower arm transistor is turned on. Since the circuit becomes short-circuited and is easily destroyed, the user needs a protection circuit such as a snubber circuit. FIG. 9 shows FET1, FET2, FET3,
This figure shows an example in which four power MOSFETs called FET4 are incorporated into an H-type bridge circuit to control a motor. In this circuit, when FET1 in the upper arm and FET4 in the lower arm are turned on, current A flows through the motor (M) 25 as shown by the two-dot chain line, and the motor 25 is driven. To control the speed of the motor 25, when the upper arm FET1 is switched from on to off, the motor current B flows back (regenerated) through the built-in diode 12 of the lower arm FET2, as shown by the dotted line. At this time, in the power MOSFET, as shown in FIG.
Charged particle holes 27 are injected into the semiconductor substrate 1 from the OS section well 3 and the peripheral well 4 . next,
When the upper arm FET1 is turned on again, the power supply voltage is applied to the lower arm FET2, so the excess carriers (holes 27) accumulated in the built-in diode 12 are
As shown by the arrow, it becomes a hole current 29 and flows into the MOS part well 3.
and swept out into the peripheral well 4. The time taken for this excess carrier to be swept out is the reverse recovery time trr. Also,
Under this condition where excess carriers are swept out, FET2 becomes short-circuited and becomes easily destroyed.
【０００５】従来のこの種パワーＭＯＳＦＥＴは、その
製造においてＭＯＳＦＥＴが形成されるＭＯＳ部ウェル
３と、ＭＯＳＦＥＴ群の周辺に設けられる周辺ウェル４
は、同時に形成されるため不純物濃度は同一となる。一
方、前述のようにＭＯＳＦＥＴ部には寄生バイポーラト
ランジスタ１５が形成される。したがって、この寄生バ
イポーラトランジスタ１５を動作させないようにするた
め、従来ＭＯＳ部ウェル３の不純物濃度を高くし、これ
によって寄生バイポーラトランジスタ１５のベース抵抗
を小さくする手段が採用されている。この結果、従来製
品ではパワーＭＯＳＦＥＴの周辺ウェル４の不純物濃度
も高くなり、ＦＥＴ１ オフ時のモータ電流Ｂによる半
導体基体１内へのキャリア（ホール２７）の注入量が増
大し、蓄積キャリアも増大する。したがって、キャリア
の掃き出しに時間が掛り、逆回復時間ｔｒｒ、が増大し
てスイッチング時間が長くなり、ロスタイムが増大する
。また、蓄積されたキャリアが、前記ＭＯＳ部ウェル３
や周辺ウェル４に流れ込む際に、電位差が高くなって寄
生バイポーラトランジスタ１５がオンし、これによって
ＭＯＳＦＥＴを破壊に至らしめることにもなる。In manufacturing this kind of conventional power MOSFET, a MOS part well 3 in which the MOSFET is formed and a peripheral well 4 provided around the MOSFET group are used.
are formed at the same time, so their impurity concentrations are the same. On the other hand, as described above, the parasitic bipolar transistor 15 is formed in the MOSFET section. Therefore, in order to prevent this parasitic bipolar transistor 15 from operating, a conventional method has been adopted in which the impurity concentration of the MOS section well 3 is increased, thereby reducing the base resistance of the parasitic bipolar transistor 15. As a result, in the conventional product, the impurity concentration in the peripheral well 4 of the power MOSFET also increases, the amount of carriers (holes 27) injected into the semiconductor substrate 1 by the motor current B when the FET 1 is off increases, and the accumulated carriers also increase. . Therefore, it takes time to sweep out the carriers, the reverse recovery time trr increases, the switching time becomes longer, and the loss time increases. Further, the accumulated carriers are transferred to the well 3 of the MOS section.
When flowing into the peripheral well 4, the potential difference becomes high and the parasitic bipolar transistor 15 is turned on, thereby causing destruction of the MOSFET.
【０００６】本発明者は、従来の技術では、ＭＯＳＦＥ
Ｔにおける寄生バイポーラトランジスタの動作抑制のた
めに、周辺ウェルまでも不純物濃度を濃くしたことに問
題があると考え、さらにＭＯＳＦＥＴ群の周辺部に設け
られる周辺ウェルには、寄生バイポーラトランジスタが
形成されないことから、ＭＯＳ部ウェルの不純物濃度よ
りも不純物濃度を低くでき、これによって面積的に大き
い周辺ウェルから半導体基体に注入されるキャリア量を
抑えることができる点に着目し、本発明を成した。[0006] The present inventor has discovered that in the prior art, MOSFE
In order to suppress the operation of the parasitic bipolar transistor in T, we believe that there is a problem in increasing the impurity concentration even to the peripheral well, and furthermore, we believe that the parasitic bipolar transistor is not formed in the peripheral well provided in the peripheral area of the MOSFET group. The present invention was developed by focusing on the fact that the impurity concentration can be lower than that of the MOS well, thereby suppressing the amount of carriers injected into the semiconductor substrate from the peripheral well, which is large in area.
【０００７】本発明の目的は、パワーＭＯＳＦＥＴにお
ける内蔵ダイオードの逆回復時間の低減を図ることにあ
る。An object of the present invention is to reduce the reverse recovery time of a built-in diode in a power MOSFET.
【０００８】本発明の他の目的は、パワーＭＯＳＦＥＴ
における内蔵ダイオードの破壊耐量の向上を図ることに
ある。Another object of the present invention is to provide a power MOSFET.
The purpose is to improve the breakdown resistance of the built-in diode.
【０００９】本発明の前記ならびにそのほかの目的と新
規な特徴は、本明細書の記述および添付図面からあきら
かになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
【００１０】0010
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。すなわち、本発明の縦型パワーＭＯ
ＳＦＥＴにあっては、その製造においてＭＯＳ部ウェル
および周辺ウェルは相互に独立した工程によって形成さ
れ、かつ周辺ウェルの不純物濃度はＭＯＳ部ウェルの不
純物濃度よりも低くなっている。[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, the vertical power MO of the present invention
In manufacturing an SFET, a MOS part well and a peripheral well are formed in mutually independent steps, and the impurity concentration of the peripheral well is lower than that of the MOS part well.
【００１１】[0011]
【作用】上記した手段によれば、本発明の縦型パワーＭ
ＯＳＦＥＴは、周辺ウェルの不純物濃度はＭＯＳ部ウェ
ルの不純物濃度よりも一桁低くなっていることから、Ｍ
ＯＳＦＥＴの内蔵ダイオードに順方向電流が流れた際、
周辺ウェルから半導体基体に注入されるホールの量は大
幅に少なくなる。特に周辺ウェルはその面積が各ＭＯＳ
部ウェルに比較して大幅に大きいため、周辺ウェルに近
接した最外周のＭＯＳ部ウェルの周辺近傍に蓄積される
ホール量は、従来に比較して少なくなる。この結果、内
蔵ダイオードの逆回復時間ｔｒｒが短縮されてスイッチ
ングの高速化が図れるとともに、破壊耐量も向上する。[Operation] According to the above-mentioned means, the vertical power M of the present invention
Since the impurity concentration in the peripheral well of the OSFET is one order of magnitude lower than that in the MOS well, the M
When forward current flows through the built-in diode of the OSFET,
The amount of holes injected into the semiconductor body from the peripheral well is significantly reduced. In particular, the area of the peripheral well is
Since the holes are significantly larger than the peripheral wells, the amount of holes accumulated near the periphery of the outermost MOS well near the peripheral wells is smaller than in the past. As a result, the reverse recovery time trr of the built-in diode is shortened, switching speed can be increased, and breakdown resistance is also improved.
【００１２】0012
【実施例】以下図面を参照して本発明の一実施例につい
て説明する。図１は本発明によるパワーＭＯＳＦＥＴの
要部を示す模式的断面図、図２は同じくＭＯＳ部ウェル
および周辺ウェルの配置を示す模式的平面図、図３〜図
６は同じく本発明のパワーＭＯＳＦＥＴの製造各工程に
おける模式的断面図であって、図３は周辺ウェルが製造
された半導体基体の一部の断面図、図４はＭＯＳ部ウェ
ルが製造された半導体基体の断面図、図５はゲート酸化
膜が製造された半導体基体の断面図、図６はソース電極
が製造された半導体基体の断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the main parts of a power MOSFET according to the present invention, FIG. 2 is a schematic plan view showing the arrangement of a MOS part well and a peripheral well, and FIGS. FIG. 3 is a cross-sectional view of a part of the semiconductor substrate in which the peripheral well has been manufactured, FIG. 4 is a cross-sectional view of the semiconductor substrate in which the MOS part well has been manufactured, and FIG. 5 is a schematic cross-sectional view of each manufacturing step. FIG. 6 is a cross-sectional view of a semiconductor substrate on which an oxide film has been manufactured, and FIG. 6 is a cross-sectional view of a semiconductor substrate on which a source electrode has been manufactured.
【００１３】この実施例では、単体のパワーＭＯＳＦＥ
Ｔに本発明を適用した例について説明する。本発明の縦
型パワーＭＯＳＦＥＴを構成する半導体素子（チップ）
３５は、所定の厚さを有する矩形板構造となっている。
半導体素子３５においては、多数のＭＯＳ部ウェル３と
、これらＭＯＳＦＥＴ群を取り囲む周辺ウェル４のレイ
アウトは図２のようになっている。ハッチングで示され
る領域が周辺ウェル４となり、この矩形部分がフィール
ド・リミッティング・リング（ＦＬＲ）３６となる。
また、このＦＬＲ３６の両側内側には矩形状に一部張り
出した矩形領域３７が設けられている。これら矩形領域
３７の上方にはゲートやソース用のワイヤボンディング
パッドが形成される。また、前記周辺ウェル４に取り囲
まれる領域に点在する微小矩形体がＭＯＳ部ウェル３で
ある。In this embodiment, a single power MOSFE
An example in which the present invention is applied to T will be explained. Semiconductor element (chip) constituting the vertical power MOSFET of the present invention
35 has a rectangular plate structure having a predetermined thickness. In the semiconductor element 35, the layout of a large number of MOS part wells 3 and a peripheral well 4 surrounding these MOSFET groups is as shown in FIG. The hatched region becomes the peripheral well 4, and this rectangular portion becomes the field limiting ring (FLR) 36. Furthermore, rectangular regions 37 are provided on both sides of the FLR 36, with a portion thereof extending in a rectangular shape. Wire bonding pads for gates and sources are formed above these rectangular regions 37. Further, minute rectangular bodies scattered in a region surrounded by the peripheral well 4 are MOS section wells 3.
【００１４】図１はＭＯＳ部ウェル３および周辺ウェル
４の一部を示す模式的断面図である。縦型パワーＭＯＳ
ＦＥＴは、図１に示されるように、導電型がｎ形（ｎ＋
形）となるシリコンの半導体基体１の主面に、前記の
レイアウト通りにいずれも導電型がｐ形となるＭＯＳ部
ウェル３および周辺ウェル４が形成されている。半導体
基体１の主面にはｎ− 形のエピタキシャル層２が設け
られていることから、前記ＭＯＳ部ウェル３および周辺
ウェル４は、このエピタキシャル層２の表層部に形成さ
れることになる。前記ＭＯＳ部ウェル３および周辺ウェ
ル４はその深さが４〜６μｍ程度となっている。FIG. 1 is a schematic cross-sectional view showing a part of the MOS section well 3 and peripheral well 4. As shown in FIG. Vertical power MOS
As shown in FIG. 1, the FET has n-type conductivity (n+
A MOS part well 3 and a peripheral well 4, both of which have p-type conductivity, are formed on the main surface of a silicon semiconductor substrate 1 having a shape (type) according to the layout described above. Since the n- type epitaxial layer 2 is provided on the main surface of the semiconductor substrate 1, the MOS well 3 and the peripheral well 4 are formed in the surface layer of the epitaxial layer 2. The depth of the MOS section well 3 and the peripheral well 4 is about 4 to 6 μm.
【００１５】前記ＭＯＳ部ウェル３および周辺ウェル４
は、後述するようにそれぞれ独立した工程によって形成
されるため、同じ深さである必要はなく、特性に対応し
てそれぞれ選択すればよい。前記ＭＯＳ部ウェル３はそ
の不純物濃度が１０１９ｃｍ−３程度となりｐ＋ 形を
形成し、寄生バイポーラトランジスタのベースとなるＭ
ＯＳ部ウェル３の抵抗、すなわちベース抵抗が増大しな
いようになっている。これによって動作時、寄生バイポ
ーラトランジスタが動作するようなことはなくなる。ま
た、前記周辺ウェル４はその不純物濃度が５×１０１６
ｃｍ−３程度以下と低くなりｐ− 形を構成し、内蔵ダ
イオード１２に順方向電流が流れた際、周辺ウェル４か
ら半導体基体１に注入されるキャリア（ホール２７）の
量が、前記ＭＯＳ部ウェル３から半導体基体１に注入さ
れるキャリア量よりも大幅に少なくなるように構成され
ている。これによって、ＭＯＳ部ウェル３や周辺ウェル
４の周辺に蓄積されたホール２７が、ＭＯＳ部ウェル３
や周辺ウェル４にホール電流２９となって掃き出される
際、蓄積キャリアが従来に比較して大幅に少なくなるた
め、掃き出し時間、すなわち逆回復時間ｔｒｒが短縮さ
れる。また、蓄積キャリアが少ないことから内蔵ダイオ
ード１２の破壊も起き難くなり、破壊耐量が向上する。The MOS section well 3 and the peripheral well 4
As will be described later, the depths do not need to be the same since they are formed by independent processes, and may be selected depending on the characteristics. The MOS part well 3 has an impurity concentration of about 1019 cm-3, forming a p+ type, and becomes the base of the parasitic bipolar transistor.
The resistance of the OS section well 3, ie, the base resistance, is prevented from increasing. This prevents the parasitic bipolar transistor from operating during operation. Further, the impurity concentration of the peripheral well 4 is 5×10 16
cm-3 or less, forming a p- type, and when a forward current flows through the built-in diode 12, the amount of carriers (holes 27) injected from the peripheral well 4 into the semiconductor substrate 1 increases. The structure is such that the amount of carriers injected from the well 3 into the semiconductor substrate 1 is significantly smaller. As a result, the holes 27 accumulated around the MOS part well 3 and the peripheral well 4 are removed from the MOS part well 3.
When the carriers are swept out as a hole current 29 in the peripheral well 4, the accumulated carriers are significantly reduced compared to the conventional case, so that the sweep-out time, that is, the reverse recovery time trr is shortened. Furthermore, since there are few accumulated carriers, the built-in diode 12 is less likely to be destroyed, and its destruction resistance is improved.
【００１６】さらに、前記周辺ウェル４に近接するＭＯ
Ｓ部ウェル３、すなわち最外周に位置するＭＯＳ部ウェ
ル３には、ＭＯＳ部ウェル３から半導体基体１に注入さ
れたホール２７に加えて、周辺ウェル４から半導体基体
１に注入されたホール２７も入って来ることになる。周
辺ウェル４はＭＯＳ部ウェル３に比較してその面積が大
幅に広いため、半導体基体１に蓄積される周辺ウェル４
によるホール２７の量も多いが、周辺ウェル４の不純物
濃度がＭＯＳ部ウェル３の不純物濃度に比較して低いこ
とから、周辺ウェル４による蓄積キャリアの量も少なく
なり、周辺ウェル４に近接したＭＯＳ部ウェル３へのキ
ャリアの掃き出し量は少なくなる。この結果、蓄積キャ
リアの戻りに起因するＭＯＳＦＥＴの破壊も防止できる
ことになる。すなわち、図１は、内蔵ダイオード１２の
順方向電流が切れ、ｐｎ接合がバイアスされたため、逆
方向電流が流れている状態を示すものであり、蓄積され
たホール２７が再びｐ（ｐ＋ ，ｐ− ）形であるＭＯ
Ｓ部ウェル３および周辺ウェル４に戻る状態を示す図で
ある。この場合、前記ｐ形領域内のホール電流２９は、
ＭＯＳＦＥＴ部の寄生バイポーラトランジスタのベース
電流となるため、トランジスタがオンする可能性がある
が、周辺ウェル４から半導体基体１に注入されたホール
２７の量は少ないため、周辺ウェル４に隣接するＭＯＳ
ＦＥＴの負担は少なくなり、寄生バイポーラトランジス
タがオンすることは抑止できる。なお、ホール２７およ
びホール電流２９の数は、図１の場合は少なく、図７の
場合は多く示し、従来品と本発明品とが異なることを示
してある。Furthermore, the MO near the peripheral well 4
In the S part well 3, that is, the MOS part well 3 located at the outermost periphery, in addition to the holes 27 injected from the MOS part well 3 into the semiconductor substrate 1, there are also holes 27 injected into the semiconductor substrate 1 from the peripheral well 4. It will come in. Since the area of the peripheral well 4 is significantly larger than that of the MOS part well 3, the peripheral well 4 accumulated in the semiconductor substrate 1
Although the amount of holes 27 due to The amount of carriers swept into the inner well 3 is reduced. As a result, destruction of the MOSFET due to the return of accumulated carriers can also be prevented. That is, FIG. 1 shows a state in which the forward current of the built-in diode 12 is cut off and the pn junction is biased, so that a reverse current is flowing, and the accumulated holes 27 are again p(p+, p- ) shape MO
FIG. 3 is a diagram showing a state of returning to the S part well 3 and the peripheral well 4. FIG. In this case, the hole current 29 in the p-type region is
The base current of the parasitic bipolar transistor in the MOSFET section may turn on the transistor, but since the amount of holes 27 injected from the peripheral well 4 into the semiconductor substrate 1 is small, the MOS adjacent to the peripheral well 4
The load on the FET is reduced, and the parasitic bipolar transistor is prevented from turning on. Note that the number of holes 27 and hole currents 29 are small in the case of FIG. 1 and large in the case of FIG. 7, indicating that the conventional product and the product of the present invention are different.
【００１７】一方、前記半導体基体１の主面には、厚い
絶縁膜（フィールド絶縁膜）６および薄い絶縁膜（ゲー
ト酸化膜）７が選択的に設けられている。このゲート酸
化膜７は、前記ＭＯＳ部ウェル３の表層部に設けられた
ｎ＋ 形のソース（Ｓ）領域１０と、隣接する周辺ウェ
ル４のソース領域１０間に亘って設けられ、その上には
ゲート（Ｇ）電極１１が配設されている。したがって、
前記ゲート電極１１に所定の電圧が印加されると、前記
周辺ウェル４の外側のエピタキシャル層２とソース領域
１０との間の表層部がチャネルとなり、ソース・ドレイ
ン間に電流が流れる。また、前記半導体基体１とＭＯＳ
部ウェル３および周辺ウェル４との間には、ダイオード
（内蔵ダイオード）１２が形成される。また、ＭＯＳ部
ウェル３においては、前記ソース領域１０，ＭＯＳ部ウ
ェル３，エピタキシャル層２によって寄生バイポーラト
ランジスタが形成される。なお、同図中１７は層間絶縁
膜、１９はソース電極、２０はゲート配線層、２１はソ
ース配線層、２２はドレイン電極である。On the other hand, a thick insulating film (field insulating film) 6 and a thin insulating film (gate oxide film) 7 are selectively provided on the main surface of the semiconductor substrate 1. This gate oxide film 7 is provided between the n+ type source (S) region 10 provided in the surface layer part of the MOS section well 3 and the source region 10 of the adjacent peripheral well 4, and is A gate (G) electrode 11 is provided. therefore,
When a predetermined voltage is applied to the gate electrode 11, the surface layer between the epitaxial layer 2 outside the peripheral well 4 and the source region 10 becomes a channel, and a current flows between the source and drain. Further, the semiconductor substrate 1 and the MOS
A diode (built-in diode) 12 is formed between the peripheral well 3 and the peripheral well 4. In the MOS well 3, a parasitic bipolar transistor is formed by the source region 10, the MOS well 3, and the epitaxial layer 2. In the figure, 17 is an interlayer insulating film, 19 is a source electrode, 20 is a gate wiring layer, 21 is a source wiring layer, and 22 is a drain electrode.
【００１８】つぎに、このような縦型パワーＭＯＳＦＥ
Ｔの製造方法について説明する。最初に図３に示すよう
な半導体基体１を用意する。この半導体基体１はｎ＋
形のシリコンからなり、その主面にはｎ− 形のエピタ
キシャル層２が設けられている。このエピタキシャル層
２はその厚さが耐圧によって選択される。このような半
導体基体１に対して酸化処理が行われ、半導体基体１の
主面に絶縁膜（ＳｉＯ２ 膜）４０が選択的に形成され
る。また、絶縁膜４０が設けられない部分には、厚さが
１００〜３００ÅのＳｉＯ２ 膜からなるスルー膜４１
が形成される。その後、半導体基体１の主面には、ボロ
ン（Ｂ）がイオンインプランテーション（イオン注入）
によって注入されかつ拡散される。イオン注入において
は、ドーズ量は１×１０１３ｃｍ−２程度が選択され、
不純物濃度が１×１０１６ｃｍ−３程度となる周辺ウェ
ル４が形成される。これは、前述のように内蔵ダイオー
ド１２に順方向電流が流れた際、面積的に大きな周辺ウ
ェル４から半導体基体１に多量のホール２７が注入され
ないように可及的不純物濃度を低くすることによる。ま
た、前記イオン注入においては、イオンの打ち込み量を
十分小さくできるが、耐圧特性を損なわないための接合
深さを確保する必要から拡散時間は長めとする必要があ
る。Next, such a vertical power MOSFE
The method for manufacturing T will be explained. First, a semiconductor substrate 1 as shown in FIG. 3 is prepared. This semiconductor substrate 1 is n+
It is made of shaped silicon, and an n-type epitaxial layer 2 is provided on its main surface. The thickness of this epitaxial layer 2 is selected depending on the breakdown voltage. Such semiconductor substrate 1 is subjected to oxidation treatment, and an insulating film (SiO2 film) 40 is selectively formed on the main surface of semiconductor substrate 1. In addition, in the part where the insulating film 40 is not provided, a through film 41 made of a SiO2 film with a thickness of 100 to 300 Å is provided.
is formed. After that, boron (B) is ion-implanted onto the main surface of the semiconductor substrate 1.
injected and diffused by In ion implantation, the dose is selected to be about 1×1013 cm-2,
A peripheral well 4 having an impurity concentration of about 1×10 16 cm −3 is formed. This is done by reducing the impurity concentration as much as possible to prevent a large number of holes 27 from being injected into the semiconductor substrate 1 from the peripheral well 4, which has a large area, when a forward current flows through the built-in diode 12 as described above. . Further, in the ion implantation, although the amount of ions implanted can be sufficiently small, the diffusion time needs to be long because it is necessary to ensure a junction depth that does not impair the breakdown voltage characteristics.
【００１９】つぎに、前記絶縁膜４０，スルー膜４１を
除去した後、図４に示すように半導体基体１の主面に再
び選択的に絶縁膜４３を形成する。また、この絶縁膜４
３が設けられない領域、すなわちＭＯＳＦＥＴを形成す
る領域に、厚さ１００〜３００ÅのＳｉＯ２ 膜からな
るスルー膜４４を形成する。ついで、前記半導体基体１
の主面にボロンがイオン注入されるとともに拡散処理が
施される。イオン注入においては、ドーズ量は１×１０
１５ｃｍ−２程度が選択され、不純物濃度が１×１０１
９ｃｍ−３程度となるＭＯＳ部ウェル３が形成される。
ＭＯＳ部ウェル３は、寄生バイポーラトランジスタのベ
ース抵抗低減のために十分濃度を上げる必要があり、拡
散時間は短めの方向で調整する。特性によっても異なる
が、ＭＯＳ部ウェル３の不純物濃度は少なくとも１０１
７ｃｍ−３以上は必要となる。最終的熱履歴後のＭＯＳ
部ウェル３と周辺ウェル４の接合深さは、たとえば４〜
６μｍ程度となるが、同一であっても良いが周辺部の方
を深くすることが特性面から望ましい。Next, after removing the insulating film 40 and the through film 41, an insulating film 43 is selectively formed again on the main surface of the semiconductor substrate 1, as shown in FIG. Moreover, this insulating film 4
A through film 44 made of a SiO2 film with a thickness of 100 to 300 Å is formed in the region where the MOSFET is not provided, that is, in the region where the MOSFET is to be formed. Then, the semiconductor substrate 1
Boron ions are implanted into the main surface and a diffusion process is performed. In ion implantation, the dose is 1×10
About 15cm-2 was selected, and the impurity concentration was 1×101.
A MOS part well 3 having a thickness of about 9 cm -3 is formed. The concentration of the MOS part well 3 must be sufficiently increased to reduce the base resistance of the parasitic bipolar transistor, and the diffusion time is adjusted to be shorter. Although it varies depending on the characteristics, the impurity concentration of the MOS part well 3 is at least 101
7 cm-3 or more is required. MOS after final thermal history
The junction depth between the peripheral well 3 and the peripheral well 4 is, for example, 4 to 4.
The thickness is approximately 6 μm, and although it may be the same, it is desirable from the viewpoint of characteristics that the peripheral portion be deeper.
【００２０】つぎに、前記絶縁膜４３，スルー膜４４を
除去した後、図５に示すように半導体基体１の主面に、
厚い絶縁膜（フィールド絶縁膜）６および薄い絶縁膜（
ゲート絶縁膜）７を選択的に形成する。その後、前記フ
ィールド絶縁膜６およびゲート絶縁膜７上に選択的にゲ
ート電極１１を形成する。Next, after removing the insulating film 43 and the through film 44, as shown in FIG.
A thick insulating film (field insulating film) 6 and a thin insulating film (
A gate insulating film) 7 is selectively formed. Thereafter, a gate electrode 11 is selectively formed on the field insulating film 6 and the gate insulating film 7.
【００２１】つぎに、図６に示すように常用のホトリソ
グラフィおよびイオン注入等によって、それぞれ所望の
拡散領域が形成される。ＭＯＳ部ウェル３にあっては、
ＭＯＳ部ウェル３の表層部に重なるとともに、ＭＯＳ部
ウェル３の周囲から食み出すｐ形領域９、ＭＯＳ部ウェ
ル３の表層部に設けられたｎ＋ 形のソース領域１０が
設けられる。また、周辺ウェル４にあっては、オーミッ
クコンタクト用にｐ＋ 形のコンタクト層１３が設けら
れる。また、前記半導体基体１の主面には、ゲート電極
１１を選択的に被う層間絶縁膜１７が設けられる。また
、所定部分にはソース電極１９，前記コンタクト層１３
に電気的に接続されるソース配線層２１，前記ゲート電
極１１に接続されるゲート配線層２０が設けられる。ま
た、図示はしないが、半導体基体１の主面は所定部分を
パッシベーション膜で被われる。このような半導体基体
１は、その裏面を研削されて所定の厚さにされた後、裏
面にドレイン電極２２が形成されて、半導体基体１に示
されるパワーＭＯＳＦＥＴが製造される。Next, as shown in FIG. 6, desired diffusion regions are formed by conventional photolithography, ion implantation, and the like. In MOS part well 3,
A p-type region 9 overlaps with the surface layer of the MOS well 3 and protrudes from the periphery of the MOS well 3, and an n+ type source region 10 is provided on the surface of the MOS well 3. Further, in the peripheral well 4, a p+ type contact layer 13 is provided for ohmic contact. Further, an interlayer insulating film 17 selectively covering the gate electrode 11 is provided on the main surface of the semiconductor substrate 1 . Further, a source electrode 19 and the contact layer 13 are provided at a predetermined portion.
A source wiring layer 21 electrically connected to the gate electrode 11 and a gate wiring layer 20 connected to the gate electrode 11 are provided. Further, although not shown, a predetermined portion of the main surface of the semiconductor substrate 1 is covered with a passivation film. After the back surface of such a semiconductor substrate 1 is ground to a predetermined thickness, a drain electrode 22 is formed on the back surface, and the power MOSFET shown in the semiconductor substrate 1 is manufactured.
【００２２】このような実施例による本発明によれば、
つぎのような効果が得られる。
（１）本発明の縦型パワーＭＯＳＦＥＴは、ＭＯＳ部ウ
ェルの周辺の周辺ウェルの不純物濃度は低くなっている
ことから、内蔵ダイオードに順方向電流が流れた際の半
導体基体に注入されるホールの量は、従来品に比較して
少なくなり、半導体基体に蓄積されるホール（キャリア
）の量が少なくなるという効果が得られる。According to the present invention according to such an embodiment,
The following effects can be obtained. (1) In the vertical power MOSFET of the present invention, since the impurity concentration of the peripheral well around the MOS part well is low, holes injected into the semiconductor substrate when forward current flows through the built-in diode are reduced. The amount of holes (carriers) accumulated in the semiconductor substrate is reduced compared to conventional products.
【００２３】（２）上記（１）により、本発明の縦型パ
ワーＭＯＳＦＥＴは、内蔵ダイオードの逆回復時におい
て、ＭＯＳ部ウェルや周辺ウェルに戻る蓄積キャリアの
量が少なくなることから、逆回復時間が短縮されスイッ
チング時間が短縮されるという効果が得られる。本発明
によれば、逆回復時間ｔｒｒは当社従来品に比べて約２
０〜３０％短くすることができる。(2) According to (1) above, the vertical power MOSFET of the present invention reduces the amount of accumulated carriers returning to the MOS well and the peripheral well during reverse recovery of the built-in diode, so that the reverse recovery time is reduced. The effect is that the switching time is shortened and the switching time is shortened. According to the present invention, the reverse recovery time trr is approximately 2
It can be shortened by 0-30%.
【００２４】（３）上記（１）により、本発明の縦型パ
ワーＭＯＳＦＥＴは、内蔵ダイオードの逆回復時におい
て、ＭＯＳ部ウェルや周辺ウェルに戻る蓄積キャリアの
量が少なくなることから、内蔵ダイオードの破壊耐量が
向上するという効果が得られる。本発明によれば、破壊
耐量は当社従来品に比べ５倍以上向上できる。(3) According to (1) above, the vertical power MOSFET of the present invention reduces the amount of accumulated carriers that return to the MOS well and the peripheral well during reverse recovery of the built-in diode. The effect of improving fracture resistance can be obtained. According to the present invention, the fracture resistance can be improved by more than 5 times compared to our conventional products.
【００２５】（４）本発明の縦型パワーＭＯＳＦＥＴは
、周辺ウェルから半導体基体に注入されるホールの量が
少ないことから、周辺ウェルに近接するＭＯＳ部ウェル
、すなわち最外周に位置するＭＯＳ部ウェルに戻るホー
ルも少なくなり、周辺ウェルに近接するＭＯＳＦＥＴの
破壊も防止できるという効果が得られる。(4) In the vertical power MOSFET of the present invention, since the amount of holes injected from the peripheral well into the semiconductor substrate is small, the MOS part well adjacent to the peripheral well, that is, the MOS part well located at the outermost periphery, The number of holes returning to the wells is also reduced, and the effect is that destruction of MOSFETs near the peripheral wells can be prevented.
【００２６】（５）上記（１）〜（４）により、本発明
によれば、破壊耐量が高くかつスイッチングスピードが
早い縦型パワーＭＯＳＦＥＴを提供することができると
いう相乗効果が得られる。(5) According to the above (1) to (4), according to the present invention, a synergistic effect can be obtained in that a vertical power MOSFET with high breakdown resistance and high switching speed can be provided.
【００２７】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。図１０は本
発明の他の実施例によるパワーＭＯＳＦＥＴの要部を示
す模式的断面図である。この実施例では、ｐ＋ 形とな
るＭＯＳ部ウェル３を浅くかつ狭くするとともに、ＭＯ
Ｓ部ウェル３の周縁から張り出すｐ形領域９を前記ＭＯ
Ｓ部ウェル３よりも深くする構造となっている。また、
ｐ− 形の周辺ウェル４の不純物濃度は、前記実施例と
同様にＭＯＳ部ウェル３よりも低くなっている。したが
って、この実施例でも前記実施例同様な効果が得られる
。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. FIG. 10 is a schematic cross-sectional view showing the main parts of a power MOSFET according to another embodiment of the present invention. In this embodiment, the MOS part well 3, which is p+ type, is made shallow and narrow, and the MOS part well 3 is made shallow and narrow.
The p-type region 9 extending from the periphery of the S part well 3 is connected to the MO
It has a structure that is deeper than the S part well 3. Also,
The impurity concentration of the p-type peripheral well 4 is lower than that of the MOS part well 3, as in the previous embodiment. Therefore, this embodiment also provides the same effects as the previous embodiment.
【００２８】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である単体の
パワーＭＯＳＦＥＴの製造技術に適用した場合について
説明したが、それに限定されるものではなく、ＩＧＢＴ
（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ
Ｔｒａｎｓｉｓｔｏｒ）等にも適用できる。本発明
は少なくともパワーＭＯＳＦＥＴを有する半導体装置に
は適用できる。[0028] In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing technology of a single power MOSFET, which is the background application field, but the invention is not limited thereto.
(Insulated Gate Bipolar
Transistor), etc. The present invention is applicable to at least a semiconductor device having a power MOSFET.
【００２９】[0029]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。すなわち、本発明の縦型パワーＭＯ
ＳＦＥＴは、内蔵ダイオード動作時、周辺ウェルから半
導体基体に注入されるキャリアが少なくなることから、
内蔵ダイオードの逆回復時間が短縮されてスイッチング
スピードが向上するとともに、内蔵ダイオードやＭＯＳ
ＦＥＴの破壊耐量も向上する。Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the vertical power MO of the present invention
In SFET, when the built-in diode operates, fewer carriers are injected from the peripheral well into the semiconductor substrate.
The reverse recovery time of the built-in diode is shortened to improve switching speed, and the built-in diode and MOS
The breakdown resistance of the FET is also improved.
【図１】本発明によるパワーＭＯＳＦＥＴの要部を示す
模式的断面図である。FIG. 1 is a schematic cross-sectional view showing essential parts of a power MOSFET according to the present invention.
【図２】本発明によるパワーＭＯＳＦＥＴにおけるＭＯ
Ｓ部ウェルおよび周辺ウェルの配置を示す模式的平面図
である。FIG. 2 MO in the power MOSFET according to the present invention
FIG. 3 is a schematic plan view showing the arrangement of an S part well and a peripheral well.
【図３】本発明によるパワーＭＯＳＦＥＴの周辺ウェル
製造状態を示す半導体基体の一部の模式的断面図である
。FIG. 3 is a schematic cross-sectional view of a part of a semiconductor substrate showing a peripheral well manufacturing state of a power MOSFET according to the present invention.
【図４】本発明によるパワーＭＯＳＦＥＴのＭＯＳ部ウ
ェル製造状態を示す半導体基体の一部の模式的断面図で
ある。FIG. 4 is a schematic cross-sectional view of a part of a semiconductor substrate showing the manufacturing state of a MOS part well of a power MOSFET according to the present invention.
【図５】本発明によるパワーＭＯＳＦＥＴのゲート酸化
膜製造状態を示す半導体基体の一部の模式的断面図であ
る。FIG. 5 is a schematic cross-sectional view of a part of a semiconductor substrate showing the state of manufacturing a gate oxide film of a power MOSFET according to the present invention.
【図６】本発明によるパワーＭＯＳＦＥＴのソース電極
製造状態を示す半導体基体の一部の模式的断面図である
。FIG. 6 is a schematic cross-sectional view of a part of a semiconductor substrate showing a state of manufacturing a source electrode of a power MOSFET according to the present invention.
【図７】従来のパワーＭＯＳＦＥＴにおける逆回復時間
中のホール電流の流れを示す模式的断面図である。FIG. 7 is a schematic cross-sectional view showing the flow of Hall current during reverse recovery time in a conventional power MOSFET.
【図８】従来のパワーＭＯＳＦＥＴの要部を示す模式的
断面図である。FIG. 8 is a schematic cross-sectional view showing the main parts of a conventional power MOSFET.
【図９】パワーＭＯＳＦＥＴを使用したモータ制御回路
図である。FIG. 9 is a motor control circuit diagram using a power MOSFET.
【図１０】本発明の他の実施例によるパワーＭＯＳＦＥ
Ｔの要部を示す模式的断面図である。FIG. 10: Power MOSFE according to another embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing the main part of T.
１…半導体基体、２…エピタキシャル層、３…ＭＯＳ部
ウェル、４…周辺ウェル、６…フィールド絶縁膜、７…
ゲート絶縁膜、９…ｐ形領域、１０…ソース領域、１１
…ゲート電極、１２…内蔵ダイオード、１３…コンタク
ト層、１５…寄生バイポーラトランジスタ、１７…層間
絶縁膜、１９…ソース電極、２０…ゲート配線層、２１
…ソース配線層、２２…ドレイン電極、２５…モータ、
２７…ホール、２９…ホール電流、３５…チップ、３６
…フィールド・リミッティング・リング、３７…矩形領
域、４０，４３…絶縁膜、４１，４４…スルー膜。DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Epitaxial layer, 3... MOS part well, 4... Peripheral well, 6... Field insulating film, 7...
Gate insulating film, 9...p-type region, 10... source region, 11
... Gate electrode, 12 ... Built-in diode, 13 ... Contact layer, 15 ... Parasitic bipolar transistor, 17 ... Interlayer insulating film, 19 ... Source electrode, 20 ... Gate wiring layer, 21
...source wiring layer, 22...drain electrode, 25...motor,
27...Hall, 29...Hall current, 35...Chip, 36
...Field limiting ring, 37...Rectangular area, 40, 43...Insulating film, 41, 44...Through film.
Claims (2)
面に、ＭＯＳＦＥＴを形成する第２の導電型からなるＭ
ＯＳ部ウェルと、ＭＯＳＦＥＴ群の周辺に延在する第２
の導電型からなる周辺ウェルとを有する半導体装置であ
って、前記周辺ウェルの不純物濃度は、前記ＭＯＳ部ウ
ェルの不純物濃度よりも低くなっていることを特徴とす
る半導体装置。Claim 1: A semiconductor substrate of a second conductivity type forming a MOSFET on the main surface of a semiconductor substrate of a first conductivity type.
The second well extending around the OS part well and the MOSFET group
1. A semiconductor device comprising: a peripheral well having a conductivity type, wherein an impurity concentration of the peripheral well is lower than an impurity concentration of the MOS portion well.
在するｐ形からなる周辺ウェルの不純物濃度は、１×１
０１６ｃｍ−３程度以下となっているとともに、前記ｎ
チャネルＭＯＳＦＥＴを形成するＭＯＳ部ウェルの不純
物濃度は、１０１７ｃｍ−３程度以上となっていること
を特徴とする特許請求の範囲第１項記載の半導体装置。2. The impurity concentration of the p-type peripheral well extending around the n-channel MOSFET group is 1×1.
016 cm-3 or less, and the n
2. The semiconductor device according to claim 1, wherein the impurity concentration of the MOS part well forming the channel MOSFET is approximately 10<17>cm<-3> or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3119918A JPH04346477A (en) | 1991-05-24 | 1991-05-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3119918A JPH04346477A (en) | 1991-05-24 | 1991-05-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04346477A true JPH04346477A (en) | 1992-12-02 |
Family
ID=14773405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3119918A Pending JPH04346477A (en) | 1991-05-24 | 1991-05-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04346477A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236999A (en) * | 1993-01-22 | 1994-08-23 | Nec Corp | Manufacture of vertical-type field-effect transistor |
| US5703390A (en) * | 1994-10-31 | 1997-12-30 | Nec Corporation | Semiconductor device having four power MOSFETs constituting H bridge circuit |
| JP2007180577A (en) * | 2007-02-26 | 2007-07-12 | Nissan Motor Co Ltd | Silicon carbide semiconductor element |
| JP2009272473A (en) * | 2008-05-08 | 2009-11-19 | Denso Corp | Semiconductor device manufacturing method |
| WO2010073759A1 (en) * | 2008-12-25 | 2010-07-01 | 三菱電機株式会社 | Power semiconductor device |
| JP2012109602A (en) * | 2010-04-06 | 2012-06-07 | Mitsubishi Electric Corp | Power semiconductor device and method of manufacturing the same, and power module |
| JP2013021304A (en) * | 2011-06-15 | 2013-01-31 | Denso Corp | Semiconductor device |
| JP2015057851A (en) * | 2014-11-19 | 2015-03-26 | 三菱電機株式会社 | Semiconductor device |
| JP2017055145A (en) * | 2016-12-22 | 2017-03-16 | 三菱電機株式会社 | Semiconductor device |
| US11063122B2 (en) | 2016-11-01 | 2021-07-13 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device and power conversion device |
-
1991
- 1991-05-24 JP JP3119918A patent/JPH04346477A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236999A (en) * | 1993-01-22 | 1994-08-23 | Nec Corp | Manufacture of vertical-type field-effect transistor |
| US5703390A (en) * | 1994-10-31 | 1997-12-30 | Nec Corporation | Semiconductor device having four power MOSFETs constituting H bridge circuit |
| JP2007180577A (en) * | 2007-02-26 | 2007-07-12 | Nissan Motor Co Ltd | Silicon carbide semiconductor element |
| JP2009272473A (en) * | 2008-05-08 | 2009-11-19 | Denso Corp | Semiconductor device manufacturing method |
| US8513735B2 (en) | 2008-12-25 | 2013-08-20 | Mitsubishi Electric Corporation | Power semiconductor device |
| WO2010073759A1 (en) * | 2008-12-25 | 2010-07-01 | 三菱電機株式会社 | Power semiconductor device |
| JP5529042B2 (en) * | 2008-12-25 | 2014-06-25 | 三菱電機株式会社 | Power semiconductor device |
| JP2014082521A (en) * | 2010-04-06 | 2014-05-08 | Mitsubishi Electric Corp | Power semiconductor device |
| JP2012109602A (en) * | 2010-04-06 | 2012-06-07 | Mitsubishi Electric Corp | Power semiconductor device and method of manufacturing the same, and power module |
| US9006819B2 (en) | 2010-04-06 | 2015-04-14 | Mitsubishi Electric Corporation | Power semiconductor device and method for manufacturing same |
| JP2017005278A (en) * | 2010-04-06 | 2017-01-05 | 三菱電機株式会社 | Power semiconductor device |
| JP2013021304A (en) * | 2011-06-15 | 2013-01-31 | Denso Corp | Semiconductor device |
| US8841699B2 (en) | 2011-06-15 | 2014-09-23 | Denso Corporation | Semiconductor device including insulated gate bipolar transistor and diode |
| JP2015057851A (en) * | 2014-11-19 | 2015-03-26 | 三菱電機株式会社 | Semiconductor device |
| US11063122B2 (en) | 2016-11-01 | 2021-07-13 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device and power conversion device |
| JP2017055145A (en) * | 2016-12-22 | 2017-03-16 | 三菱電機株式会社 | Semiconductor device |
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