JPH04346260A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04346260A JPH04346260A JP3118487A JP11848791A JPH04346260A JP H04346260 A JPH04346260 A JP H04346260A JP 3118487 A JP3118487 A JP 3118487A JP 11848791 A JP11848791 A JP 11848791A JP H04346260 A JPH04346260 A JP H04346260A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- copper
- control circuit
- board
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052802 copper Inorganic materials 0.000 claims abstract description 61
- 239000010949 copper Substances 0.000 claims abstract description 61
- 230000017525 heat dissipation Effects 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 8
- 238000010168 coupling process Methods 0.000 abstract description 8
- 238000005859 coupling reaction Methods 0.000 abstract description 8
- 230000007257 malfunction Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052720 vanadium Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 resistors Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、パワーＭＯＳＦＥＴや
ＩＧＢＴ等のパワーデバイスを基板上に実装する構造を
もつ半導体装置いわゆるパワーＩＣに関し、特にＤＢＣ
基板上に配線したパターン上のパワーデバイスとプリン
ト基板上の制御回路のノイズ等による誤動作対策を施し
たパワーＩＣの実装構造に関するものである。[Industrial Application Field] The present invention relates to a semiconductor device having a structure in which power devices such as power MOSFETs and IGBTs are mounted on a substrate, and in particular to a so-called power IC.
The present invention relates to a power IC mounting structure that takes measures against malfunctions caused by noise, etc. of power devices on patterns wired on a board and control circuits on a printed circuit board.
【０００２】0002
【従来の技術】従来のこの種半導体装置として、３相ブ
リッジ構成のパワーモジュールを例にあげて図３に示し
て説明する。図３はそのパワーモジュールの回路図を示
すものであり、ここではパワーデバイスとしてＩＧＢＴ
を用いた場合を示す。同図において、１ＵＰ〜１ＷＮは
出力用のパワートランジスタであり、これらは、パワー
トランジスタ１ＵＰと１ＵＮ，１ＶＰと１ＶＮ，１ＷＰ
と１ＷＮにそれぞれ接続され、端子Ｐ−Ｎ間に並列に接
続されている。そして各々のパワートランジスタ１ＵＰ
〜１ＷＮには、それぞれ制御回路２ＵＰ，２ＵＮ，２Ｖ
Ｐ，２ＶＮ，２ＷＰ，２ＷＮが接続されている。また、
これら制御回路への電源は、Ｐ側の制御回路２ＵＰ，２
ＶＰ，２ＷＰにはそれぞれ電源４ＵＰ，４ＶＰ，４ＷＰ
が接続され、Ｎ側の制御回路２ＵＮ，２ＶＮ，２ＷＮに
は１つの電源４Ｎよりそれぞれ接続されている。2. Description of the Related Art As a conventional semiconductor device of this type, a power module having a three-phase bridge configuration will be exemplified and explained with reference to FIG. Figure 3 shows the circuit diagram of the power module, in which IGBT is used as the power device.
The case is shown below. In the same figure, 1UP to 1WN are power transistors for output, and these are power transistors 1UP and 1UN, 1VP and 1VN, and 1WP.
and 1WN, respectively, and are connected in parallel between terminals P and N. And each power transistor 1UP
~1WN has control circuits 2UP, 2UN, and 2V, respectively.
P, 2VN, 2WP, and 2WN are connected. Also,
The power to these control circuits is the control circuits 2UP and 2 on the P side.
Power supply 4UP, 4VP, 4WP for VP, 2WP respectively
are connected to the control circuits 2UN, 2VN, and 2WN on the N side, respectively, from one power source 4N.
【０００３】また、３ＵＰ〜３ＷＮは各々の入力端子で
あり、これら入力端子３ＵＰ，３ＶＰ，３ＷＰ，３ＶＮ
，３ＷＮに所定の入力信号が供給されることにより、こ
れら入力信号によって各制御回路２ＵＰ〜２ＷＮが駆動
される。そしてその各出力信号によりそれぞれのパワー
トランジスタ１ＵＰ〜１ＷＮがオン，オフ動作して、各
出力端子Ｕ，Ｖ，Ｗより３相交流出力を取り出すものと
なっている。[0003] Further, 3UP to 3WN are respective input terminals, and these input terminals 3UP, 3VP, 3WP, 3VN
, 3WN, each of the control circuits 2UP to 2WN is driven by these input signals. Each of the power transistors 1UP to 1WN is turned on and off by each output signal, and a three-phase AC output is taken out from each output terminal U, V, and W.
【０００４】図４は、図３に示すＵ相Ｐ側パワートラン
ジスタ１ＵＰの部分の従来の実装構造を示す模式図であ
る。この実装構造は、図４に示すように、放熱用銅ベー
ス板１０の上に、絶縁層であるＡｌ２Ｏ３１３の両面に
銅パターン１２，１４が形成されたＤＢＣ基板１１が載
置され、そのＤＢＣ基板１１の表面の銅パターン１４上
にパワートランジスタ１ＵＰ，１ＵＮが半田付け等によ
り搭載されている。また、制御回路２ＵＰを構成するＩ
Ｃや抵抗，コンデンサ等の部品はプリント基板２０上の
銅パターン２１に接続されて搭載されており、これらプ
リント基板２０とＤＢＣ基板１１とのパターン間の接続
は継ぎ端子３０にて結線されている。FIG. 4 is a schematic diagram showing a conventional mounting structure of the U-phase P-side power transistor 1UP shown in FIG. In this mounting structure, as shown in FIG. 4, a DBC substrate 11 with copper patterns 12 and 14 formed on both sides of an Al2O313 insulating layer is placed on a heat dissipation copper base plate 10. Power transistors 1UP and 1UN are mounted on a copper pattern 14 on the surface of 11 by soldering or the like. In addition, the I
Components such as capacitors, resistors, and capacitors are connected to and mounted on copper patterns 21 on a printed circuit board 20, and connections between these patterns on the printed circuit board 20 and the DBC board 11 are made using joint terminals 30. .
【０００５】この時、ＤＢＣ基板１１の表面の銅パター
ン１４と銅ベース板１０の間には絶縁層としてのＡｌ２
Ｏ３１３が介在されるため、各々の銅パターンは銅ベー
ス板１０との間で容量により結合されている。なお、図
中６はＤＢＣ基板１１上の各々の銅パターン１４と各パ
ワートランジスタ１ＵＰ，１ＵＮとを結線するアルミ（
Ａｌ）ワイヤー、１４１はＤＢＣ基板１１上の銅パター
ン１４の一部のパターンであり、各端子Ｕ，Ｐや３ＵＰ
への信号源，電源４ＵＰなどが外部と接続されている。At this time, an Al2 insulating layer is formed between the copper pattern 14 on the surface of the DBC substrate 11 and the copper base plate 10.
Since O313 is interposed, each copper pattern is capacitively coupled to the copper base plate 10. In addition, 6 in the figure is an aluminum (
Al) Wire 141 is a part of the copper pattern 14 on the DBC board 11, and each terminal U, P and 3UP
The signal source, power supply 4UP, etc. are connected to the outside.
【０００６】[0006]
【発明が解決しようとする課題】このように従来の実装
構造では、放熱用金属ベース板としての銅ベース板１０
に対して例えば端子Ｕにノイズが印加されたとすると、
制御回路２ＵＰの入力端子３ＵＰに銅ベース板１０に対
して端子Ｕに印加されたノイズとほぼ同じノイズがその
制御回路の基準電位である端子Ｕとの間に印加されるこ
とになり、制御回路が誤動作するという問題点があった
。本発明は上記のような問題点を解消するためになされ
たものであり、その目的は、銅ベース板などの放熱用金
属ベース板に対して出力端子Ｕ，Ｖ，ＷおよびＰ，Ｎに
ノイズが印加されても、パワーデバイスおよびその制御
回路が誤動作しない高信頼性の半導体装置を提供するこ
とにある。[Problems to be Solved by the Invention] As described above, in the conventional mounting structure, the copper base plate 10 as a metal base plate for heat dissipation is
For example, if noise is applied to terminal U,
Almost the same noise as the noise applied to the terminal U of the copper base plate 10 is applied to the input terminal 3UP of the control circuit 2UP between it and the terminal U, which is the reference potential of the control circuit. There was a problem in that it malfunctioned. The present invention has been made in order to solve the above-mentioned problems, and its purpose is to eliminate noise at the output terminals U, V, W and P, N with respect to a metal base plate for heat dissipation such as a copper base plate. It is an object of the present invention to provide a highly reliable semiconductor device in which a power device and its control circuit do not malfunction even when the power is applied.
【０００７】[0007]
【課題を解決するための手段】本発明に係る半導体装置
は、放熱用金属ベース板を装着するＤＢＣ基板の銅パタ
ーン上に搭載されたパワーデバイスチップと、プリント
基板上に搭載されて前記チップのパワーデバイスを制御
するための制御回路と、これらＤＢＣ基板とプリント基
板とを結線する継ぎ端子を備え、ＤＢＣ基板は、パワー
デバイスチップを搭載する銅パターン上の継ぎ端子との
継ぎ部分のパターンをシールドパターンとし、このシー
ルドパターン上に絶縁層を貼り付けるとともに、該絶縁
層上に銅パターンを形成してなり、前記シールドパター
ン上の銅パターンとプリント基板とを継ぎ端子にて接続
して、このシールドパターンにプリント基板上の制御回
路を駆動する電源の基準電位を付与するようにしたもの
である。[Means for Solving the Problems] A semiconductor device according to the present invention includes a power device chip mounted on a copper pattern of a DBC board on which a metal base plate for heat dissipation is attached, and a power device chip mounted on a printed circuit board to which the chip is mounted. The DBC board is equipped with a control circuit for controlling the power device and a joint terminal for connecting the DBC board and the printed circuit board, and the DBC board shields the pattern at the joint part between the joint terminal and the copper pattern on which the power device chip is mounted. A pattern is formed, an insulating layer is pasted on this shield pattern, and a copper pattern is formed on the insulating layer, and the copper pattern on the shield pattern and the printed circuit board are connected with a joint terminal to form this shield. The reference potential of the power supply that drives the control circuit on the printed circuit board is applied to the pattern.
【０００８】また、本発明の別の発明に係る半導体装置
は、上記のものにおいて、ＤＢＣ基板は、パワーデバイ
スチップを搭載する銅パターン上の継ぎ端子との継ぎ部
分のパターン上に、絶縁層と銅パターンとの積層構造に
代えて、両面銅パターンを有しかつスルーホールを有す
るガラスエポキシ基板を貼り付け、このエポキシ基板の
裏面銅パターンにプリント基板上の制御回路を駆動する
電源の基準電位を付与して、これをシールドパターンと
して用いるようにしたものである。Further, in the semiconductor device according to another aspect of the present invention, in the above semiconductor device, the DBC substrate has an insulating layer and Instead of a laminated structure with copper patterns, a glass epoxy board with copper patterns on both sides and through holes is pasted, and the reference potential of the power supply that drives the control circuit on the printed circuit board is connected to the copper pattern on the back side of this epoxy board. This is used as a shield pattern.
【０００９】[0009]
【作用】本発明においては、プリント基板上の制御回路
の配線のための銅パターンと金属ベース板との間の直接
の容量結合をなくし、基準電位（グランド電位と同電位
）が付与されたシールドパターンとの間の容量結合を大
きくしたことにより、金属ベース板と出力端子の間に印
加されるノイズによりパワートランジスタや制御回路が
誤動作するのを防ぐことができる。[Operation] In the present invention, direct capacitive coupling between the copper pattern for wiring the control circuit on the printed circuit board and the metal base plate is eliminated, and the shield is provided with a reference potential (same potential as the ground potential). By increasing the capacitive coupling with the pattern, it is possible to prevent the power transistor and the control circuit from malfunctioning due to noise applied between the metal base plate and the output terminal.
【００１０】0010
【実施例】以下、本発明の実施例について図面を用いて
説明する。図１は、本発明の一実施例による３相ブリッ
ジ構成のパワーモジュールの基本的な回路図である。同
図において、出力用のパワートランジスタ１ＵＰと１Ｕ
Ｎ，１ＶＰと１ＶＮ，１ＷＰと１ＷＮはそれぞれ接続さ
れており、端子Ｐ−Ｎ間に並列に接続されている。そし
て、これらパワートランジスタ１ＵＰ〜１ＷＮにはそれ
ぞれ制御回路２ＵＰ，２ＵＮ，２ＶＰ，２ＶＮ，２ＷＰ
，２ＷＮが接続されている。これら制御回路への電源は
、Ｐ側の制御回路２ＵＰ，２ＶＰ，２ＷＰにはそれぞれ
電源４ＵＰ，４ＶＰ，４ＷＰが接続され、Ｎ側の制御回
路２ＵＮ，２ＶＮ，２ＷＮには１つの電源４Ｎよりそれ
ぞれ接続されている。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a basic circuit diagram of a three-phase bridge configuration power module according to an embodiment of the present invention. In the same figure, output power transistors 1UP and 1U
N, 1VP and 1VN, 1WP and 1WN are connected, respectively, and are connected in parallel between terminals PN. These power transistors 1UP to 1WN have control circuits 2UP, 2UN, 2VP, 2VN, and 2WP, respectively.
, 2WN are connected. As for the power supply to these control circuits, power supplies 4UP, 4VP, and 4WP are connected to the control circuits 2UP, 2VP, and 2WP on the P side, respectively, and one power supply 4N is connected to the control circuits 2UN, 2VN, and 2WN on the N side, respectively. has been done.
【００１１】また、各入力端子３ＵＰ，３ＶＰ，３ＷＰ
，３ＵＮ，３ＶＮ，３ＷＮに所定の入力信号が供給され
ることにより、これら入力信号によって各制御回路２Ｕ
Ｐ〜２ＷＮが駆動される。そして、その各出力信号によ
りそれぞれのパワートランジスタ１ＵＰ〜１ＷＮがオン
，オフ動作して、上記従来例と同様に各出力端子Ｕ，Ｖ
，Ｗより３相交流出力を取り出すものとなっている。[0011] Also, each input terminal 3UP, 3VP, 3WP
, 3UN, 3VN, and 3WN, each control circuit 2U is controlled by these input signals.
P~2WN is driven. Then, each of the power transistors 1UP to 1WN is turned on and off by each output signal, and each of the output terminals U and V is operated similarly to the above conventional example.
, W are used to extract three-phase AC output.
【００１２】ここで、制御回路２ＵＰ〜２ＷＮへの配線
のパターンは、制御回路２ＵＰのパターンは端子Ｕの電
位を基準としたシールドパターン５ＵＰが、そして制御
回路２ＶＰのパターンは端子Ｖの電位を基準としたシー
ルドパターン５ＶＰが、制御回路２ＷＰのパターンは端
子Ｗの電位を基準としたシールドパターン５ＷＰがそれ
ぞれ構成され、さらに制御回路２ＶＮ，２ＶＮ，２ＷＮ
それぞれのパターンは端子Ｎの電位を基準とした１つの
シールドパターン５Ｎが構成されている。この時、それ
ぞれのシールドパターン５ＵＰ〜５Ｎの基準電位は各々
の制御回路に供給されている電源４ＵＰ，４ＶＰ，４Ｗ
Ｐのマイナス側つまり制御回路２ＵＰ，２ＶＰ，２ＷＰ
，２ＶＮ，２ＷＮそれぞれのグランド（ＧＮＤ）電位と
同電位である。Here, the pattern of the wiring to the control circuits 2UP to 2WN is that the pattern of the control circuit 2UP is a shield pattern 5UP based on the potential of the terminal U, and the pattern of the control circuit 2VP is based on the potential of the terminal V. The pattern of the control circuit 2WP is a shield pattern 5WP based on the potential of the terminal W, and the control circuits 2VN, 2VN, 2WN
Each pattern constitutes one shield pattern 5N based on the potential of the terminal N. At this time, the reference potential of each shield pattern 5UP to 5N is the power supply 4UP, 4VP, 4W supplied to each control circuit.
The negative side of P, that is, the control circuits 2UP, 2VP, 2WP
, 2VN, and 2WN.
【００１３】図２は、図１に示すＵ相Ｐ側パワートラン
ジスタ１ＵＰの部分の実装構造を示す模式図である。す
なわち、銅ベース板１０の上にＤＢＣ基板１１が載置さ
れ、そのＤＢＣ基板１１の表面の銅パターン１４のうち
、その継ぎ端子３０との継ぎ部分のパターンをシールド
パターン５ＵＰとし、このシールドパターン５ＵＰの上
に絶縁層１５を貼り付け、その上に銅パターン１４ａが
形成されている。また、パワートランジスタ１ＵＰは、
上述した従来例と同様にＤＢＣ基板１１の銅パターン１
４上に半田付けされ、制御回路２ＵＰを構成するＩＣや
ディスクリートトランジスタ，抵抗，コンデンサ等の部
品がプリント基板２０上に実装されている。FIG. 2 is a schematic diagram showing the mounting structure of the U-phase P-side power transistor 1UP shown in FIG. That is, the DBC board 11 is placed on the copper base board 10, and of the copper pattern 14 on the surface of the DBC board 11, the pattern of the joint part with the joint terminal 30 is defined as a shield pattern 5UP. An insulating layer 15 is pasted thereon, and a copper pattern 14a is formed thereon. In addition, the power transistor 1UP is
Similarly to the conventional example described above, the copper pattern 1 of the DBC board 11
Components such as ICs, discrete transistors, resistors, and capacitors constituting the control circuit 2UP are mounted on the printed circuit board 20.
【００１４】また、この制御回路２ＵＰは、継ぎ端子３
０によってそのパターン１４ａ，スルーホール１６を介
してシールドパターン５ＵＰと電気的に接続され、アル
ミ（Ａｌ）ワイヤ６でパワートランジスタ１ＵＰと接続
されている。このとき、シールドパターン５ＵＰは、継
ぎ端子３０を介して制御回路２ＵＰを駆動する電源４Ｕ
Ｐの基準電位であるＵ電位（電源４ＵＰのマイナス側）
とそれぞれスルーホール１６により接続され、基準電位
と同電位となっている。なお、図中同一符号は同一また
は相当部分を示している。[0014] Furthermore, this control circuit 2UP is connected to a connecting terminal 3.
0 is electrically connected to the shield pattern 5UP via the pattern 14a and the through hole 16, and is connected to the power transistor 1UP by an aluminum (Al) wire 6. At this time, the shield pattern 5UP is connected to the power source 4U that drives the control circuit 2UP via the joint terminal 30.
U potential which is the reference potential of P (minus side of power supply 4UP)
are connected to each other by through holes 16, and have the same potential as the reference potential. Note that the same reference numerals in the figures indicate the same or corresponding parts.
【００１５】次に上記実施例の動作を説明する。ＤＢＣ
基板１１上の各銅パターン１４はそれぞれ銅ベース板１
０との間や他のパターンとの間で容量結合しているが、
ここでは端子Ｕのパターンと銅ベース板１０との間の容
量ＣＶを考えてみる。この容量ＣＶにはシールドパター
ン５ＵＰの電位が端子Ｕと同電位であるので、シールド
パターン５ＵＰと銅ベース板１０との容量も含まれる。
制御回路２ＵＰの入力端子３ＵＰのパターンとシールド
パターン５ＵＰとの間の容量をＣＵＰＩとし、入力端子
３ＵＰのパターンと銅ベース板１０との間の容量をＣＵ
ＰＳとすると、容量の大きさは、ＣＶは端子Ｕのパター
ンが出力パターンとシールドパターン５ＵＰによる結合
容量であるので、最は大きく、ＣＵＰＳは入力端子３Ｕ
Ｐのパターンと銅ベース板１０との間には、シールドパ
ターン５ＵＰがあるため、その直接の結合容量は極めて
小さい。Next, the operation of the above embodiment will be explained. D.B.C.
Each copper pattern 14 on the substrate 11 is connected to the copper base plate 1.
Although it is capacitively coupled with 0 and with other patterns,
Here, the capacitance CV between the terminal U pattern and the copper base plate 10 will be considered. Since the potential of the shield pattern 5UP is the same as that of the terminal U, this capacitance CV also includes the capacitance between the shield pattern 5UP and the copper base plate 10. Let CUPI be the capacitance between the input terminal 3UP pattern of the control circuit 2UP and the shield pattern 5UP, and let CU be the capacitance between the input terminal 3UP pattern and the copper base plate 10.
If PS is the capacitance, CV is the largest because the pattern of terminal U is the coupling capacitance between the output pattern and shield pattern 5UP, and CUPS is the capacitance of input terminal 3U.
Since the shield pattern 5UP exists between the P pattern and the copper base plate 10, its direct coupling capacitance is extremely small.
【００１６】このため、銅ベース板１０に対して端子Ｕ
にノイズが印加されたとしても制御回路２ＵＰの入力端
子３ＵＰには、ノイズの影響はほとんどなく、ノイズに
よる制御回路２ＵＰの誤動作することはない。これと同
様で、各制御回路２ＵＰ，２ＷＰ，２ＵＮ，２ＶＮ，２
ＷＮの場合についても同じである。銅ベース板１０に対
して出力端子Ｕ，Ｖ，Ｗ，Ｐ，Ｎにノイズが印加されて
もパワートランジスタ，制御回路が誤動作することはな
い。For this reason, the terminal U is connected to the copper base plate 10.
Even if noise is applied to the input terminal 3UP of the control circuit 2UP, the noise has almost no effect on the input terminal 3UP of the control circuit 2UP, and the control circuit 2UP will not malfunction due to the noise. Similar to this, each control circuit 2UP, 2WP, 2UN, 2VN, 2
The same applies to the case of WN. Even if noise is applied to the output terminals U, V, W, P, and N of the copper base plate 10, the power transistor and the control circuit will not malfunction.
【００１７】なお、上記実施例ではＤＢＣ基板１１上の
銅パターン１４の継ぎ端子３０との接続部分のパターン
をシールドパターンとし、そのシールドパターン上に絶
縁相５，銅パターン１４ａを積層して、この銅パターン
１４ａとプリント基板２０上の制御回路とを継ぎ端子３
０にて接続する場合について説明したが、本発明は、こ
れに限定されるものではなく、幾多の変形が可能である
。In the above embodiment, the pattern of the connecting portion of the copper pattern 14 on the DBC board 11 with the joint terminal 30 is used as a shield pattern, and the insulating layer 5 and the copper pattern 14a are laminated on the shield pattern. The copper pattern 14a and the control circuit on the printed circuit board 20 are connected to the terminal 3.
Although the case where the connection is made at 0 is described, the present invention is not limited to this, and many modifications are possible.
【００１８】例えば、ＤＢＣ基板１１の銅パターン１４
上の継ぎ端子３０との継ぎ部分のパターン上に、両面銅
パターンを有しかつスルーホールを有するガラスエポキ
シ基板を貼り付け、その裏面銅パターンにプリント基板
上の制御回路を駆動する電源の基準電位を付与して、こ
れをシールドパターンとして用いても、上記実施例と同
様の効果を奏する。また、上記実施例ではパワーデバイ
スとしてＩＧＢＴの場合について説明したが、パワーＭ
ＯＳＦＥＴ，バイポーラトランジスタ等であってもよく
、さらに放熱用の金属ベース板も銅ベース板以外のもの
であっても，同様の効果を奏する。For example, the copper pattern 14 of the DBC board 11
A glass epoxy board with copper patterns on both sides and through holes is pasted on the pattern of the joint part with the upper joint terminal 30, and the reference potential of the power supply that drives the control circuit on the printed circuit board is applied to the copper pattern on the back side. Even if this is applied as a shield pattern, the same effect as in the above embodiment can be obtained. Further, in the above embodiment, the case where IGBT was used as the power device was explained, but the power M
It may be an OSFET, a bipolar transistor, etc., and even if the metal base plate for heat dissipation is other than a copper base plate, the same effect will be achieved.
【００１９】[0019]
【発明の効果】以上のように本発明は、放熱用の金属ベ
ース板を有するＤＢＣ基板のプリント基板とを継ぐとこ
ろの銅パターンをシールドパターンとし、その上に絶縁
層，銅パターンを積層形成してそれとプリント基板上の
制御回路とを継ぐように構成するか、あるいは前記ＤＢ
Ｃ基板のプリント基板とを継ぐところの銅パターン上に
両面銅パターンを有しかつスルーホールを有するガラス
エポキシ基板を貼り付け、その裏面銅パターンをシール
ドパターンとしてそれとプリント基板上の制御回路とを
継ぐように構成したので、制御回路のパターンと金属ベ
ース板との間の直接の容量結合をなくし、制御回路のパ
ターンとシールドパターンとの容量結合も大きくなる。
これによって、金属ベース板と出力端子との間の印加さ
れたノイズによるパワーデバイスや制御回路の誤動作が
発生しない高信頼性のパワーＩＣが得られる効果がある
。[Effects of the Invention] As described above, the present invention uses a shield pattern as a copper pattern connecting a printed circuit board of a DBC board having a metal base plate for heat dissipation, and forms an insulating layer and a copper pattern on top of the shield pattern. or connect it to the control circuit on the printed circuit board, or
A glass epoxy board with copper patterns on both sides and through holes is pasted on the copper pattern where the C board is connected to the printed circuit board, and the copper pattern on the back side is used as a shield pattern to connect it to the control circuit on the printed circuit board. With this configuration, direct capacitive coupling between the control circuit pattern and the metal base plate is eliminated, and capacitive coupling between the control circuit pattern and the shield pattern is also increased. This has the effect of providing a highly reliable power IC in which malfunctions of power devices and control circuits do not occur due to noise applied between the metal base plate and the output terminal.
【図１】本発明の一実施例による３相ブリッジ構成のパ
ワーＩＣの基本的な回路構成図である。FIG. 1 is a basic circuit configuration diagram of a power IC with a three-phase bridge configuration according to an embodiment of the present invention.
【図２】図１のＵ相Ｐ側のパワートランジスタ部分の断
面構造を示す模式図である。FIG. 2 is a schematic diagram showing a cross-sectional structure of a power transistor portion on the U-phase P side in FIG. 1;
【図３】従来例による３相ブリッジ構成のパワーＩＣの
回路構成図である。FIG. 3 is a circuit configuration diagram of a power IC having a three-phase bridge configuration according to a conventional example.
【図４】図３のＵ相Ｐ側のパワートランジスタ部分の断
面構造を示す模式図である。4 is a schematic diagram showing a cross-sectional structure of a power transistor portion on the U-phase P side in FIG. 3; FIG.
１ＵＰ〜１ＷＮ パワートランジスタ２ＵＰ〜２ＷＮ
制御回路
３ＵＰ〜３ＷＮ 入力端子
４ＵＰ〜４Ｎ 電源
５ＵＰ〜５Ｎ シールドパターン
１０ 銅ベース板（放熱用金属ベース板）１１ Ｄ
ＢＣ基板
１２ 銅パターン
１３ Ａｌ２Ｏ３
１４，１４ａ 銅パターン
１５ 絶縁層
１６ スルーホール
２０ プリント基板
３０ 継ぎ端子1UP~1WN Power transistor 2UP~2WN
Control circuit 3UP~3WN Input terminal 4UP~4N Power supply 5UP~5N Shield pattern 10 Copper base plate (metal base plate for heat dissipation) 11 D
BC board 12 Copper pattern 13 Al2O3 14, 14a Copper pattern 15 Insulating layer 16 Through hole 20 Printed circuit board 30 Joint terminal
Claims (2)
基板の銅パターン上に搭載されたパワーデバイスチップ
と、プリント基板上に搭載されて前記チップのパワーデ
バイスを制御するための制御回路と、前記ＤＢＣ基板と
前記プリント基板とを結線する継ぎ端子を備え、前記Ｄ
ＢＣ基板は、前記パワーデバイスチップを搭載する銅パ
ターン上の前記継ぎ端子との継ぎ部分のパターンをシー
ルドパターンとし、このシールドパターン上に絶縁層を
貼りつけるとともに、該絶縁層上に銅パターンを形成し
てなり、前記シールドパターン上の銅パターンと前記プ
リント基板とを前記継ぎ端子にて接続して、該シールド
パターンに前記プリント基板上の前記制御回路を駆動す
る電源の基準電位を付与するようにしたことを特徴とす
る半導体装置。[Claim 1] DBC equipped with a metal base plate for heat dissipation
A power device chip mounted on a copper pattern of a circuit board, a control circuit mounted on a printed circuit board for controlling the power device of the chip, and a connecting terminal for connecting the DBC board and the printed circuit board. , the above D
In the BC board, a pattern at a joint portion with the joint terminal on the copper pattern on which the power device chip is mounted is used as a shield pattern, an insulating layer is pasted on the shield pattern, and a copper pattern is formed on the insulating layer. The copper pattern on the shield pattern and the printed circuit board are connected by the joint terminal, and a reference potential of a power source for driving the control circuit on the printed circuit board is applied to the shield pattern. A semiconductor device characterized by:
ワーデバイスチップを搭載する銅パターン上の継ぎ端子
との継ぎ部分のパターン上に、絶縁層と銅パターンとの
積層構造に代えて、両面銅パターンを有しかつスルーホ
ールを有するガラスエポキシ基板を貼り付けたことを特
徴とする半導体装置。2. In claim 1, the DBC board includes a double-sided copper layer on the pattern of the joint portion of the copper pattern on which the power device chip is mounted and the joint terminal, instead of the laminated structure of the insulating layer and the copper pattern. A semiconductor device characterized in that a glass epoxy substrate having a pattern and through holes is attached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3118487A JP2600516B2 (en) | 1991-05-23 | 1991-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3118487A JP2600516B2 (en) | 1991-05-23 | 1991-05-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04346260A true JPH04346260A (en) | 1992-12-02 |
| JP2600516B2 JP2600516B2 (en) | 1997-04-16 |
Family
ID=14737895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3118487A Expired - Lifetime JP2600516B2 (en) | 1991-05-23 | 1991-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2600516B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5727727A (en) * | 1995-02-02 | 1998-03-17 | Vlt Corporation | Flowing solder in a gap |
| US5808358A (en) * | 1994-11-10 | 1998-09-15 | Vlt Corporation | Packaging electrical circuits |
| US5876859A (en) * | 1994-11-10 | 1999-03-02 | Vlt Corporation | Direct metal bonding |
| US5945130A (en) * | 1994-11-15 | 1999-08-31 | Vlt Corporation | Apparatus for circuit encapsulation |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5456843B2 (en) * | 2012-05-24 | 2014-04-02 | 三菱電機株式会社 | Power supply |
-
1991
- 1991-05-23 JP JP3118487A patent/JP2600516B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808358A (en) * | 1994-11-10 | 1998-09-15 | Vlt Corporation | Packaging electrical circuits |
| US5876859A (en) * | 1994-11-10 | 1999-03-02 | Vlt Corporation | Direct metal bonding |
| US5938104A (en) * | 1994-11-10 | 1999-08-17 | Vlt Corporation | Direct metal bonding |
| US6096981A (en) * | 1994-11-10 | 2000-08-01 | Vlt Corporation | Packaging electrical circuits |
| US6119923A (en) * | 1994-11-10 | 2000-09-19 | Vlt Corporation | Packaging electrical circuits |
| US6159772A (en) * | 1994-11-10 | 2000-12-12 | Vlt Corporation | Packaging electrical circuits |
| US5945130A (en) * | 1994-11-15 | 1999-08-31 | Vlt Corporation | Apparatus for circuit encapsulation |
| US6403009B1 (en) | 1994-11-15 | 2002-06-11 | Vlt Corporation | Circuit encapsulation |
| US6710257B2 (en) | 1994-11-15 | 2004-03-23 | Vlt Corporation | Circuit encapsulation |
| US5727727A (en) * | 1995-02-02 | 1998-03-17 | Vlt Corporation | Flowing solder in a gap |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2600516B2 (en) | 1997-04-16 |
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