JPH04338630A - Method for manufacture of semiconductor device - Google Patents
Method for manufacture of semiconductor deviceInfo
- Publication number
- JPH04338630A JPH04338630A JP3141462A JP14146291A JPH04338630A JP H04338630 A JPH04338630 A JP H04338630A JP 3141462 A JP3141462 A JP 3141462A JP 14146291 A JP14146291 A JP 14146291A JP H04338630 A JPH04338630 A JP H04338630A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- resin layer
- fine pattern
- ladder polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229920000642 polymer Polymers 0.000 claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims description 15
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 6
- 125000001153 fluoro group Chemical group F* 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000002952 polymeric resin Substances 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- 229920003002 synthetic resin Polymers 0.000 claims 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 abstract description 12
- 238000003754 machining Methods 0.000 abstract description 2
- 230000000052 comparative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 14
- 239000000243 solution Substances 0.000 description 7
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 6
- RDOXTESZEPMUJZ-UHFFFAOYSA-N anisole Chemical compound COC1=CC=CC=C1 RDOXTESZEPMUJZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- UZKWTJUDCOPSNM-UHFFFAOYSA-N methoxybenzene Substances CCCCOC=C UZKWTJUDCOPSNM-UHFFFAOYSA-N 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体装置の製造方
法に関するものであり、特に半導体基板上に微細なパタ
ーンを形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a fine pattern on a semiconductor substrate.
【０００２】0002
【従来の技術】図２は微細パターンを感光性樹脂を用い
た多層構造の膜で形成する従来の半導体装置の製造方法
を示したものであり、その多層構造は図２（ａ） に示
すようになる。その材料としては半導体基板１上に比較
的厚い有機樹脂層１０を形成し、第２層目にはシロキサ
ンポリマーのアルコール溶液を用いて、スピンコート法
により形成した膜１３を、上記有機樹脂層１０上に形成
し、最上層は感光性樹脂層の比較的薄い薄膜層１２を形
成した構成としている。図２（ａ） は最上層の感光性
樹脂層を露光，現像し、画像形成を行った状態を示す。2. Description of the Related Art FIG. 2 shows a conventional method for manufacturing a semiconductor device in which a fine pattern is formed using a multilayered film using a photosensitive resin, and the multilayered structure is as shown in FIG. 2(a). become. As for its material, a relatively thick organic resin layer 10 is formed on the semiconductor substrate 1, and the second layer is a film 13 formed by spin coating using an alcohol solution of siloxane polymer. The uppermost layer is a relatively thin thin film layer 12 of a photosensitive resin layer. FIG. 2(a) shows a state in which the uppermost photosensitive resin layer has been exposed and developed to form an image.
【０００３】このような構造の多層膜の最上層の感光樹
脂層を露光，現像することにより画像形成を行った後、
最上層をマスクとしてシロキサンポリマー層１３をＦ原
子を含むリアクティブイオンエッチング（ＲＩＥ）を用
いて画像形成した後（図２（ｂ））、Ｏ原子を含むＲＩ
Ｅを用いて有機樹脂層１０の異方性エッチングを行うこ
とにより、図２（ｃ） に示すように段差を有する部分
においても微細パターンを形成することが可能となって
いる。After forming an image by exposing and developing the uppermost photosensitive resin layer of the multilayer film having such a structure,
After forming an image on the siloxane polymer layer 13 using reactive ion etching (RIE) containing F atoms using the top layer as a mask (FIG. 2(b)), RI containing O atoms is formed.
By performing anisotropic etching of the organic resin layer 10 using E, it is possible to form a fine pattern even in a portion having a step, as shown in FIG. 2(c).
【０００４】0004
【発明が解決しようとする課題】ところが、この従来の
微細パターン形成方法においては、２つの問題点が有る
。１つはシロキサンポリマー溶液は低粘性であるため、
半導体基板の段差等、最上層の厚膜有機樹脂層で吸収で
きない凹凸の凹部に留まりやすいので、シロキサンポリ
マー層の厚さのばらつきが大きいという問題であり、も
う１つはシロキサンポリマー溶液が低粘性であるために
、厚膜の塗布膜が得られず、最下層の有機樹脂層をＲＩ
Ｅでエッチングする場合、そのパターンの角が削られて
図２（ｃ） に示すような加工精度ずれ１４が生じ、必
要な寸法精度が得られないという問題である。However, this conventional fine pattern forming method has two problems. One is that siloxane polymer solutions have low viscosity;
This problem is caused by large variations in the thickness of the siloxane polymer layer, as it tends to stay in uneven concavities such as steps on a semiconductor substrate that cannot be absorbed by the thick organic resin layer on the top layer.Another problem is that the siloxane polymer solution has a low viscosity. Therefore, a thick coating film cannot be obtained, and the bottom organic resin layer is not coated with RI.
When etching is performed using E, the corners of the pattern are shaved off, resulting in a machining accuracy deviation 14 as shown in FIG. 2(c), and the problem is that the required dimensional accuracy cannot be obtained.
【０００５】この発明は、上記のような従来のものの問
題点を解消するためになされたもので、段差を有する半
導体基板上でも加工精度の良い微細パターンを形成でき
る半導体装置の製造方法を提供することを目的とする。The present invention has been made to solve the problems of the conventional methods as described above, and provides a method for manufacturing a semiconductor device that can form a fine pattern with high processing accuracy even on a semiconductor substrate having steps. The purpose is to
【０００６】[0006]
【課題を解決するための手段】この発明に係る半導体装
置の製造方法は、シロキサンポリマーの代わりにシリコ
ンラダーポリマー溶液を用いてスピンコートした塗布膜
を用いて多層構造の膜を形成した後、最上層をリソグラ
フィー技術により画像形成し、ＲＩＥによりシリコンラ
ダーポリマー層の画像形成を行った後、酸素原子を含む
ＲＩＥにより微細パターンを形成するようにしたもので
ある。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a multilayer film using a spin-coated film using a silicon ladder polymer solution instead of a siloxane polymer, and then finally After forming an image on the upper layer using lithography technology and forming an image on the silicon ladder polymer layer using RIE, a fine pattern is formed using RIE containing oxygen atoms.
【０００７】[0007]
【作用】この発明において用いるシリコンラダーポリマ
ー溶液は分子量が比較的大きく、シロキサンポリマーに
比べて高粘性溶液が得られ、シロキサンポリマーより厚
膜が得られ、先に記述した２つの問題点を解決すること
ができる。即ち、シリコンラダーポリマー溶液は高粘性
であるため、凹部に留まることがなく、膜厚の不均一性
が改善される。厚膜形成が容易であるため、最下層のＲ
ＩＥのエッチング時の中間層のパターンの角が削られて
も下層パターンへの影響がないために加工精度が向上す
る。[Action] The silicon ladder polymer solution used in this invention has a relatively large molecular weight, and a higher viscosity solution can be obtained than that of a siloxane polymer, and a thicker film can be obtained than that of a siloxane polymer, thus solving the two problems described above. be able to. That is, since the silicon ladder polymer solution has high viscosity, it does not stay in the recesses, and the non-uniformity of the film thickness is improved. Because it is easy to form a thick film, the bottom layer R
Even if the corners of the intermediate layer pattern are shaved off during IE etching, there is no effect on the underlying pattern, improving processing accuracy.
【０００８】[0008]
【実施例】以下、この発明の一実施例を図について説明
する。図１はこの発明の一実施例による半導体装置の製
造方法を示し、図において、最下層の比較的厚い有機樹
脂層１０を、日立化成株式会社製 ＭＨ−５０をスピ
ンコート法で２．０μｍ塗布し、２００℃，１５分ベー
キングして形成する。その上に化学式（１） で示され
るシリコンラダーポリマー（Ｒ１ ＝Ｒ２ ＝ＣＨ３
，分子量１００００〜２００００）のアニソール／トル
エン混合溶液をスピンコートし、０．７μｍを塗布し、
２００℃，１５分ベーキングして層１２を形成する。さ
らにその上に感光性樹脂として三菱化成株式会社製ＭＣ
ＰＲ−２０００Ｈを０．７μｍスピンコートし、８０℃
，８０秒プレベークして層１３を形成した後、これを露
光，現像して図１（ａ） に示すパターンを段差上で得
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, a comparatively thick lowermost organic resin layer 10 is coated with MH-50 manufactured by Hitachi Chemical Co., Ltd. to a thickness of 2.0 μm by spin coating. Then, bake at 200°C for 15 minutes to form. On top of that, a silicon ladder polymer (R1 = R2 = CH3
, molecular weight 10,000 to 20,000) by spin-coating an anisole/toluene mixed solution, applying 0.7 μm,
A layer 12 is formed by baking at 200° C. for 15 minutes. Furthermore, MC manufactured by Mitsubishi Kasei Co., Ltd. is applied as a photosensitive resin on top of that.
Spin coat PR-2000H to a thickness of 0.7 μm and heat at 80°C.
After prebaking for 80 seconds to form a layer 13, this is exposed and developed to obtain the pattern shown in FIG. 1(a) on the step.
【０００９】次に、Ｆ原子を含むＲＩＥプラズマエッチ
ングを行うことにより、層１１のパターニングを行い（
図１（ｂ））、さらにＯ原子を含むＲＩＥプラズマエッ
チングを行うことにより、図１（ｃ） に示すような加
工精度に優れたパターンを得ることができる。Next, the layer 11 is patterned by performing RIE plasma etching containing F atoms (
By further performing RIE plasma etching containing O atoms, a pattern with excellent processing accuracy as shown in FIG. 1(c) can be obtained.
【００１０】このように、本実施例によれば、中間層に
用いたシリコンラダーポリマー層が粘性が高いので、最
上層の厚膜有機樹脂層で吸収できない凹凸の凹部に留ま
りにくく、シロキサンポリマー層の厚さを容易に均一化
でき、しかもシリコンラダーポリマー層が高粘性である
ために、容易に厚膜化が可能であるので、最下層をＲＩ
Ｅでエッチングする時のダメージによる中間層の角が削
れることによるパターン巾のシフトやパターン段面形状
の劣化を抑制することができ、微細パターンの加工精度
の向上が達成できる。As described above, according to this embodiment, since the silicon ladder polymer layer used as the intermediate layer has a high viscosity, it is difficult to stay in the uneven recesses that cannot be absorbed by the thick film organic resin layer as the top layer, and the siloxane polymer layer The thickness of the silicon ladder polymer layer can be easily made uniform, and since the silicon ladder polymer layer has high viscosity, it is possible to easily increase the thickness of the silicon ladder polymer layer.
It is possible to suppress a shift in the pattern width and deterioration of the pattern step shape due to the corners of the intermediate layer being shaved off due to damage during etching with E, and it is possible to improve the processing accuracy of fine patterns.
【００１１】なお、中間層のシリコンラダーポリマーと
して、[0011] As the silicon ladder polymer of the intermediate layer,
【００１２】0012
【化２】[Case 2]
【００１３】としたラダーポリマーで、分子量１５００
０〜３００００のアニソール／トルエン混合溶液を用い
たスピンコート膜を０．７μｍ形成した構造を持つ３層
膜を用いても同様の効果を得ることができた。A ladder polymer with a molecular weight of 1500
A similar effect could be obtained using a three-layer film having a structure in which a 0.7 μm thick spin-coated film was formed using an anisole/toluene mixed solution of 0 to 30,000.
【００１４】[0014]
【発明の効果】以上のように、この発明に係る半導体装
置の製造方法によれば、シロキサンポリマーと同様かそ
れ以上の酸素原子を含むＲＩＥプラズマ耐性を有し、か
つ容易に厚膜のスピンコートの可能なシリコンラダーポ
リマーを用いた３層構造を有する膜を形成することより
、ＲＩＥプラズマエッチングにより加工精度の高い微細
パターンを容易に得ることができる。As described above, the method for manufacturing a semiconductor device according to the present invention has RIE plasma resistance containing oxygen atoms equal to or higher than that of a siloxane polymer, and can easily spin coat a thick film. By forming a film having a three-layer structure using a silicon ladder polymer that can be used, a fine pattern with high processing accuracy can be easily obtained by RIE plasma etching.
【図１】本発明の一実施例によって形成される半導体装
置の製造方法を示す図であり、図１（ａ） 〜（ｃ）
はその各工程を示す断面図である。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device formed according to an embodiment of the present invention, and FIGS. 1(a) to 1(c)
FIG. 2 is a cross-sectional view showing each step.
【図２】従来の微細パターンの形成方法によるパターン
断面を示す図であり、図２（ａ）〜（ｃ） はその各工
程をプロセス順に示す図である。FIG. 2 is a diagram showing a cross section of a pattern according to a conventional fine pattern forming method, and FIGS. 2(a) to 2(c) are diagrams showing each step in the process order.
１ 半導体基板 １０ 有機樹脂層 １１ シリコンラダーポリマー １２ 感光性樹脂層 １３ シロキサンポリマー層 1 Semiconductor substrate 10 Organic resin layer 11 Silicon ladder polymer 12 Photosensitive resin layer 13 Siloxane polymer layer
Claims (2)
細パターンを形成する際、感光性樹脂層の下に複数の樹
脂層を形成する微細パターンの形成方法において、半導
体基板上に厚い有機樹脂層を形成する工程と、該有機樹
脂層の上に後述する化学式（１） で示すようなシリコ
ンラダーポリマーの樹脂層を形成する工程と、該シリコ
ンラダーポリマー層の上に感光性樹脂層を形成した構造
を有する多層膜を用いてプラズマエッチング技術により
微細パターンを形成する工程とを含むことを特徴とする
半導体装置の製造方法。1. In a method for forming a fine pattern in which a plurality of resin layers are formed under a photosensitive resin layer when forming a fine pattern on a semiconductor substrate using a photosensitive resin, a thick organic resin is formed on the semiconductor substrate. a step of forming a silicon ladder polymer resin layer as shown in chemical formula (1) described below on the organic resin layer; and a step of forming a photosensitive resin layer on the silicon ladder polymer layer. 1. A method for manufacturing a semiconductor device, comprising: forming a fine pattern using a multilayer film having a structure using a plasma etching technique.
ターン形成において、最上層の感光性樹脂を用いて画像
形成を行った後、プラズマエッチングを用いてその下の
シリコンラダーポリマーをフッ素原子を含むガスを用い
てプラズマエッチングする工程と、その後、最下層の有
機樹脂層を酸素原子を含む異方性プラズマエッチングを
用いてパターニングし、微細パターンを形成する工程と
を含むことを特徴とする請求項１記載の半導体装置の製
造方法。 【化１】2. In pattern formation using a multilayer film having the above structure, after forming an image using the top layer photosensitive resin, the underlying silicon ladder polymer is etched with fluorine atoms using plasma etching. A claim characterized by comprising the steps of performing plasma etching using a gas containing oxygen atoms, and then patterning the bottom organic resin layer using anisotropic plasma etching containing oxygen atoms to form a fine pattern. Item 1. A method for manufacturing a semiconductor device according to item 1. [Chemical formula 1]
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3141462A JPH04338630A (en) | 1991-05-15 | 1991-05-15 | Method for manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3141462A JPH04338630A (en) | 1991-05-15 | 1991-05-15 | Method for manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04338630A true JPH04338630A (en) | 1992-11-25 |
Family
ID=15292449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3141462A Pending JPH04338630A (en) | 1991-05-15 | 1991-05-15 | Method for manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04338630A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998032162A1 (en) * | 1997-01-21 | 1998-07-23 | Matsushita Electric Industrial Co., Ltd. | Pattern forming method |
| JP2002252222A (en) * | 2001-02-22 | 2002-09-06 | Nec Corp | Method for manufacturing semiconductor device, and the semiconductor device |
| US7914975B2 (en) | 2007-04-10 | 2011-03-29 | International Business Machines Corporation | Multiple exposure lithography method incorporating intermediate layer patterning |
-
1991
- 1991-05-15 JP JP3141462A patent/JPH04338630A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998032162A1 (en) * | 1997-01-21 | 1998-07-23 | Matsushita Electric Industrial Co., Ltd. | Pattern forming method |
| JP2002252222A (en) * | 2001-02-22 | 2002-09-06 | Nec Corp | Method for manufacturing semiconductor device, and the semiconductor device |
| US7914975B2 (en) | 2007-04-10 | 2011-03-29 | International Business Machines Corporation | Multiple exposure lithography method incorporating intermediate layer patterning |
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