JPH0431772A - Service interruption detecting circuit - Google Patents
Service interruption detecting circuitInfo
- Publication number
- JPH0431772A JPH0431772A JP13757590A JP13757590A JPH0431772A JP H0431772 A JPH0431772 A JP H0431772A JP 13757590 A JP13757590 A JP 13757590A JP 13757590 A JP13757590 A JP 13757590A JP H0431772 A JPH0431772 A JP H0431772A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- lowering
- service interruption
- peak value
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 45
- 239000003990 capacitor Substances 0.000 abstract description 19
- 238000009499 grossing Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000004804 winding Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 206010003591 Ataxia Diseases 0.000 description 1
- 206010010947 Coordination abnormal Diseases 0.000 description 1
- 101150030723 RIR2 gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 208000028756 lack of coordination Diseases 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
本発明は交流電圧を入力とする電源装置と、その電源装
置から電源を供給される制御装置などの負荷とからなる
系を保護、するために入力交流電圧の低下を検出する回
路に関する。
上記負荷がコンピュータを用いた制御装置等であるとき
は電源低下時に必要データをバックアップRAMへ退避
するなどの停電準備動作を行う必要があるため、実際に
電源装置の出力が低下し始める以前に、停電検知信号が
必要となる。
なお以下各図において同一の符号は同一もしくは相当部
分を示す。The present invention relates to a circuit that detects a drop in input AC voltage in order to protect a system consisting of a power supply device that inputs AC voltage and a load such as a control device that is supplied with power from the power supply device. When the load mentioned above is a control device using a computer, etc., it is necessary to perform power outage preparation operations such as saving necessary data to backup RAM when the power decreases, so before the output of the power supply actually starts to decrease, A power outage detection signal is required. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.
第3図はこの種の停電検出回路を含むシステムの構成例
を示す。同図において01は交流電源、1はトランス、
2A、2Bはこのトランス1の巻線IA、IBの出力電
圧をそれぞれ整流するダイオードブリッジ、3はダイオ
ードブリッジ2Aの整流出力電圧を平滑化する平滑コン
デンサ、4はDC/DCC/式−タとしての電源装置、
11はその負荷(この例では制御装置)である。またF
Lはダイオードブリッジ2Bの整流出力電圧を平滑化す
るフィルタ、6はこのフィルタFLの出力電圧を所定の
検出レベル■Sと比較するコンパレータである。
将来の停電検出回路はこの第3図のようにトランス1か
らの交流電源電圧を整流し、リップル除去のためのフィ
ルタFLを通して直流電圧に変換した後、この電圧を低
下検出レベル■Sと比較して停電検出信号8を作ってい
た。
またこの場合、停電をその瞬時に検出するのではなく、
平滑コンデンサ3の存在によって停電後暫時は電源装置
4、従って負荷11が正常に動作し得るので、この間に
負荷11内のコンピュータに停電準備動作(必要なデー
タのバックアップRAMへの退避など)を行わせるため
に、この準備動作を行う時間分だけ早めに停電検出信号
を出すとしても、なお停電後、停電検出信号出力までに
若干の待ち時間を取ることができ、この停電検出待ち時
間はフィルタFLの放電時定数を選ぶことで得られて来
た。FIG. 3 shows an example of the configuration of a system including this type of power failure detection circuit. In the figure, 01 is an AC power supply, 1 is a transformer,
2A and 2B are diode bridges that rectify the output voltages of the windings IA and IB of this transformer 1, 3 is a smoothing capacitor that smoothes the rectified output voltage of the diode bridge 2A, and 4 is a DC/DCC/formula-ta. power supply,
11 is its load (in this example, a control device). Also F
L is a filter that smoothes the rectified output voltage of the diode bridge 2B, and 6 is a comparator that compares the output voltage of this filter FL with a predetermined detection level S. As shown in Figure 3, future power failure detection circuits will rectify the AC power supply voltage from transformer 1, convert it to DC voltage through filter FL for ripple removal, and then compare this voltage with drop detection level S. power outage detection signal 8 was generated. In this case, instead of detecting a power outage instantly,
Due to the presence of the smoothing capacitor 3, the power supply 4, and therefore the load 11, can operate normally for a while after a power outage, so during this time, the computer in the load 11 performs power outage preparation operations (e.g., saving necessary data to a backup RAM). Even if the power outage detection signal is issued earlier by the time taken to perform this preparation operation, there will still be some waiting time after the power outage until the power outage detection signal is output, and this power outage detection waiting time is It has been obtained by choosing the discharge time constant of .
第3図におけるフィルタFLはダイオードブリッジ2B
の整流出力電圧からリップルを除去するための役割に基
づく放電時定数と前記の停電検出待ち時間を適切に得る
ための放電時定数との2つの時定数を満足し得るもので
なければならない。
しかし負荷の種類によっては前記の停電検出待ち時間を
特に短かくしなければならぬものもあり、このようにし
ようとすると、リップル除去に必要な時定数が確保でき
なくなるという問題があった。
また第3図の平滑コンデンサ3の回路のように中小容量
の電源装置において一般的なコンデンサ入力型では、交
流電源電圧のピーク値付近のみが、コンデンサ3の充電
に関わる。すなわち交流ピーク付近の電圧で電源装置4
0入力整流電圧が決まるが、停電検出回路は全波整流波
形にフィルタFLをかけた値を交流電圧検出値としてい
るので、平滑コンデンサ3の出力電圧とフィルタFLの
出力電圧とが正確には対応せず、特に単相交流で波形が
歪んだ場合には電源装置4の入力直流電圧と停電検出回
路の検出電圧との誤差が大きくなり、電源装置4側と停
電検出回路側とで停電検出上の協調がとれないという問
題もあった。
そこで本発明は前記の問題を解消し得る停電検出回路を
提供することを課題とする。The filter FL in FIG. 3 is a diode bridge 2B.
It must be able to satisfy two time constants: a discharge time constant based on its role in removing ripples from the rectified output voltage of the circuit, and a discharge time constant in order to appropriately obtain the power failure detection waiting time. However, depending on the type of load, there are some cases in which the above-mentioned power failure detection waiting time must be particularly shortened, and if this is attempted, there is a problem that the time constant necessary for ripple removal cannot be secured. Further, in a capacitor input type circuit that is common in small to medium capacity power supply devices, such as the circuit of the smoothing capacitor 3 shown in FIG. 3, only the vicinity of the peak value of the AC power supply voltage is involved in charging the capacitor 3. In other words, the power supply device 4 at a voltage near the AC peak
The 0 input rectified voltage is determined, but since the power outage detection circuit uses the value obtained by multiplying the full-wave rectified waveform by the filter FL as the AC voltage detection value, the output voltage of the smoothing capacitor 3 and the output voltage of the filter FL do not exactly correspond. If the waveform is distorted, especially in single-phase AC, the error between the input DC voltage of the power supply 4 and the detection voltage of the power failure detection circuit will become large, and the power failure detection will be difficult between the power supply 4 side and the power failure detection circuit side. There was also the problem of a lack of coordination. Therefore, it is an object of the present invention to provide a power failure detection circuit that can solve the above-mentioned problems.
前記の課題を解決するために本発明の回路は、r(コン
パレータ6、ANDゲート10などを介し、)交流電源
電圧のピーク値が所定値を下回ったことを検出して(コ
ンデンサC1,抵抗RLR2、ダイオードD1、コンパ
レータ12などを介し)停電検出信号(8など)を出力
するjものとする。In order to solve the above problems, the circuit of the present invention detects that the peak value of the AC power supply voltage r (via the comparator 6, AND gate 10, etc.) has fallen below a predetermined value (via the capacitor C1, the resistor RLR2, etc.) , diode D1, comparator 12, etc.) outputs a power failure detection signal (8, etc.).
交流電圧のピーク値の低下を検出することで、電源整流
電圧平滑化のためのフィルタ遅れ時間と無関係に停電を
迅速検出したのち、平滑コンデンサ3の電圧低下速度に
合わせた適切な遅れ時間を経て、停電検出信号8を出力
するようにしたものである。By detecting the drop in the peak value of the AC voltage, a power outage can be quickly detected regardless of the filter delay time for smoothing the power supply rectification voltage, and then after an appropriate delay time that matches the voltage drop speed of the smoothing capacitor 3. , a power outage detection signal 8 is output.
第1図は本発明の一実施例としての回路図で第3図に対
応するものである。また第2図は第1図の要部動作説明
用の波形図である。
第1図は第3図に対応し停電検出回路のみが異なる。次
に第2図を参照しつつ第1図の要部の構成と動作を説明
する。即ち第1図において6(6A、6B>は交流電源
01の検出電圧としてのトランス巻線IBの交流電圧の
瞬時レベルを検出レベルVSIと比較するコンパレータ
で、6Aは入力交流電圧の正の半波が、6Bは反転アン
プ9を介し入力交流電圧を反転することにより入力交流
電圧の負の半波の絶対値が、それぞれ検出レベルVSI
を越えると“L”の信号を出力し、この状態以外では“
H”の信号を出力する。第2図(1)はトランス巻線I
Bの電圧波形(電源検出波形)と、このコンパレータ6
A、6Bによる検出のレベルVSI との関係を示す、
10はこのコンパレータ6A、6Bの出力信号のAND
条件を取るANDゲートでその出力信号の波形は第2図
(2)のようになり、同図時点t1以前のように交流電
源検出電圧のピーク値の絶対値が検出レベルVSIを越
える状態(つまり正常状態)にあるときは、ANDゲー
ト10は“H″、“L”の信号の交互の出力を繰り返す
が、第2図の時点t1以後のように、前記交流電源検出
電圧のピーク値の絶対値が検出レベル■S1を下まわる
状態(つまり停電状B)になると、ANDゲート10は
“H”の信号を出し続けるようになる。このようにして
コンパレータ6およびANDゲート10は交流電源電圧
のピーク値の低下を監視している。
次にコンデンサC1、抵抗R1,R2、ダイオードD1
、コンパレータ12からなる回路は、交流電源の前記の
ピーク値低下検出後、停電検出信号8を負荷11へ出力
するまでの停電検出待ち時間TWを作るタイマ回路を構
成している。この場合抵抗R1,R2の値はR1(R2
に選ばれている。即ちコンデンサC1は、ANDゲート
10の”H”の出力信号により高抵抗R2を介してゆる
やかに充電され、他方、ANDゲート10の“L”の出
力信号によりダイオードDI、抵抗R1を介して急速に
放電される。従ってコンデンサC1の両端電圧は第2図
(3)のように、時点t1以前には殆ど上昇せず、時点
t1以後、R2・C1の時定数でゆるやかに上昇して行
く。
コンパレータ12はこのコンデンサC1の電圧を所定電
圧(検出時間レベル)VS2と比較し、第2図(4)の
ようにコンデンサC1電圧がレベルVS2を越える時点
L2において、“°H”の停電検出信号8を出力する。
このようにして時点t1からt2までの期間が停電検出
待ち時間TWとなる。FIG. 1 is a circuit diagram as an embodiment of the present invention, and corresponds to FIG. 3. Further, FIG. 2 is a waveform diagram for explaining the operation of the main part of FIG. 1. FIG. 1 corresponds to FIG. 3, and only the power failure detection circuit is different. Next, the configuration and operation of the main parts shown in FIG. 1 will be explained with reference to FIG. 2. That is, in FIG. 1, 6 (6A, 6B> is a comparator that compares the instantaneous level of the AC voltage of the transformer winding IB as the detection voltage of the AC power supply 01 with the detection level VSI, and 6A is the positive half wave of the input AC voltage. However, in 6B, by inverting the input AC voltage through the inverting amplifier 9, the absolute value of the negative half wave of the input AC voltage becomes the detection level VSI.
When it exceeds this state, it outputs an “L” signal, and in other than this state, it outputs a “L” signal.
Outputs a signal of "H". Figure 2 (1) shows the transformer winding I.
B voltage waveform (power supply detection waveform) and this comparator 6
A, showing the relationship with the detection level VSI by 6B,
10 is the AND of the output signals of the comparators 6A and 6B.
The waveform of the output signal of the AND gate that takes the conditions becomes as shown in Figure 2 (2), and the absolute value of the peak value of the AC power supply detection voltage exceeds the detection level VSI (i.e., before time t1 in the figure). In the normal state), the AND gate 10 repeats alternately outputting "H" and "L" signals, but as after time t1 in FIG. 2, the absolute peak value of the AC power supply detection voltage When the value falls below the detection level ■S1 (that is, power outage condition B), the AND gate 10 continues to output an "H" signal. In this way, the comparator 6 and the AND gate 10 monitor the decrease in the peak value of the AC power supply voltage. Next, capacitor C1, resistors R1, R2, diode D1
, the comparator 12 constitutes a timer circuit that creates a power outage detection waiting time TW from when the drop in the peak value of the AC power source is detected to when the power outage detection signal 8 is output to the load 11. In this case, the values of resistors R1 and R2 are R1(R2
has been selected. That is, the capacitor C1 is slowly charged via the high resistance R2 by the "H" output signal of the AND gate 10, and rapidly charged via the diode DI and the resistor R1 by the "L" output signal of the AND gate 10. Discharged. Therefore, as shown in FIG. 2 (3), the voltage across the capacitor C1 hardly increases before time t1, and after time t1, it gradually increases with the time constant of R2·C1. The comparator 12 compares the voltage of this capacitor C1 with a predetermined voltage (detection time level) VS2, and at the time L2 when the capacitor C1 voltage exceeds the level VS2 as shown in FIG. Outputs 8. In this way, the period from time t1 to t2 becomes the power failure detection waiting time TW.
本発明によれば交流電源電圧の低下をその波形のピーク
値で判別するようにしたので、次のような効果を得るこ
とができる。
■停電検出波形にフィルタをかける必要がなくなり、検
出待ち時間TWのためだけに遅れ要素(フィルタ、タイ
マ)を使えるので、時間設定が任意に行なえる。
■コンデンサ入力型の電源装置を対象として、交流波形
が歪んだ場合にも、入力コンデンサ電圧(第1図のVD
C)に対して従来より誤差の少ない低下検出が可能であ
る。According to the present invention, since a drop in AC power supply voltage is determined by the peak value of its waveform, the following effects can be obtained. - There is no need to apply a filter to the power failure detection waveform, and a delay element (filter, timer) can be used only for the detection waiting time TW, so the time can be set arbitrarily. ■For capacitor input type power supplies, even if the AC waveform is distorted, the input capacitor voltage (VD in Figure 1)
For C), it is possible to detect a drop with less error than in the past.
第1図は本発明の一実施例としての構成を示す回路図、
第2図は第1図の要部動作説明用の波形図、第3図は第
1図に対応する従来の回路図である。
01:交流電源、1ニドランス、LA、IB:巻線、2
A:ダイオードブリッジ、3:平滑コンデンサ、4:電
源装置、6 (6A、6B) :、12:コンパレータ
、8:停電検出信号、9:反転アンプ、10:ANDゲ
ート、11:負荷、C1:コンデンサ、RIR2:抵抗
、D1=ダイオード、VSI:検出レベル、VS2:検
出時間レベル、TW:停電検出待ち時景6FIG. 1 is a circuit diagram showing a configuration as an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the main part of FIG. 1, and FIG. 3 is a conventional circuit diagram corresponding to FIG. 1. be. 01: AC power supply, 1 Nidorance, LA, IB: Winding, 2
A: Diode bridge, 3: Smoothing capacitor, 4: Power supply, 6 (6A, 6B):, 12: Comparator, 8: Power failure detection signal, 9: Inverting amplifier, 10: AND gate, 11: Load, C1: Capacitor , RIR2: Resistor, D1=Diode, VSI: Detection level, VS2: Detection time level, TW: Power outage detection waiting scene 6
Claims (1)
検出して停電検出信号を出力することを特徴とする停電
検出回路。1) A power outage detection circuit that detects that the peak value of AC power supply voltage has fallen below a predetermined value and outputs a power outage detection signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13757590A JPH0431772A (en) | 1990-05-28 | 1990-05-28 | Service interruption detecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13757590A JPH0431772A (en) | 1990-05-28 | 1990-05-28 | Service interruption detecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0431772A true JPH0431772A (en) | 1992-02-03 |
Family
ID=15201927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13757590A Pending JPH0431772A (en) | 1990-05-28 | 1990-05-28 | Service interruption detecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0431772A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5611412A (en) * | 1995-07-07 | 1997-03-18 | Otis Elevator Company | Elevator car hitch |
WO2012098781A1 (en) * | 2011-01-20 | 2012-07-26 | オリンパス株式会社 | Power supply device |
JP2014054018A (en) * | 2012-09-05 | 2014-03-20 | Sony Corp | Power supply monitor device, ac-dc conversion device, and method for controlling power supply monitor device |
-
1990
- 1990-05-28 JP JP13757590A patent/JPH0431772A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5611412A (en) * | 1995-07-07 | 1997-03-18 | Otis Elevator Company | Elevator car hitch |
WO2012098781A1 (en) * | 2011-01-20 | 2012-07-26 | オリンパス株式会社 | Power supply device |
US9099931B2 (en) | 2011-01-20 | 2015-08-04 | Olympus Corporation | Power supply device |
JP2014054018A (en) * | 2012-09-05 | 2014-03-20 | Sony Corp | Power supply monitor device, ac-dc conversion device, and method for controlling power supply monitor device |
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