JPH04312072A - Vertical deflection circuit - Google Patents
Vertical deflection circuitInfo
- Publication number
- JPH04312072A JPH04312072A JP10521491A JP10521491A JPH04312072A JP H04312072 A JPH04312072 A JP H04312072A JP 10521491 A JP10521491 A JP 10521491A JP 10521491 A JP10521491 A JP 10521491A JP H04312072 A JPH04312072 A JP H04312072A
- Authority
- JP
- Japan
- Prior art keywords
- vertical deflection
- crt
- deflection current
- level
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004804 winding Methods 0.000 claims abstract description 8
- 238000001514 detection method Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 abstract description 7
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Abstract
Description
〔発明の目的〕 [Purpose of the invention]
【０００１】0001
【産業上の利用分野】本発明はカラ−テレビジョン受像
機などの垂直偏向回路に係わり、特にＣＲＴビ−ムのブ
ランキングに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to vertical deflection circuits for color television receivers and the like, and more particularly to blanking of CRT beams.
【０００２】0002
【従来の技術】従来この種のテレビジョン受像機の垂直
偏向回路では、ＣＲＴの垂直帰線期間にＣＲＴビ−ムを
消去するため、垂直偏向出力段から出力される鋸波状の
垂直偏向電流から垂直帰線期間発生するパルスを作り、
このパルスにより前記垂直帰線期間では映像信号を黒レ
ベル又は黒レベルより更に黒側に制御することにより、
前記ＣＲＴビ−ムを出さないようにしている。2. Description of the Related Art Conventionally, in the vertical deflection circuit of this type of television receiver, in order to erase the CRT beam during the vertical blanking period of the CRT, the sawtooth vertical deflection current outputted from the vertical deflection output stage is used. Create a pulse that occurs during the vertical retrace period,
By controlling the video signal to the black level or even blacker than the black level during the vertical retrace period using this pulse,
The CRT beam is not emitted.
【０００３】図３は従来の垂直偏向回路におけるＣＲＴ
ビ−ムのブランキング方法を説明する回路図である。鋸
波状の垂直偏向電流を出力する垂直出力段を形成するト
ランジスタＱ１、Ｑ２の共通エミッタからは垂直偏向電
流が出力され、これが垂直偏向巻線２に供給される。
又、前記トランジスタＱ１、Ｑ２の共通エミッタの出力
段に現れる帰線期間の高い電圧レベルは抵抗５、６によ
り分圧されて、信号処理ＩＣ（Ｖ．ＢＬＫ）８に入力さ
れている。これにより、信号処理ＩＣ８は垂直帰線期間
にＣＲＴへ入力する映像信号を黒レベルか或いはそれ以
下にする信号処理を行う。このため、前記垂直帰線期間
にはＣＲＴビ−ムはＣＲＴの蛍光面に照射されないこと
になる。しかし、上記回路にて何等かの故障により前記
出力段１から出力されている垂直偏向電流が殆ど０にな
った場合、ＣＲＴビ−ムは横一文字状態になって蛍光面
の中央に集中するため、ＣＲＴの蛍光面に焼き付けがお
こり、高価なＣＲＴを交換しなければならないような損
害を与える可能性があった。FIG. 3 shows a CRT in a conventional vertical deflection circuit.
FIG. 2 is a circuit diagram illustrating a beam blanking method. A vertical deflection current is outputted from the common emitters of transistors Q1 and Q2 forming a vertical output stage that outputs a sawtooth vertical deflection current, and is supplied to the vertical deflection winding 2. Further, the high voltage level during the retrace period appearing at the output stage of the common emitters of the transistors Q1 and Q2 is divided by resistors 5 and 6 and input to a signal processing IC (V.BLK) 8. Thereby, the signal processing IC 8 performs signal processing to bring the video signal input to the CRT to the black level or lower during the vertical retrace period. Therefore, the CRT beam is not irradiated onto the CRT fluorescent screen during the vertical retrace period. However, if the vertical deflection current output from the output stage 1 becomes almost 0 due to some kind of failure in the above circuit, the CRT beam becomes horizontal and concentrated at the center of the phosphor screen. , the phosphor screen of the CRT may be burnt-in, causing damage that may require replacement of the expensive CRT.
【０００４】0004
【発明が解決しようとする課題】上記の如く従来の垂直
偏向回路では、部品の故障等により前記垂直偏向回路の
出力段から垂直偏向電流が殆ど流れなくなった場合、Ｃ
ＲＴ蛍光面の横中央に高輝度のビ−ムが集中するため、
ＣＲＴ蛍光面に焼き付けがおこり、ＣＲＴを交換しなけ
ればならないというような事故が発生する恐れがあった
。[Problems to be Solved by the Invention] As described above, in the conventional vertical deflection circuit, when almost no vertical deflection current flows from the output stage of the vertical deflection circuit due to component failure, etc., the C
Because the high-intensity beam is concentrated in the horizontal center of the RT fluorescent screen,
There was a risk that burn-in would occur on the CRT's phosphor screen, causing an accident in which the CRT would have to be replaced.
【０００５】そこで本発明は上記の欠点を除去するもの
で、何等かの故障により垂直偏向電流が０又は異常に少
なくなってもＣＲＴの蛍光面に損傷を与えないようにす
ることができる垂直偏向回路を提供することを目的とし
ている。
〔発明の構成〕Therefore, the present invention aims to eliminate the above-mentioned drawbacks, and provides a vertical deflection system that can prevent damage to the phosphor screen of a CRT even if the vertical deflection current becomes zero or abnormally low due to some kind of failure. The purpose is to provide circuits. [Structure of the invention]
【０００６】[0006]
【課題を解決するための手段】本発明は垂直偏向電流を
垂直偏向巻線に供給すると共に、垂直帰線期間はブラン
キング信号を信号処理部に送って、ＣＲＴへ入力する映
像信号を黒レベル又はそれ以下にすることによってＣＲ
Ｔビームを消去する垂直偏向回路において、前記垂直偏
向電流が所定レベル以下になったことを検出する検出回
路と、この検出回路によって前記垂直偏向電流が所定レ
ベル以下になったことが検出されている期間は前記信号
処理部にブランキング信号を常時送る制御回路とを具備
した構成を有する。[Means for Solving the Problems] The present invention supplies a vertical deflection current to a vertical deflection winding, and also sends a blanking signal to a signal processing section during a vertical retrace period to control a video signal input to a CRT at a black level. or lower by CR
The vertical deflection circuit for erasing the T-beam includes a detection circuit for detecting that the vertical deflection current has become below a predetermined level, and a detection circuit for detecting that the vertical deflection current has become below the predetermined level. The period has a configuration including a control circuit that constantly sends a blanking signal to the signal processing section.
【０００７】[0007]
【作用】本発明の垂直偏向回路において、検出回路は垂
直偏向電流が所定レベル以下になったことを検出する。
制御回路は前記検出回路によって前記垂直偏向電流が所
定レベル以下になったことが検出されている期間は信号
処理部にブランキング信号を常時送って、ＣＲＴビーム
を消去する。In the vertical deflection circuit of the present invention, the detection circuit detects when the vertical deflection current has fallen below a predetermined level. The control circuit constantly sends a blanking signal to the signal processing section to erase the CRT beam while the detection circuit detects that the vertical deflection current is below a predetermined level.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図面を参照して説
明する。図１は本発明の垂直偏向回路の一実施例を示し
たブロック図である。１は垂直偏向電流を出力する出力
段で、トランジスタＱ１、Ｑ２から成る。トランジスタ
Ｑ１、Ｑ２の共通エミッタは垂直偏向巻線２及び抵抗５
と抵抗６からなる分圧回路に接続されている。垂直偏向
巻線２の他端はカップリングコンデンサ３と帰還抵抗４
を介して接地されている。帰還抵抗４とカップリングコ
ンデンサ３の接続点はオペアンプ１２の非反転入力端子
に接続されている。抵抗１０と抵抗１１は電圧Ｖｃｃを
分圧して基準電圧ＶＴＨを作るもので、このＶＴＨはオ
ペアンプ１２の反転入力端子に入力されている。オペア
ンプ１２の出力側は抵抗１４とコンデンサ１５からなる
積分回路に接続されている。この積分回路の積分電圧Ｖ
ｃ はオペアンプ１７の反転入力端子に入力される。尚
、抵抗１６はコンデンサ１５の放電用抵抗である。オペ
アンプ１７の非反転入力端子は接地され、その出力側は
ダイオ−ド１８を介してダイオ−ド１９のカソ−ド側に
接続されている。ダイオ−ド１８、１９のカソ−ド側は
抵抗２１を介して信号処理ＩＣ８の入力端子に接続され
ている。
抵抗２１と抵抗２２は信号処理ＩＣ８への入力信号のレ
ベルを調整するものである。又、前記ダイオ−ド１９の
アノ−ド側は分圧抵抗５、６の接続点に接続されている
。ダイオ−ド２０は信号処理ＩＣ８の入力側を負電圧に
クランプするものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the vertical deflection circuit of the present invention. Reference numeral 1 denotes an output stage that outputs a vertical deflection current, and is composed of transistors Q1 and Q2. The common emitter of transistors Q1 and Q2 is connected to vertical deflection winding 2 and resistor 5.
and a resistor 6. The other end of the vertical deflection winding 2 is connected to a coupling capacitor 3 and a feedback resistor 4.
is grounded through. A connection point between the feedback resistor 4 and the coupling capacitor 3 is connected to a non-inverting input terminal of the operational amplifier 12. The resistor 10 and the resistor 11 divide the voltage Vcc to create a reference voltage VTH, and this VTH is input to the inverting input terminal of the operational amplifier 12. The output side of the operational amplifier 12 is connected to an integrating circuit consisting of a resistor 14 and a capacitor 15. The integrated voltage V of this integrating circuit
c is input to the inverting input terminal of the operational amplifier 17. Note that the resistor 16 is a resistor for discharging the capacitor 15. The non-inverting input terminal of the operational amplifier 17 is grounded, and its output side is connected via a diode 18 to the cathode side of a diode 19. The cathode sides of the diodes 18 and 19 are connected to the input terminal of the signal processing IC 8 via a resistor 21. The resistor 21 and the resistor 22 are used to adjust the level of the input signal to the signal processing IC 8. Further, the anode side of the diode 19 is connected to the connection point of the voltage dividing resistors 5 and 6. The diode 20 clamps the input side of the signal processing IC 8 to a negative voltage.
【０００９】次に本実施例の動作について説明する。出
力段１から出力される垂直偏向電流は垂直偏向巻線２を
流れ、カップリングコンデンサ３及び帰還抵抗４を介し
て接地側に至る。又、前記出力段の垂直偏向電流は分圧
抵抗５、６にてある電圧レベルに変換された後、ダイオ
−ド１９、抵抗２１を介して信号処理ＩＣ８に入力され
る。このため、垂直帰線期間は信号処理ＩＣ８によりＣ
ＲＴへ入力される映像信号を黒レベル或いはそれ以下に
する処理が行われ、ＣＲＴビ−ムが消去される。Next, the operation of this embodiment will be explained. The vertical deflection current output from the output stage 1 flows through the vertical deflection winding 2 and reaches the ground side via the coupling capacitor 3 and the feedback resistor 4. Further, the vertical deflection current of the output stage is converted to a certain voltage level by voltage dividing resistors 5 and 6, and then inputted to the signal processing IC 8 via a diode 19 and a resistor 21. Therefore, the vertical retrace period is controlled by the signal processing IC 8.
The video signal input to the RT is processed to be at or below the black level, and the CRT beam is erased.
【００１０】一方、帰還抵抗４には前記垂直偏向電流に
比例した図２（Ａ）に示したような電圧Ｖｆ が現れ、
この電圧がオペアンプ１２の非反転入力に入力される。
オペアンプ１２の反転入力には分圧抵抗１０、１１で作
られた基準電圧ＶＴＨが入力されるため、オペアンプ１
２は前記電圧Ｖｆ と基準電圧ＶＴＨとを比較し、図２
（Ａ）に示したように電圧Ｖｆ が基準電圧ＶＴＨより
も高い期間、その出力を図２（Ｂ）に示す如くハイレベ
ルとする。このオペアンプ１２の出力は抵抗１４とコン
デンサ１５にて積分され、その積分電圧ＶＣ がオペア
ンプ１７の反転入力に入力される。オペアンプ１７は入
力される積分電圧ＶＣ を閾値電圧（ここでは接地レベ
ル）と比較して、前記電圧ＶＣ が閾値電圧以下になる
と、その出力をハイレベルにする動作を行い、これ以外
の場合はその出力電圧はロ−レベルである。このため、
通常、信号処理ＩＣ８はオペアンプ１７の出力に影響さ
れずにその動作を行っている。On the other hand, a voltage Vf as shown in FIG. 2(A) proportional to the vertical deflection current appears in the feedback resistor 4,
This voltage is input to the non-inverting input of the operational amplifier 12. Since the reference voltage VTH created by the voltage dividing resistors 10 and 11 is input to the inverting input of the operational amplifier 12, the operational amplifier 1
2 compares the voltage Vf and the reference voltage VTH, and FIG.
During the period when the voltage Vf is higher than the reference voltage VTH as shown in FIG. 2(A), the output is set at a high level as shown in FIG. 2(B). The output of the operational amplifier 12 is integrated by a resistor 14 and a capacitor 15, and the integrated voltage VC is input to the inverting input of the operational amplifier 17. The operational amplifier 17 compares the input integrated voltage VC with a threshold voltage (ground level in this case), and when the voltage VC becomes less than the threshold voltage, it operates to make its output high level. The output voltage is low level. For this reason,
Normally, the signal processing IC 8 operates without being influenced by the output of the operational amplifier 17.
【００１１】しかし、出力段１から出力される垂直偏向
電流の電流値が０或いは非常に少なくなったような場合
、帰還抵抗４に発生する電圧Ｖｆ が降下し、前記基準
電圧ＶＴＨよりも小さくなるような状態では前記積分電
圧ＶＣ が閾値電圧（接地レベル）以下になるため、オ
ペアンプ１７の出力はハイレベルとなり、このハイレベ
ルの出力信号がダイオ−ド１８を介して信号処理ＩＣ８
の入力端子に印加されて、この入力端子をハイレベルに
保持する。このため、信号処理ＩＣ８が働いてＣＲＴに
送る映像信号を黒レベル或いはそれ以下にしてしまうた
め、ＣＲＴビ−ムは全期間にて消去される。However, when the current value of the vertical deflection current output from the output stage 1 becomes 0 or becomes very small, the voltage Vf generated in the feedback resistor 4 drops and becomes smaller than the reference voltage VTH. In such a state, the integrated voltage VC becomes less than the threshold voltage (ground level), so the output of the operational amplifier 17 becomes high level, and this high level output signal is passed through the diode 18 to the signal processing IC 8.
is applied to the input terminal of , and holds this input terminal at a high level. For this reason, the signal processing IC 8 operates to reduce the video signal sent to the CRT to the black level or lower, so that the CRT beam is erased for the entire period.
【００１２】本実施例によれば、何等かの原因により出
力段１から出力される垂直偏向電流が０又は極小になる
と、これをオペアンプ１２、１７等で構成される検出回
路にて検出し、この検出期間中、信号処理ＩＣ８の入力
端子をハイレベルに保持することにより、ＣＲＴビ−ム
を全期間に亙って消去することができる。このため、従
来のようにＣＲＴの蛍光面に横一文字の高輝度ビ−ムが
当たるようなことが防止され、垂直偏向電流が０又極小
になるような故障が生じても、ＣＲＴの蛍光面を損傷し
てこれを交換しなければならないというような事故を防
止することができる。According to this embodiment, when the vertical deflection current output from the output stage 1 becomes zero or extremely small due to some reason, this is detected by the detection circuit composed of operational amplifiers 12, 17, etc. During this detection period, by holding the input terminal of the signal processing IC 8 at a high level, the CRT beam can be erased over the entire period. This prevents the horizontal high-intensity beam from hitting the CRT's phosphor screen as in the past, and even if a failure occurs where the vertical deflection current becomes zero or minimal, the CRT's phosphor screen Accidents such as damage to the product and the need to replace it can be prevented.
【００１３】[0013]
【発明の効果】以上記述した如く本発明の垂直偏向回路
によれば、何等かの故障により垂直偏向電流が０又は異
常に少なくなってもＣＲＴの蛍光面に損傷を与えないよ
うにすることができる。As described above, according to the vertical deflection circuit of the present invention, even if the vertical deflection current becomes 0 or abnormally low due to some kind of failure, it is possible to prevent damage to the fluorescent screen of a CRT. can.
【図１】本発明の垂直偏向回路の一実施例を示した回路
図。FIG. 1 is a circuit diagram showing an embodiment of a vertical deflection circuit of the present invention.
【図２】図１に示した垂直偏向回路の動作を説明する波
形図。FIG. 2 is a waveform diagram illustrating the operation of the vertical deflection circuit shown in FIG. 1.
【図３】従来の垂直偏向回路の一例を示した回路図。FIG. 3 is a circuit diagram showing an example of a conventional vertical deflection circuit.
１ 出力段
２ 垂直偏向巻線４ 帰還抵抗
５、６、１０、１１ 分圧抵抗
８ 信号処理
ＩＣ、１２、１７ オペアンプ
１８，１９ ダイオ−ド1 Output stage
2 Vertical deflection winding 4 Feedback resistor
5, 6, 10, 11 Voltage dividing resistor 8 Signal processing
IC, 12, 17 Operational amplifier 18, 19 Diode
Claims (1)
共に、垂直帰線期間はブランキング信号を信号処理部に
送って、ＣＲＴへ入力する映像信号を黒レベル又はそれ
以下にすることによってＣＲＴビームを消去する垂直偏
向回路において、前記垂直偏向電流が所定レベル以下に
なったことを検出する検出回路と、この検出回路によっ
て前記垂直偏向電流が所定レベル以下になったことが検
出されている期間は前記信号処理部にブランキング信号
を常時送る制御回路とを具備したことを特徴とする垂直
偏向回路。Claim 1: A vertical deflection current is supplied to a vertical deflection winding, and a blanking signal is sent to a signal processing section during a vertical retrace period to reduce the video signal input to a CRT to a black level or lower. A vertical deflection circuit for erasing a CRT beam includes a detection circuit for detecting that the vertical deflection current has become below a predetermined level, and a detection circuit for detecting that the vertical deflection current has become below a predetermined level. A vertical deflection circuit comprising: a control circuit that constantly sends a blanking signal to the signal processing section during the period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10521491A JPH04312072A (en) | 1991-04-11 | 1991-04-11 | Vertical deflection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10521491A JPH04312072A (en) | 1991-04-11 | 1991-04-11 | Vertical deflection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04312072A true JPH04312072A (en) | 1992-11-04 |
Family
ID=14401423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10521491A Withdrawn JPH04312072A (en) | 1991-04-11 | 1991-04-11 | Vertical deflection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04312072A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998038795A1 (en) * | 1997-02-26 | 1998-09-03 | Thomson Consumer Electronics, Inc. | Scan loss detector |
-
1991
- 1991-04-11 JP JP10521491A patent/JPH04312072A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998038795A1 (en) * | 1997-02-26 | 1998-09-03 | Thomson Consumer Electronics, Inc. | Scan loss detector |
| US5856730A (en) * | 1997-02-26 | 1999-01-05 | Thomson Consumer Electronics, Inc. | Scan loss detector |
| GB2337678A (en) * | 1997-02-26 | 1999-11-24 | Thomson Consumer Electronics | Scan loss detector |
| GB2337678B (en) * | 1997-02-26 | 2001-03-07 | Thomson Consumer Electronics | Scan loss detector |
| KR100541789B1 (en) * | 1997-02-26 | 2006-01-12 | 톰슨 콘슈머 일렉트로닉스, 인코포레이티드 | Scan loss detector |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980711 |