JPH04307520A - Active matrix type liquid crystal display device - Google Patents
Active matrix type liquid crystal display deviceInfo
- Publication number
- JPH04307520A JPH04307520A JP3073024A JP7302491A JPH04307520A JP H04307520 A JPH04307520 A JP H04307520A JP 3073024 A JP3073024 A JP 3073024A JP 7302491 A JP7302491 A JP 7302491A JP H04307520 A JPH04307520 A JP H04307520A
- Authority
- JP
- Japan
- Prior art keywords
- picture element
- liquid crystal
- electrode
- data line
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 27
- 239000011159 matrix material Substances 0.000 title claims description 14
- 239000000463 material Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract description 2
- 238000002788 crimping Methods 0.000 abstract 1
- 230000006698 induction Effects 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、液晶表示装置に属し、
その中でも各絵素毎にトランジスタを有するアクティブ
マトリクス型液晶表示装置に関する。[Industrial Application Field] The present invention belongs to a liquid crystal display device,
Among these, the present invention relates to an active matrix liquid crystal display device having a transistor for each picture element.
【０００２】0002
【従来の技術】アクティブマトリクス型液晶表示装置を
構成する各絵素では、その中に設けられた絵素電極と対
向電極とで挟まれた部分の液晶だけが、印加された電圧
や電流に応答して透過光あるいは散乱光などを制御する
事ができる。この場合、絵素電極の無い部分が充分に遮
光されていなければ、制御できない光の漏れが発生し、
表示装置のコントラストが低下する。この事を抑止する
為には、絵素電極の無い部分にあらたに遮光膜を積層し
て設けるか、あるいは、絶縁膜を介して、遮光性のスキ
ャンラインとデータラインそれぞれに絵素電極を被せる
必要がある。前者の方法では、いわゆるアライメントマ
ージンを考慮した設計によって、遮光性膜の無い部分の
比率（以下開口率と呼ぶ）が低下する。[Prior Art] In each picture element constituting an active matrix liquid crystal display device, only the liquid crystal in the portion sandwiched between the picture element electrode and the counter electrode provided therein responds to applied voltage or current. It is possible to control transmitted light or scattered light. In this case, if the area without the picture element electrode is not sufficiently shielded from light, uncontrollable light leakage will occur.
The contrast of the display device is reduced. In order to prevent this, a new layer of light-shielding film should be added to the area where there is no pixel electrode, or a pixel electrode should be placed over each of the light-shielding scan line and data line through an insulating film. There is a need. In the former method, the ratio of the portion without a light-shielding film (hereinafter referred to as the aperture ratio) is reduced due to the design taking into account the so-called alignment margin.
【０００３】以下、従来技術の一例として、開口率を上
げる為、遮光性のスキャンラインとデータラインそれぞ
れに、絶縁膜を介して絵素電極を被せた構造のアクティ
ブマトリクス型液晶表示装置について説明する。図４は
その略平面図、図５は図４にあるＡ−Ｂ間断面図、図６
はＣ−Ｄ間断面図である。[0003] As an example of the prior art, an active matrix liquid crystal display device having a structure in which a light-shielding scan line and a data line are each covered with a pixel electrode via an insulating film in order to increase the aperture ratio will be described below. . 4 is a schematic plan view thereof, FIG. 5 is a sectional view taken along A-B in FIG. 4, and FIG.
is a sectional view taken along line CD.
【０００４】光透過性の基板４１上には、厚さ２５０Å
の半導体層４２が島状にパターニングされて配され、そ
の上には厚さ３０００Åのゲート絶縁膜４３が全面に被
着されている。半導体層の一部と交差する形の分岐部分
４４１を備えたスキャンライン４４は、クロム等の遮光
性金属薄膜３０００Åの被着とパターニングによって形
成され、この後にＢやＰなどのイオン打ち込みを行った
結果、半導体層４２は、チャネル部分４２２と、ソース
４２３、ドレイン４２１とに分離されている。いわゆる
セルファライン構造である。厚み５０００Åの層間絶縁
膜４５を全面に被着した後、ドレインスルーホール４５
１部分の層間絶縁膜４５とゲート絶縁膜４３とを除去し
、更にこの上にデータライン４６を設ける事によって、
ドレイン４２１とデータライン４６とが接続されている
。データライン４６は、アルミニウムなどやはり遮光性
の金属薄膜４０００Åの被着とパターニングとで形成さ
れている。絵素絶縁膜４７は、全面に２μｍの厚みで被
着された後、ソーススルーホール４７１部分が除去され
る。更に同じ部分の層間絶縁膜とゲート絶縁膜とを除去
した後に絵素電極４８が被着、パターニングされ、ソー
ス４２３と接続されている。絵素電極４８は、隣接する
絵素電極とのギャップを、スキャンラインあるいはデー
タラインの上に限定する様にパターニングされており、
この結果、スキャンラインとデータラインとで遮光され
た部分以外の全領域の液晶に対する制御を可能にしてい
る。[0004] On the light-transmitting substrate 41, there is a layer having a thickness of 250 Å.
A semiconductor layer 42 is patterned into an island shape, and a gate insulating film 43 having a thickness of 3000 Å is deposited on the entire surface thereof. A scan line 44 having a branch portion 441 that intersects a part of the semiconductor layer is formed by depositing and patterning a 3000 Å light-shielding metal thin film such as chromium, followed by ion implantation of B, P, etc. As a result, the semiconductor layer 42 is separated into a channel portion 422, a source 423, and a drain 421. This is a so-called self-line structure. After depositing an interlayer insulating film 45 with a thickness of 5000 Å on the entire surface, a drain through hole 45 is formed.
By removing part of the interlayer insulating film 45 and gate insulating film 43 and further providing the data line 46 on top of this,
Drain 421 and data line 46 are connected. The data line 46 is formed by depositing and patterning a 4000 Å thin film of a light-shielding metal such as aluminum. After the picture element insulating film 47 is deposited to a thickness of 2 μm over the entire surface, the source through hole 471 portion is removed. Further, after removing the interlayer insulating film and the gate insulating film at the same portion, a picture element electrode 48 is deposited, patterned, and connected to the source 423. The picture element electrode 48 is patterned to limit the gap between the picture element electrode and the adjacent picture element electrode above the scan line or the data line.
As a result, it is possible to control the entire area of the liquid crystal except for the portions shaded by the scan lines and data lines.
【０００５】以上が、開口率の向上を主たる目的として
構成したアクティブマトリクス型液晶表示装置の従来例
である。The above are conventional examples of active matrix liquid crystal display devices constructed with the main purpose of improving the aperture ratio.
【０００６】[0006]
【発明が解決しようとする課題】上記従来例に示した構
造においては、トランジスタのゲートに接続されたスキ
ャンラインと、同じトランジスタのソースに接続された
絵素電極との積層部分が存在し、この間で、絶縁膜を介
した容量（以下ＣＳＰと呼ぶ）が形成される。よく知ら
れている様に、ＣＳＰは、トランジスタのチャネル部分
でゲートとソースとの間に形成される容量（以下Ｃｇｓ
と呼ぶ）と共に、絵素電位の片側方向へのシフト（以下
レベルシフトと呼ぶ）の原因になっている。２回の垂直
走査期間内でのレベルシフトの様子を、他の電位と共に
図７に示す。７１がトランジスタのゲート電位であり、
選択期７０１から保持期７０２へと移行するとき、ゲー
ト電位７１のパルス高に比例して、絵素電位７２は、こ
の場合負の方向へレベルシフト７２１の分だけ移動する
。図７は１垂直走査期間毎に絵素電位を反転しているが
、この反転に拘らず、いずれの走査期間も同一方向にレ
ベルシフトが起こり、液晶層を挟んで反対側にある共通
電極の共通電位７３を、レベルシフトを含んだ絵素電位
のセンターに合わせる必要がある。しかし、レベルシフ
トは、液晶層の容量に依存する。そして、液晶層の容量
は、透過光や散乱光の制御状態に依って異なる。つまり
、表示の状態によってレベルシフトの量は異なり、共通
電位を合わせるべき絵素電位のセンターを一律に決定す
ることはできない。この様にして発生した共通電位と絵
素電位のセンターとの電位差は、表示特性に対し、コン
トラストの低下、フリッカーの発生といった影響を及ぼ
し、更に液晶層の長時間動作安定性を阻害する。[Problems to be Solved by the Invention] In the structure shown in the above-mentioned conventional example, there is a laminated portion of the scan line connected to the gate of the transistor and the pixel electrode connected to the source of the same transistor. Thus, a capacitance (hereinafter referred to as CSP) via an insulating film is formed. As is well known, CSP is the capacitance (hereinafter referred to as Cgs) formed between the gate and source in the channel portion of a transistor.
(hereinafter referred to as "level shift"), as well as a shift of the picture element potential in one direction (hereinafter referred to as "level shift"). FIG. 7 shows the level shift within two vertical scanning periods together with other potentials. 71 is the gate potential of the transistor,
When transitioning from the selection period 701 to the holding period 702, the picture element potential 72 moves in the negative direction by the level shift 721 in proportion to the pulse height of the gate potential 71. In FIG. 7, the pixel potential is inverted every vertical scanning period, but regardless of this inversion, a level shift occurs in the same direction in every scanning period, and the level shift of the common electrode on the opposite side of the liquid crystal layer occurs. It is necessary to align the common potential 73 with the center of the picture element potential including level shift. However, the level shift depends on the capacitance of the liquid crystal layer. The capacity of the liquid crystal layer varies depending on the control state of transmitted light and scattered light. In other words, the amount of level shift varies depending on the display state, and it is not possible to uniformly determine the center of the picture element potentials to which the common potential should be matched. The potential difference between the common potential and the center of the picture element potential, which is generated in this manner, has an effect on the display characteristics such as a decrease in contrast and the occurrence of flicker, and further impairs the long-term operation stability of the liquid crystal layer.
【０００７】[0007]
【課題を解決するための手段】本発明では、そもそもレ
ベルシフトを誘発する原因であるＣＳＰとＣｇｓのうち
ＣＳＰを大幅に低減する為、スキャンラインと絵素電極
との絶縁膜を介した積層部分の全部または一部に、デー
タラインに接続されかつデータラインから分岐したシー
ルド電極を、厚さ方向の両側に絶縁膜を介し、スキャン
ラインと絵素電極との間に挟持して積層する。[Means for Solving the Problems] In the present invention, in order to significantly reduce CSP among CSP and Cgs, which are the causes of level shifts in the first place, the laminated portion between the scan line and the pixel electrode is A shield electrode connected to the data line and branched from the data line is laminated on all or a part of the data line with an insulating film interposed between the scan line and the pixel electrode on both sides in the thickness direction.
【０００８】[0008]
【実施例】以下、本実施例を適用したアクティブマトリ
クス型液晶表示装置の実施例を説明する。図１はその略
平面図、図２は図１のＣ−Ｄ間断面図である。Embodiment An embodiment of an active matrix liquid crystal display device to which this embodiment is applied will be described below. FIG. 1 is a schematic plan view thereof, and FIG. 2 is a sectional view taken along line CD in FIG.
【０００９】光透過性の基板１１、半導体層１２、ゲー
ト絶縁膜１３、分岐部分１４１を備えたスキャンライン
１４、層間絶縁膜１５とそのドレインスルーホール１５
１、絵素絶縁膜１７とそのソーススルーホール１７１、
および絵素電極１８は、本実施例では前出の従来例と同
じ構成である。本発明の適用によって直接変更されたの
は、シールド電極１６１が新たに配された点である。こ
のとき、シールド電極が、データライン１６と同時に被
着された、データラインと同一の材料によって形成され
るものであれば、プロセスを追加する事無くシールド電
極が設けられる事になる。これはプロセスの簡略化を目
的とした請求項２に属する発明の実施例である。シール
ド電極は、データラインと分岐して接続し、絵素電極１
８とスキャンライン１４との積層部分の約９５％の領域
に配した。１００％にならないのは、隣接するデータラ
インとの短絡を避ける為である。具体的な積層構造とし
ては、図２に示す様に、シールド電極１６１を、層間絶
縁膜１５を介してスキャンライン１４１の一部と積層し
、一方、厚さ方向の反対側では、絵素絶縁膜１７を介し
て絵素電極１８の一部と積層する。スキャンラインと絵
素電極との積層部分に、シールド電極の全部を含むか、
あるいは一部分を含むかは、アライメントマージンの余
裕、開口率、低減されるＣＳＰの量などを考えて決める
べきである。これに合わせて、データライン１６（シー
ルド電極１６１を含む）以外の構成要素についても必要
に応じてディメンジョンを最適化すれば良く、本実施例
と従来例との関係は特許請求の範囲を更に規定するもの
ではない。A light-transmissive substrate 11 , a semiconductor layer 12 , a gate insulating film 13 , a scan line 14 having a branch portion 141 , an interlayer insulating film 15 and its drain through hole 15
1. Picture element insulating film 17 and its source through hole 171,
In this embodiment, the picture element electrode 18 has the same structure as in the conventional example described above. What is directly changed by applying the present invention is that a shield electrode 161 is newly arranged. At this time, if the shield electrode is formed of the same material as the data line and deposited at the same time as the data line 16, the shield electrode can be provided without any additional process. This is an embodiment of the invention belonging to claim 2 aimed at simplifying the process. The shield electrode is branched and connected to the data line, and is connected to the pixel electrode 1.
8 and scan line 14 in about 95% of the laminated area. The reason why it is not 100% is to avoid short circuits with adjacent data lines. Specifically, as shown in FIG. 2, the shield electrode 161 is laminated with a part of the scan line 141 via the interlayer insulating film 15, while on the opposite side in the thickness direction, a pixel insulator is formed. It is laminated with a part of the picture element electrode 18 via the film 17. Does the stacked area between the scan line and pixel electrode include all of the shield electrode?
Or whether to include a portion should be determined by considering the alignment margin, the aperture ratio, the amount of CSP to be reduced, etc. In accordance with this, the dimensions of components other than the data line 16 (including the shield electrode 161) may be optimized as necessary, and the relationship between this embodiment and the conventional example will further define the scope of the claims. It's not something you do.
【００１０】次に、これまでに説明してきた実施例につ
いて、更に詳細な構成例を示し、特に寄生容量の具体的
な数値を例示する。１絵素のピッチは７２μｍ×７２μ
ｍとした。Next, a more detailed configuration example of the embodiments described above will be shown, and in particular, specific numerical values of the parasitic capacitance will be illustrated. The pitch of one pixel is 72μm x 72μ
It was set as m.
【００１１】半導体層１２は多結晶シリコンで形成する
。形成方法としては、ＬＰＣＶＤ法や、これにレーザア
ニールまたは固相成長など結晶化の促進を加える方法も
ある。膜厚は２５０Åである。半導体層として多結晶シ
リコンを用いる目的は、以降で経るイオン打込プロセス
によるソースドレイン形成を容易にし、セルファライン
構造として前出のＣｇｓを低減させる為であるが、ＣＳ
Ｐの低減を実現しても並列に存在するＣｇｓによってそ
の効果がうすい場合に有効な手段となる。これは請求項
１の効果を補填する目的で、請求項３に記載した範囲に
属する。本実施例は請求項３を含んでおり、ゲート絶縁
膜を厚み３０００Åの酸化シリコンとした場合、Ｃｇｓ
は約０．５ｆＦ（フェムトファラド）に留まっている。The semiconductor layer 12 is made of polycrystalline silicon. Formation methods include the LPCVD method and methods that add acceleration of crystallization such as laser annealing or solid phase growth. The film thickness is 250 Å. The purpose of using polycrystalline silicon as the semiconductor layer is to facilitate source/drain formation through the subsequent ion implantation process and to reduce the aforementioned Cgs as a self-aligned structure.
This is an effective means when even if P is reduced, the effect is weak due to Cgs existing in parallel. This falls within the scope of claim 3 for the purpose of compensating for the effect of claim 1. This embodiment includes claim 3, and when the gate insulating film is made of silicon oxide with a thickness of 3000 Å, Cgs
remains at approximately 0.5 fF (femtofarad).
【００１２】スキャンライン１４とシールド電極１６１
とは、層間絶縁膜である厚さ５０００Åの酸化シリコン
を介して積層される部分で、データラインとスキャンラ
インとのクロス容量（以下ＣＣｒと呼ぶ）の一部となり
、このときＣＣｒは約１６ｆＦになる。またシールド電
極１６１と絵素電極１８とが積層された部分も、絵素絶
縁膜１７を介して容量を形成し、絵素電極とデータライ
ンとの容量（以下ＣＤＰと呼ぶ）の一部となる。絵素絶
縁膜には、コーティングと加熱イミド化によって形成さ
れた厚さ２μｍのポリイミドを用いたが、これは、被着
の容易さ、基板上の平坦化および低誘電率材料である事
などを考慮して選択した例である。例えばこの比誘電率
をεＰＩが２．５ｔ程度であれば、ＣＤＰは約４ｆＦで
ある。Scan line 14 and shield electrode 161
is a part that is laminated through a 5000 Å thick silicon oxide interlayer insulating film, and becomes part of the cross capacitance between the data line and scan line (hereinafter referred to as CCr), and at this time CCr is approximately 16 fF. Become. Further, the layered portion of the shield electrode 161 and the picture element electrode 18 also forms a capacitance via the picture element insulating film 17, and becomes part of the capacitance between the picture element electrode and the data line (hereinafter referred to as CDP). . For the pixel insulating film, we used polyimide with a thickness of 2 μm formed by coating and heating imidization, which was used because of its ease of adhesion, flatness on the substrate, and low dielectric constant material. This is an example selected with consideration. For example, if the dielectric constant εPI is about 2.5t, the CDP is about 4fF.
【００１３】ＣＣｒはデータラインやスキャンラインの
伝達特性の遅延を誘発するが、例えばＨＤＴＶやＩＢＭ
のＸＧＡなどの高速走査に応用した場合でも、本実施例
の値は問題となる範囲ではない事が判っている。これは
アルミニウムやクロムのシート抵抗と浮遊容量、更に表
示装置自体の大きさなどにも依存する。[0013]CCr induces a delay in the transfer characteristics of data lines and scan lines.
It has been found that even when applied to high-speed scanning such as XGA, the values of this embodiment are not in a problematic range. This depends on the sheet resistance and stray capacitance of aluminum and chromium, as well as the size of the display device itself.
【００１４】ＣＤＰは、絵素の液晶容量（ＣＬＣと呼ぶ
、本実施例では３０から８０ｆＦ程度まで、表示状態に
依存して変化する）と直列に接続されたかたちで、デー
タラインと共通電極との間の電位を分割する。つまり、
ＣＤＰによって液晶に加わる実効電圧が低下する事にな
る。本実施例で低下する実効電圧は、一般的な駆動環境
下では数百ｍＶであり、これをデータ電圧によって補正
した場合でも、他の絵素へのデータ電圧印加状態などに
起因した実効電圧の振れ（データクロストークと呼ぶ）
が残留する。本実施例ではこれが２０ｍＶ程度となり、
表示特性を損うまでには至っていない。[0014] The CDP is connected in series with the liquid crystal capacitance (called CLC, in this embodiment, it varies from about 30 to 80 fF depending on the display state) of the picture element, and connects the data line and the common electrode. Divide the potential between. In other words,
CDP reduces the effective voltage applied to the liquid crystal. The effective voltage that decreases in this example is several hundred mV under a general driving environment, and even when this is corrected by the data voltage, the effective voltage decreases due to the data voltage application state to other picture elements. Runout (called data crosstalk)
remains. In this example, this is about 20mV,
It has not reached the point where the display characteristics are impaired.
【００１５】上述した様に、従来ＣＳＰとして形成され
ていた容量の殆んどをＣＣｒとＣＤＰとに変換した本実
施例では、増加したＣＣｒやＣＤＰによる表示特性の低
下が無視できる範囲に留まっている一方、ＣＳＰは約０
．２ｆＦと従来の２０分の１にまで低減されている。こ
の結果、ＣＳＰとＣｇｓとの並列合成容量は約０．７ｆ
Ｆとなり、前出の絵素電位のレベルシフト自体が約２０
０ｍＶ以下に押えられる。更に、共通電位を調整する事
によって、絵素電位センターと共通電位との差（表示状
態で変化する液晶の容量に依存）を±７０ｍＶ程度と、
表示特性に対して殆んど影響を及ぼさない範囲にまで低
減している。As described above, in this embodiment, in which most of the capacitance conventionally formed as CSP is converted into CCr and CDP, the deterioration in display characteristics due to increased CCr and CDP remains within a negligible range. On the other hand, CSP is about 0
．． It has been reduced to 2fF, one-twentieth of the conventional one. As a result, the parallel combined capacitance of CSP and Cgs is approximately 0.7f.
F, and the level shift of the picture element potential itself is approximately 20
The voltage can be kept below 0mV. Furthermore, by adjusting the common potential, the difference between the pixel potential center and the common potential (depending on the capacitance of the liquid crystal that changes depending on the display state) can be reduced to about ±70 mV.
This has been reduced to a level that has almost no effect on display characteristics.
【００１６】[0016]
【発明の効果】上記実施例に代表される様に、本発明を
アクティブマトリクス型液晶表示装置に適用した結果、
ＣＳＰが減少する。そして図３のタイムチャートに示す
る通り、絵素電位３２のレベルシフト３２１自体が減り
、同時に液晶層の制御状態に依って異なるレベルシフト
量の差も低減される事になる。本実施例ではこの差が１
４０ｍＶ程度に押えられており、絵素電位３２のセンタ
ーに共通電位３３を±７０ｍＶの範囲で設定できた事に
よって、表示特性として、コントラストの低下やフリッ
カーの発生を問題のない程度にまで抑制する事が可能に
なっている。更に、表示状態によって液晶層に加わるＤ
Ｃ電圧が減少するこ事は、液晶層の長時間動作安定性を
向上させる事になる。[Effects of the Invention] As represented by the above embodiments, as a result of applying the present invention to an active matrix type liquid crystal display device,
CSP decreases. As shown in the time chart of FIG. 3, the level shift 321 of the picture element potential 32 itself is reduced, and at the same time, the difference in level shift amounts that vary depending on the control state of the liquid crystal layer is also reduced. In this example, this difference is 1
By being able to set the common potential 33 at the center of the pixel potential 32 within a range of ±70 mV, it is possible to suppress the reduction in contrast and the occurrence of flicker to a level that does not cause problems in terms of display characteristics. Things are now possible. Furthermore, depending on the display state, D applied to the liquid crystal layer
This reduction in C voltage improves the long-term operational stability of the liquid crystal layer.
【００１７】尚、本実施例では、１垂直走査期間毎に絵
素電位を反転させる駆動方式を例示したが、２以上の複
数走査期間毎の反転であっても同様の効果が得られ、デ
ータライン毎あるいはスキャンライン毎の反転を加えた
駆動方式に対しても有効である。In this embodiment, a driving method is exemplified in which the pixel potential is inverted every vertical scanning period, but the same effect can be obtained by inverting every two or more scanning periods, and the data It is also effective for a driving method that adds inversion for each line or scan line.
【図１】本発明を適用したアクティブマトリクス型液晶
表示装置の１絵素を拡大した略平面図。FIG. 1 is an enlarged schematic plan view of one pixel of an active matrix liquid crystal display device to which the present invention is applied.
【図２】図１に示したＣ−Ｄ間の断面図。本発明が適用
された部分である。FIG. 2 is a sectional view taken along line C-D shown in FIG. 1; This is the part to which the present invention is applied.
【図３】本発明を実施する事によって得られた絵素電位
を示したタイムチャート。他の電位も同じスケールで重
ね、２垂直走査期間について表した。FIG. 3 is a time chart showing picture element potentials obtained by implementing the present invention. Other potentials are also superimposed on the same scale and expressed for two vertical scanning periods.
【図４】従来の技術に従って構成されたアクティブマト
リクス型液晶表示装置の１絵素を拡大した略平面図。FIG. 4 is an enlarged schematic plan view of one pixel of an active matrix liquid crystal display device constructed according to a conventional technique.
【図５】図１に示したＡ−Ｂ間の断面図。トランジスタ
部分の積層構造を示す。本発明の適用によって特に大き
く変更される部分はない。FIG. 5 is a sectional view taken along line AB shown in FIG. 1; The stacked structure of the transistor part is shown. There are no particularly large changes made by applying the present invention.
【図６】図１に示したＣ−Ｄ間の断面図。本発明の適用
によって変更される部分の従来例である。FIG. 6 is a sectional view taken along line C-D shown in FIG. 1; This is a conventional example of a portion changed by application of the present invention.
【図７】従来の技術によって構成されたアクティブマト
リクス型液晶表示装置を駆動した場合の絵素電位を示し
たタイムチャート。他の電位も同じスケールで重ね、２
垂直走査期間について表した。FIG. 7 is a time chart showing pixel potentials when driving an active matrix liquid crystal display device constructed by a conventional technique. Superimpose other potentials on the same scale, 2
It is expressed in terms of vertical scanning period.
Claims (3)
トに接続されるスキャンラインと、該トランジスタのソ
ースに接続される絵素電極とが絶縁膜を介した積層部分
を有するアクティブマトリクス型液晶表示装置に於て、
上記積層部分の全部または一部に、データラインに接続
されかつデータラインから分岐して成るシールド電極が
、厚さ方向の両側に絶縁膜を介し、スキャンラインと絵
素電極との間に挟持して積層されている事を特徴とした
アクティブマトリクス型液晶表示装置。1. An active matrix liquid crystal in which a scan line connected to the gate of a transistor provided for each picture element and a picture element electrode connected to the source of the transistor are stacked with an insulating film interposed therebetween. In the display device,
In all or part of the laminated portion, a shield electrode connected to the data line and branched from the data line is sandwiched between the scan line and the pixel electrode with an insulating film interposed on both sides in the thickness direction. An active matrix type liquid crystal display device characterized by a layered structure.
ラインと同時に被着された、データラインと同一の材料
によって形成されているものである事を特徴とした、ア
クティブマトリクス型液晶表示装置。2. An active matrix liquid crystal display device, wherein the shield electrode according to claim 1 is formed of the same material as the data line and is deposited at the same time as the data line. .
結晶シリコン薄膜トランジスタを用いる事を特徴とした
請求項１記載のアクティブマトリクス型液晶表示装置。3. The active matrix liquid crystal display device according to claim 1, wherein a polycrystalline silicon thin film transistor is used as the transistor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7302491A JP3082277B2 (en) | 1991-04-05 | 1991-04-05 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7302491A JP3082277B2 (en) | 1991-04-05 | 1991-04-05 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04307520A true JPH04307520A (en) | 1992-10-29 |
| JP3082277B2 JP3082277B2 (en) | 2000-08-28 |
Family
ID=13506363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7302491A Expired - Lifetime JP3082277B2 (en) | 1991-04-05 | 1991-04-05 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3082277B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660160A1 (en) * | 1993-07-13 | 1995-06-28 | Kabushiki Kaisha Toshiba | Active matrix type display device |
| EP0664473A1 (en) * | 1993-12-24 | 1995-07-26 | Kabushiki Kaisha Toshiba | Active matrix type display device and manufacturing method thereof |
| JPH10502462A (en) * | 1994-06-30 | 1998-03-03 | ハネウエル・インコーポレーテッド | Large aperture AMLCD architecture |
| FR2772499A1 (en) * | 1997-12-15 | 1999-06-18 | Thomson Lcd | IMPROVEMENT ON MATRIX SCREENS |
| US6707067B2 (en) | 1995-06-06 | 2004-03-16 | Lg.Philips Lcd Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
| US6714266B1 (en) | 1999-08-04 | 2004-03-30 | Sharp Kabushiki Kaisha | Transmission type liquid crystal display device |
| US6870188B2 (en) | 1995-06-06 | 2005-03-22 | Lg. Philips Lcd Co., Ltd. | LCD with increased pixel opening sizes |
| KR100529576B1 (en) * | 1998-07-23 | 2006-02-13 | 삼성전자주식회사 | Thin film transistor substrate for liquid crystal display |
| US7440043B2 (en) | 2004-05-06 | 2008-10-21 | Seiko Epson Corporation | Liquid crystal display device and electronic device |
-
1991
- 1991-04-05 JP JP7302491A patent/JP3082277B2/en not_active Expired - Lifetime
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660160A1 (en) * | 1993-07-13 | 1995-06-28 | Kabushiki Kaisha Toshiba | Active matrix type display device |
| EP0660160A4 (en) * | 1993-07-13 | 1996-07-31 | Toshiba Kk | Active matrix type display device. |
| US5708483A (en) * | 1993-07-13 | 1998-01-13 | Kabushiki Kaisha Toshiba | Active matrix type display device |
| EP0664473A1 (en) * | 1993-12-24 | 1995-07-26 | Kabushiki Kaisha Toshiba | Active matrix type display device and manufacturing method thereof |
| JPH10502462A (en) * | 1994-06-30 | 1998-03-03 | ハネウエル・インコーポレーテッド | Large aperture AMLCD architecture |
| US6707067B2 (en) | 1995-06-06 | 2004-03-16 | Lg.Philips Lcd Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
| US8198110B2 (en) | 1995-06-06 | 2012-06-12 | Lg Display Co., Ltd. | Method of making a TFT array with photo-imageable insulating layer over address lines |
| US6870188B2 (en) | 1995-06-06 | 2005-03-22 | Lg. Philips Lcd Co., Ltd. | LCD with increased pixel opening sizes |
| US7135705B2 (en) | 1995-06-06 | 2006-11-14 | Lg.Philips Lcd Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
| US8253890B2 (en) | 1995-06-06 | 2012-08-28 | Lg Display Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
| US7445948B2 (en) | 1995-06-06 | 2008-11-04 | Lg. Display Co., Ltd. | Method of making a TFT array with photo-imageable insulating layer over address lines |
| US7531838B2 (en) | 1995-06-06 | 2009-05-12 | Lg Display Co., Ltd. | LCD with increased pixel opening sizes |
| US7745830B2 (en) | 1995-06-06 | 2010-06-29 | Lg Display Co., Ltd. | LCD with increased pixel opening sizes |
| JP2011124568A (en) * | 1995-06-06 | 2011-06-23 | Lg Display Co Ltd | Liquid crystal display |
| FR2772499A1 (en) * | 1997-12-15 | 1999-06-18 | Thomson Lcd | IMPROVEMENT ON MATRIX SCREENS |
| WO1999031548A1 (en) * | 1997-12-15 | 1999-06-24 | Thomson-Lcd | Improvements to matrix displays |
| KR100529576B1 (en) * | 1998-07-23 | 2006-02-13 | 삼성전자주식회사 | Thin film transistor substrate for liquid crystal display |
| US6714266B1 (en) | 1999-08-04 | 2004-03-30 | Sharp Kabushiki Kaisha | Transmission type liquid crystal display device |
| US7440043B2 (en) | 2004-05-06 | 2008-10-21 | Seiko Epson Corporation | Liquid crystal display device and electronic device |
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|---|---|
| JP3082277B2 (en) | 2000-08-28 |
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