JPH04286418A - Multi-stable circuit - Google Patents
Multi-stable circuitInfo
- Publication number
- JPH04286418A JPH04286418A JP5120791A JP5120791A JPH04286418A JP H04286418 A JPH04286418 A JP H04286418A JP 5120791 A JP5120791 A JP 5120791A JP 5120791 A JP5120791 A JP 5120791A JP H04286418 A JPH04286418 A JP H04286418A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- negative resistance
- resistance elements
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012827 research and development Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 3
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は，所定の電気信号を入力
することにより複数の電圧安定点を得ることが可能な多
安定回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistable circuit capable of obtaining a plurality of stable voltage points by inputting a predetermined electrical signal.
【０００２】0002
【従来の技術】従来複数（例えば２点）の電圧安定点を
得る回路としては双安定化回路がある。2. Description of the Related Art Conventionally, a bistable circuit is known as a circuit for obtaining a plurality of (for example, two) voltage stabilization points.
【０００３】0003
【発明が解決しようとする課題】しかしながら，従来の
双安定化回路に３点，４点と更に電圧安定点を付加する
為には回路が複雑になり，更に動作速度が遅いという問
題があった。本発明は上記従来技術の問題を解決するた
めになされたもので，簡単な回路構成で動作速度の速い
多安定回路を提供することを目的とする。[Problems to be Solved by the Invention] However, adding three or four voltage stabilization points to the conventional bistable circuit made the circuit complicated, and the operation speed was slow. . The present invention was made to solve the problems of the prior art described above, and an object of the present invention is to provide a multistable circuit with a simple circuit configuration and high operating speed.
【０００４】0004
【課題を解決するための手段】上記課題を解決する為に
本発明は，負荷抵抗と，この負荷抵抗の一端に複数個の
負性抵抗素子を直列に接続した回路の一端を接続し，前
記負荷抵抗の他端にバイアス電源を接続し，前記複数個
の負性抵抗素子を直列に接続した回路の他端を接地する
とともに前記負荷抵抗と負性抵抗素子の間に入出端子を
設けたことを特徴とするものである。[Means for Solving the Problems] In order to solve the above problems, the present invention connects a load resistor and one end of a circuit in which a plurality of negative resistance elements are connected in series to one end of the load resistor. A bias power supply is connected to the other end of the load resistor, the other end of the circuit in which the plurality of negative resistance elements are connected in series is grounded, and an input/output terminal is provided between the load resistor and the negative resistance element. It is characterized by:
【０００５】[0005]
【作用】直列に接続された負性抵抗素子はｎ＋１の安定
点を有する。[Operation] The negative resistance elements connected in series have n+1 stable points.
【０００６】[0006]
【実施例】図１は本発明の一実施例を示す回路図である
。図において１は負荷抵抗，２は負性抵抗素子を直列に
ｎ個接続した回路であり，この負性抵抗素子としては，
例えば共鳴トンネルダイオ―ド（以下，ＲＴＤという）
を用いる。負荷抵抗１の一端はバイアス電源Ｖ＋に，他
端は負性抵抗素子を直列にｎ個接続した回路２の一端に
接続され，この負性抵抗素子２の他端は接地されている
。３は直列に接続された負荷抵抗素子２の一端と負荷抵
抗１の接続点に入力抵抗５を介して接続された入力接続
端子，４は出力抵抗６を介して接続された出力接続端子
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a load resistance, and 2 is a circuit in which n negative resistance elements are connected in series.
For example, resonant tunnel diode (hereinafter referred to as RTD)
Use. One end of the load resistor 1 is connected to a bias power supply V+, and the other end is connected to one end of a circuit 2 in which n negative resistance elements are connected in series, and the other end of this negative resistance element 2 is grounded. 3 is an input connection terminal connected via an input resistor 5 to a connection point between one end of the load resistance element 2 and the load resistance 1 connected in series, and 4 is an output connection terminal connected via an output resistor 6. .
【０００７】図６はＲＴＤの概念図を示すもので，バイ
アス電圧と電流密度の関係を示している。ＲＴＤは第７
図に示す様に２つのポテンシャルバリア層と，その層に
挟まれたウェル（量子井戸）からなる構造をしている。
この層構造は一次元井戸型ポテンシャルとなっており，
ウェル層の部分に量子力学的な離散的な準位が発生する
。この両端に電圧を印加していくと陰極側の電子エネル
ギ―とウェル層の準位が一致するときだけ電流が流れ，
図６に示すような負性抵抗の性質を示す。このＲＴＤの
スイッチング速度は極めて高速なものとなる。図１に示
す負性抵抗素子を直列にｎ個接続した回路はこのような
ＲＴＤの特性の揃った（または意識的にすこしずつピ―
ク電流密度を変化させた）ものを直列接続したものであ
る。FIG. 6 shows a conceptual diagram of an RTD, showing the relationship between bias voltage and current density. RTD is the 7th
As shown in the figure, it has a structure consisting of two potential barrier layers and a well (quantum well) sandwiched between the layers. This layer structure is a one-dimensional well type potential.
Quantum mechanical discrete levels are generated in the well layer. When a voltage is applied across these ends, a current flows only when the electron energy on the cathode side matches the level in the well layer.
The properties of negative resistance are shown in FIG. The switching speed of this RTD is extremely high. The circuit shown in Figure 1, in which n negative resistance elements are connected in series, has the same characteristics as the RTD (or intentionally
(with varying current density) connected in series.
【０００８】図２は上記の回路に入力信号Ａを入力した
場合のバイアス電圧（Ｖ＋）と電流信号（Ｉ）の関係を
示すもので，ＲＴＤが１個の場合はＶ１ およびＶ２
の電圧安定点を得ることができ，ＲＴＤが２個の場合は
Ｖ１ ，Ｖ２ ，Ｖ３ の電圧安定点を，ＲＴＤが３個
の場合はＶ１ ，Ｖ２ ，Ｖ３ Ｖ４ の安定点を得る
ことができる。上記の構成によればｎ個のＲＴＤを単に
直列に接続して負荷抵抗に接続するだけの回路でｎ＋１
個の安定点を得ることができ，更にＲＴＤを用いている
ことから動作速度の速いものとなる。FIG. 2 shows the relationship between the bias voltage (V+) and the current signal (I) when input signal A is input to the above circuit, and when there is one RTD, V1 and V2
When there are two RTDs, stable voltage points of V1, V2, and V3 can be obtained, and when there are three RTDs, stable voltage points of V1, V2, V3, and V4 can be obtained. According to the above configuration, a circuit that simply connects n RTDs in series and connects them to a load resistor can provide n+1
It is possible to obtain several stable points, and since an RTD is used, the operation speed is fast.
【０００９】図３は図１に示す多安定回路をデジタイザ
として利用した応用例を示すものである。（ａ）図は入
力波形，（ｂ）図は出力波形を示している。即ち，図２
に示すようにＲＴＤ列の両端電圧は電源電圧が一定レベ
ルに達したときに出力電流が小さくなるので（ａ）図の
ような正弦波入力に対して階段状の出力となる。FIG. 3 shows an application example in which the multistable circuit shown in FIG. 1 is used as a digitizer. The figure (a) shows the input waveform, and the figure (b) shows the output waveform. That is, Figure 2
As shown in (a), when the voltage across the RTD string reaches a certain level, the output current becomes small, resulting in a stepped output with respect to the sine wave input as shown in the diagram (a).
【００１０】図４はこの多安定回路をメモリ回路として
使用した応用例を示すものである。この例においては図
１に示す回路の入力端にコンデンサ７を接続する。この
コンデンサ７の他端に図５（ａ）に示すようなパルス信
号を入力すれば図５（ｂ）に示すような一定レベルの信
号を得ることができる。即ち，ｔ＝０でＶ１ のレベル
にあると仮定すると，ｔ＝１のとき＋１のパルスが入力
され，図５（ｃ）の動作点に示す様に（０） の点から
■の点に安定点が移動してＶ２ のレベルになる。ｔ＝
２のときも同様に＋１のパルスで■のＶ３ レベルに移
動する。FIG. 4 shows an application example in which this multistable circuit is used as a memory circuit. In this example, a capacitor 7 is connected to the input terminal of the circuit shown in FIG. If a pulse signal as shown in FIG. 5(a) is input to the other end of this capacitor 7, a signal of a constant level as shown in FIG. 5(b) can be obtained. That is, assuming that it is at the level of V1 at t = 0, a +1 pulse is input at t = 1, and it stabilizes from point (0) to point ■, as shown in the operating point of Figure 5 (c). The point moves to the level of V2. t=
Similarly, in the case of 2, the +1 pulse moves to the V3 level of (■).
【００１１】図６はこの様な動作を一般化して示すもの
で＋１のパルスで矢印イの所から矢印ロの経路を辿り，
出力は例えばＶｎ からＶｎ＋１ に移動して安定する
。また，−１のパルスのパルスの場合は矢印ハの所から
矢印ニの経路を辿り，一つ下のレベルに移動して安定す
る。
即ち，この回路はある安定点ｔ＝０（Ｖ（ｎ） ）から
，Ｋを＋１とか−２というスイッチの命令とすると，ｔ
＝ｑでFIG. 6 shows a generalized version of this kind of operation, in which a pulse of +1 traces the path of arrow B from the point of arrow A.
For example, the output moves from Vn to Vn+1 and stabilizes. In addition, in the case of a pulse of -1, the pulse follows the path from arrow C to arrow D, moves to the next lower level, and becomes stable. In other words, this circuit starts from a certain stable point t = 0 (V(n)), and if K is a switch command of +1 or -2, then t
= q
【数１】
となる電位になるように働く回路である（但しＶ １よ
り大きな電圧とＶ（ＲＴＤの段数＋１）より上にいくＫ
は無効である）[Equation 1] It is a circuit that operates to reach a potential of
is invalid)
【００１２】0012
【発明の効果】以上実施例とともに具体的に説明した様
に，本発明の多安定回路によれば簡単な回路構成で動作
速度の速い多安定回路を実現することができる。As described above in detail with the embodiments, according to the multistable circuit of the present invention, it is possible to realize a multistable circuit with a simple circuit configuration and a high operating speed.
【００１３】[0013]
【図１】本発明の多安定回路の一実施例を示す回路図で
ある。FIG. 1 is a circuit diagram showing an embodiment of a multistable circuit of the present invention.
【図２】図１の回路におけるバイアス電圧と出力電流の
関係を示す図である。FIG. 2 is a diagram showing the relationship between bias voltage and output current in the circuit of FIG. 1;
【図３】図１の回路への入力波形と出力波形の一例を示
す図である。FIG. 3 is a diagram showing an example of input waveforms and output waveforms to the circuit of FIG. 1;
【図４】本発明の回路を用いた他の応用例を示す回路図
である。FIG. 4 is a circuit diagram showing another application example using the circuit of the present invention.
【図５】図４の回路への入力波形と出力波形の一例を示
す図である。FIG. 5 is a diagram showing an example of input waveforms and output waveforms to the circuit of FIG. 4;
【図６】図４の回路の動作を一般化して示す動作説明図
である。6 is an operation explanatory diagram showing a generalized operation of the circuit in FIG. 4; FIG.
【図７】ＲＴＤの概念を示す図である。FIG. 7 is a diagram showing the concept of RTD.
【図８】ＲＴＤのポテンシャル図である。FIG. 8 is a potential diagram of an RTD.
１ 負荷抵抗 ２ 負性抵抗素子。 ３ 入力端子 ４ 出力端子 ５ 入力抵抗 ６ 出力抵抗 ７ コンデンサ 1 Load resistance 2 Negative resistance element. 3 Input terminal 4 Output terminal 5 Input resistance 6 Output resistance 7 Capacitor
Claims (1)
数個の負性抵抗素子を直列に接続した回路の一端を接続
し，前記負荷抵抗の他端にバイアス電源を接続し，前記
複数個の負性抵抗素子を直列に接続した回路の他端を接
地するとともに前記負荷抵抗と負性抵抗素子の間に入出
端子を設けたことを特徴とする多安定回路。Claim 1: A load resistor; one end of a circuit in which a plurality of negative resistance elements are connected in series is connected to one end of the load resistor; a bias power supply is connected to the other end of the load resistor; 1. A multistable circuit, characterized in that the other end of the circuit is grounded, and an input/output terminal is provided between the load resistor and the negative resistance element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5120791A JPH04286418A (en) | 1991-03-15 | 1991-03-15 | Multi-stable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5120791A JPH04286418A (en) | 1991-03-15 | 1991-03-15 | Multi-stable circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04286418A true JPH04286418A (en) | 1992-10-12 |
Family
ID=12880463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5120791A Pending JPH04286418A (en) | 1991-03-15 | 1991-03-15 | Multi-stable circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04286418A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773996A (en) * | 1995-05-22 | 1998-06-30 | Nippon Telegraph And Telephone Corporation | Multiple-valued logic circuit |
-
1991
- 1991-03-15 JP JP5120791A patent/JPH04286418A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773996A (en) * | 1995-05-22 | 1998-06-30 | Nippon Telegraph And Telephone Corporation | Multiple-valued logic circuit |
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