JPH04284629A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH04284629A JPH04284629A JP7447691A JP7447691A JPH04284629A JP H04284629 A JPH04284629 A JP H04284629A JP 7447691 A JP7447691 A JP 7447691A JP 7447691 A JP7447691 A JP 7447691A JP H04284629 A JPH04284629 A JP H04284629A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- protective film
- semiconductor substrate
- peripheral edge
- peripheral end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 36
- 230000002093 peripheral effect Effects 0.000 claims abstract description 23
- 238000005498 polishing Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 9
- 239000000428 dust Substances 0.000 abstract description 6
- 239000007788 liquid Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 24
- 238000004140 cleaning Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 239000006061 abrasive grain Substances 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 150000004703 alkoxides Chemical group 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体デバイス作成
に利用する半導体基板の製造方法に係り、研磨加工前に
半導体基板材料の周辺部に保護膜を形成し、研磨加工時
における基板周辺端部の損傷を防止して周辺端部からの
発塵を防止し、基板上のパーティクルを低減した半導体
基板の製造方法に関する。[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor substrate used in the production of semiconductor devices, in which a protective film is formed on the periphery of the semiconductor substrate material before polishing, and The present invention relates to a method for manufacturing a semiconductor substrate that prevents damage to the semiconductor substrate, prevents dust from being generated from the peripheral edge, and reduces particles on the substrate.
【０００２】0002
【従来の技術】今日の半導体デバイスの高集積度化の勢
いは著しく、４メガバイト、１６メガバイトＤＲＡＭ素
子の量産が始められている。高集積度化にともない、パ
ターニングされる線巾が著しく狭くなるため、これに使
用される半導体基板（以下ウエーハという）上のパーテ
ィクルも、その大きさや個数を大幅に低減することが強
く要請されている。2. Description of the Related Art Today's semiconductor devices are becoming increasingly highly integrated, and mass production of 4 megabyte and 16 megabyte DRAM devices has begun. As the degree of integration increases, the width of patterned lines becomes significantly narrower, so there is a strong demand to significantly reduce the size and number of particles on semiconductor substrates (hereinafter referred to as wafers) used for this purpose. There is.
【０００３】一般に、ウエーハからのパーティクル発生
原因は、表裏面の付着物や周辺端部が主であるとされて
いるが、特に周辺端部からの発塵防止がパーティクルの
低減に不可欠であるとされている。[0003] Generally, the main causes of particle generation from wafers are deposits on the front and back surfaces and the peripheral edges, but it is believed that preventing dust generation from the peripheral edges is particularly essential to reducing particles. has been done.
【０００４】ウエーハは、一般に半導体結晶インゴット
よりスライスされたのち、洗浄して面取加工が行われ、
また両面研磨加工し、洗浄後にエッチング加工され、さ
らに洗浄後に鏡面加工を行い、また洗浄して仕上げられ
る。Wafers are generally sliced from a semiconductor crystal ingot, then cleaned and chamfered.
Also, both sides are polished, etched after cleaning, mirror-finished after cleaning, and finished by cleaning again.
【０００５】面取加工は周辺端部からの発塵を防止する
ために所要形状に加工するもので、微細砥粒を使用した
研削加工や、その後に面取加工面に鏡面研磨を施したり
して面取加工面の表面粗さや加工歪を小さくしておくこ
とが一般に採用されていた。[0005] Chamfering is processing into a desired shape in order to prevent dust from being generated from the peripheral edge, and involves grinding using fine abrasive grains or mirror polishing the chamfered surface afterwards. It was generally adopted to minimize the surface roughness and machining distortion of the chamfered surface.
【０００６】[0006]
【発明が解決しようとする課題】上述の如く、従来技術
では、面取加工の後にラッピング加工を行なうのが一般
的であるが、この工程では図４に示す如く、ラッピング
加工中にウェーハ１が収納されるキャリア３の内周面や
砥粒と接触したりして、周辺端部の面取加工面２に微小
な疵や欠けが発生したり、あるいは削られて面取加工面
２に形状変化が生じたりする問題があった。[Problems to be Solved by the Invention] As mentioned above, in the conventional technology, lapping is generally performed after chamfering, but in this process, as shown in FIG. Due to contact with the inner circumferential surface of the carrier 3 to be stored or abrasive grains, minute flaws or chips may occur on the chamfered surface 2 at the peripheral edge, or the chamfered surface 2 may be scraped to form a shape. There was a problem with changes occurring.
【０００７】このまま後の加工フローにて製造されたウ
ェーハは、各種のデバイス作成プロセスに投入された際
に、ウェーハの周辺端部よりパーティクルが生じて、各
種の成膜やパターニング配線を損傷させてデバイス歩留
を悪化させる要因となる。[0007] When wafers manufactured in the subsequent processing flow are put into various device fabrication processes, particles are generated from the peripheral edges of the wafers, damaging various film formations and patterning wiring. This becomes a factor that deteriorates device yield.
【０００８】この発明は、ウェーハのかかる現状に鑑み
、研磨加工時における基板周辺端部の損傷を防止して周
辺端部からの発塵を防止し、ウェーハ上のパーティクル
を低減でき、デバイス歩留の向上が可能な半導体基板の
製造方法の提供を目的としている。In view of the current state of wafers, the present invention prevents damage to the peripheral edge of the substrate during polishing, prevents dust generation from the peripheral edge, reduces particles on the wafer, and improves device yield. The purpose of the present invention is to provide a method for manufacturing a semiconductor substrate that can improve the performance.
【０００９】[0009]
【課題を解決するための手段】この発明は、半導体結晶
より薄板を切り出して、研磨加工を行ない、半導体デバ
イス用の半導体基板を製造する方法において、研磨加工
前に少なくとも半導体基板材料の周辺端部に保護膜を形
成することを特徴とする半導体基板の製造方法である。
すなわち、この発明は、面取加工後のウェーハの周辺に
薄い保護膜を形成し、これにより研磨加工によるウェー
ハ周辺への疵や欠け及び形状変化を防止することを特徴
とする。また、エッチング加工及並びにその洗浄後にウ
ェーハの周辺に薄い保護膜を形成し、鏡面研磨加工によ
るウェーハ周辺への疵や欠け及び形状変化を防止するこ
とを特徴とする。[Means for Solving the Problems] The present invention provides a method for manufacturing a semiconductor substrate for a semiconductor device by cutting out a thin plate from a semiconductor crystal and polishing it, in which at least the peripheral edge of the semiconductor substrate material is cut out before the polishing process. This is a method for manufacturing a semiconductor substrate, characterized in that a protective film is formed on the substrate. That is, the present invention is characterized in that a thin protective film is formed around the wafer after chamfering, thereby preventing scratches, chips, and shape changes around the wafer due to polishing. Another feature is that a thin protective film is formed around the wafer after etching and cleaning to prevent scratches, chips, and shape changes around the wafer due to mirror polishing.
【００１０】0010
【作用】この発明は、図１に示す如く、面取加工後のウ
ェーハ１の周辺端部、特に面取面２に保護膜４を形成し
ているため、ラッピング加工中にウェーハ１がキャリア
３に接触しても、保護膜４が研磨加工で損傷し、すなわ
ち保護膜４が緩衝層となってウェーハ１自体に疵や欠け
を生じさせない。また、面取面２の傾斜部分にも保護膜
が形成されているため、ラッピング加工中に砥粒が作用
してもウェーハ自体が加工されることはない。従ってこ
の発明の製造方法によれば、ラッピング加工を行なって
もウェーハの面取加工面に疵や欠けを生じさせることが
なく、また面取面の形状変化も生じない。さらに、この
発明は、用途により面取面を形成しないウエーハの周辺
端部に、かかる保護膜を形成しても両面あるいは片面の
研磨加工時の保護膜の作用効果は全く同等である。[Operation] As shown in FIG. 1, this invention forms a protective film 4 on the peripheral edge of the wafer 1 after chamfering, especially on the chamfered surface 2. Even if the wafer 1 comes into contact with the wafer 1, the protective film 4 will be damaged by the polishing process, that is, the protective film 4 will act as a buffer layer and will not cause scratches or chips on the wafer 1 itself. Furthermore, since the protective film is also formed on the inclined portion of the chamfered surface 2, the wafer itself will not be processed even if abrasive grains act on it during the lapping process. Therefore, according to the manufacturing method of the present invention, even when lapping is performed, no flaws or chips occur on the chamfered surface of the wafer, and no change in the shape of the chamfered surface occurs. Further, according to the present invention, even if such a protective film is formed on the peripheral edge of a wafer where no chamfered surface is formed depending on the application, the effect of the protective film during polishing of both sides or one side is completely the same.
【００１１】この発明において、ウェーハの周辺端部に
設ける保護膜には、ワックス、アルコキシド基を有する
接着剤、レジスト等の樹脂系接着剤などを使用できるが
、ラッピング加工後のウェーハ洗浄方法に合わせて、洗
浄時に保護膜を除去できるようその保護膜材質を適宜選
択してもよい。逆に使用した保護膜に応じてこれを除去
できるウェーハ洗浄方法を選定してもよい。[0011] In the present invention, wax, an adhesive having an alkoxide group, a resin adhesive such as a resist, etc. can be used for the protective film provided on the peripheral edge of the wafer. The material of the protective film may be appropriately selected so that the protective film can be removed during cleaning. Conversely, a wafer cleaning method that can remove the protective film may be selected depending on the protective film used.
【００１２】この保護膜形成方法として、実施例の如く
、保護膜形成液体をノズルで所要形状の面取面に塗布し
て自然乾燥させる方法のほか、垂直に回転させながら周
辺端部だけ保護膜液に浸漬し直ちに加熱乾燥させてもよ
く、また、ウェーハ全体を樹脂やワックス中に浸漬し乾
燥させることにより全体及び周辺端部に保護膜を形成す
るのもよい。As a method for forming this protective film, in addition to applying the protective film forming liquid with a nozzle to a chamfered surface of a desired shape and drying it naturally, as in the embodiment, there is also a method of applying a protective film forming liquid to a chamfered surface of a desired shape and drying it naturally. Alternatively, the entire wafer may be immersed in a resin or wax and dried to form a protective film on the entire wafer and its peripheral edges.
【００１３】保護膜厚さは、面取加工面の表面粗さの大
きさにより、ラッピング加工中の周辺端部の疵や欠け防
止効果、洗浄工程、洗浄液並びに保護膜の除去効率など
を考慮して適宜選択することが望ましい。The thickness of the protective film depends on the surface roughness of the chamfered surface, taking into consideration the effect of preventing scratches and chips on the peripheral edge during lapping, the cleaning process, the cleaning solution, and the removal efficiency of the protective film. It is desirable to select it appropriately.
【００１４】[0014]
【実施例】半導体結晶インゴットよりスライスしたのち
、洗浄して面取加工を行い、次いで図２に示す如く、ウ
ェーハ１を真空チャック板５に吸引固定し、ウェーハ周
辺端部の面取面２のみに、所要形状の面取面に合わせた
凹状ノズル６で保護膜形成液体を塗布して、自然乾燥あ
るいは８０℃程度のベークにて乾燥させて種々厚みの保
護膜４を形成した。[Example] After slicing a semiconductor crystal ingot, it is cleaned and chamfered, and then, as shown in FIG. Then, a protective film-forming liquid was applied using a concave nozzle 6 that matched the chamfered surface of the desired shape, and dried naturally or by baking at about 80° C. to form protective films 4 of various thicknesses.
【００１５】その後両面研磨加工し、研磨加工後の洗浄
時に保護膜を除去し、さらにエッチング加工して洗浄し
たのち、疵や欠けの発生率を調べた。測定結果を図３に
示す。[0015] After that, both sides were polished, the protective film was removed during cleaning after polishing, and after etching and cleaning, the incidence of flaws and chips was examined. The measurement results are shown in Figure 3.
【００１６】面取加工を＃５００番のダイヤモンド砥粒
を利用して加工されたウェーハでは、表面粗さＲｍａｘ
〜５μｍ程度であり、保護膜厚さが１０μｍ以上で疵や
欠けの低減効果が著しい。また、面取面の表面粗さがＲ
ｍａｙ〜２μｍ程度の場合には、保護膜厚５μｍでも該
効果が著しい。[0016] In the case of a wafer processed by chamfering using #500 diamond abrasive grains, the surface roughness Rmax
The thickness of the protective film is approximately 5 μm or more, and the effect of reducing scratches and chips is remarkable when the thickness of the protective film is 10 μm or more. Also, the surface roughness of the chamfered surface is R
When the thickness of the protective film is about 2 μm, the effect is remarkable even when the protective film thickness is 5 μm.
【００１７】[0017]
【発明の効果】この発明による半導体基板の製造方法、
研磨加工前に半導体基板の周辺端部に保護膜を形成する
ことにより、研磨加工時における基板周辺端部の損傷を
防止して周辺端部からの発塵を防止し、基板上のパーテ
ィクルを著しく低減できる。[Effects of the Invention] A method for manufacturing a semiconductor substrate according to the present invention,
By forming a protective film on the peripheral edge of a semiconductor substrate before polishing, it prevents damage to the peripheral edge of the substrate during polishing, prevents dust generation from the peripheral edge, and significantly reduces particles on the substrate. Can be reduced.
【図１】この発明による半導体基板の製造方法における
保護膜の機能を示す半導体基板の周辺端部の縦断説明図
である。FIG. 1 is a longitudinal cross-sectional view of a peripheral edge of a semiconductor substrate showing the function of a protective film in a method of manufacturing a semiconductor substrate according to the present invention.
【図２】従来の半導体基板の製造方法における半導体基
板の周辺端部の縦断説明図である。FIG. 2 is an explanatory longitudinal cross-sectional view of a peripheral edge of a semiconductor substrate in a conventional semiconductor substrate manufacturing method.
【図３】この発明による保護膜の形成方法を示す説明図
である。FIG. 3 is an explanatory diagram showing a method for forming a protective film according to the present invention.
【図４】保護膜厚さとカケ・チップ発生率との関係を示
すグラフである。FIG. 4 is a graph showing the relationship between the thickness of the protective film and the occurrence rate of chips and chips.
１ ウェーハ ２ 面取面 ３ キャリア ４ 保護膜 ５ 真空チャック板 ６ 凹状ノズル 1 Wafer 2 Chamfered surface 3. Career 4 Protective film 5 Vacuum chuck plate 6 Concave nozzle
Claims (1)
磨加工を行ない、半導体デバイス用の半導体基板を製造
する方法において、研磨加工前に少なくとも半導体基板
材料の周辺端部に保護膜を形成することを特徴とする半
導体基板の製造方法。1. A method of manufacturing a semiconductor substrate for a semiconductor device by cutting out a thin plate from a semiconductor crystal and polishing it, including forming a protective film on at least the peripheral edge of the semiconductor substrate material before the polishing process. Features: A method for manufacturing a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7447691A JPH04284629A (en) | 1991-03-13 | 1991-03-13 | Manufacture of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7447691A JPH04284629A (en) | 1991-03-13 | 1991-03-13 | Manufacture of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04284629A true JPH04284629A (en) | 1992-10-09 |
Family
ID=13548360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7447691A Pending JPH04284629A (en) | 1991-03-13 | 1991-03-13 | Manufacture of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04284629A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100596A (en) * | 2000-09-25 | 2002-04-05 | Mitsubishi Materials Silicon Corp | Edge protecting device for silicon wafer |
| JP2007043101A (en) * | 2005-06-30 | 2007-02-15 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2009509349A (en) * | 2005-09-22 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Microelectronic substrate with removable edge extension elements |
| JP2020155757A (en) * | 2019-03-18 | 2020-09-24 | 芝浦メカトロニクス株式会社 | Substrate processing apparatus and substrate processing method |
| JP2020155496A (en) * | 2019-03-18 | 2020-09-24 | 芝浦メカトロニクス株式会社 | Substrate processing apparatus and substrate processing method |
-
1991
- 1991-03-13 JP JP7447691A patent/JPH04284629A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100596A (en) * | 2000-09-25 | 2002-04-05 | Mitsubishi Materials Silicon Corp | Edge protecting device for silicon wafer |
| JP2007043101A (en) * | 2005-06-30 | 2007-02-15 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2009509349A (en) * | 2005-09-22 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Microelectronic substrate with removable edge extension elements |
| US8202460B2 (en) | 2005-09-22 | 2012-06-19 | International Business Machines Corporation | Microelectronic substrate having removable edge extension element |
| JP2020155757A (en) * | 2019-03-18 | 2020-09-24 | 芝浦メカトロニクス株式会社 | Substrate processing apparatus and substrate processing method |
| JP2020155496A (en) * | 2019-03-18 | 2020-09-24 | 芝浦メカトロニクス株式会社 | Substrate processing apparatus and substrate processing method |
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