JPH04282839A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JPH04282839A JPH04282839A JP4508391A JP4508391A JPH04282839A JP H04282839 A JPH04282839 A JP H04282839A JP 4508391 A JP4508391 A JP 4508391A JP 4508391 A JP4508391 A JP 4508391A JP H04282839 A JPH04282839 A JP H04282839A
- Authority
- JP
- Japan
- Prior art keywords
- film
- active layer
- insulating film
- tft
- upper insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 43
- 239000010408 film Substances 0.000 claims abstract description 187
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000001681 protective effect Effects 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 70
- 239000011241 protective layer Substances 0.000 abstract 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 38
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 238000005530 etching Methods 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、不要な活性層，コンタ
クト層により生じる素子特性の低下を防止した薄膜トラ
ンジスタ及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor that prevents deterioration of device characteristics caused by unnecessary active layers and contact layers, and a method for manufacturing the same.
【０００２】0002
【従来の技術】エレクトロルミネッセンス，発光ダイオ
−ド，プラズマ，蛍光表示，液晶等の表示デバイスは、
表示部の薄型化が可能であり計測機器，事務機器やコン
ピュ−タ等の端末表示装置あるいは特殊な表示装置への
用途として要求が高まっている。これらの中で薄膜トラ
ンジスタをスイッチング素子マトリックスアレイに用い
た液晶表示装置は、高画質，高精細のフラットパネルデ
ィスプレイとして開発が進められ、対角１０”程度の６
４０×４８０画素のカラ−ＯＡ用ディスプレイが実現さ
れている。[Prior Art] Display devices such as electroluminescence, light emitting diode, plasma, fluorescent display, liquid crystal, etc.
Since it is possible to make the display section thinner, demand is increasing for use in terminal display devices such as measuring instruments, office equipment, and computers, or special display devices. Among these, liquid crystal display devices that use thin film transistors in switching element matrix arrays are being developed as high-picture-quality, high-definition flat panel displays, with a diagonal of about 10" and 6"
A color OA display with 40 x 480 pixels has been realized.
【０００３】図２２〜図２６には従来のアクティブ型マ
トリクスアレイ基板における薄膜トランジスタの製造工
程断面図，図２７〜図３１には同薄膜トランジスタの製
造工程平面図，図３２〜図３３には図２７〜図３１のＡ
−Ａ´それぞれが示されている。最初、図２２，図２７
，図３２に示す如く、ガラス板のような透光性絶縁基板
１上に所定パタ−ンのゲ−ト線３を形成する。22 to 26 are cross-sectional views of the manufacturing process of a thin film transistor in a conventional active type matrix array substrate, FIGS. 27 to 31 are plan views of the manufacturing process of the same thin film transistor, and FIGS. A in Figure 31
-A' are shown respectively. First, Figure 22, Figure 27
, as shown in FIG. 32, a predetermined pattern of gate lines 3 is formed on a transparent insulating substrate 1 such as a glass plate.
【０００４】次に図２３，図２８，図３３に示すように
、ゲ−ト線３が形成された透光性絶縁基板１上にゲ−ト
絶縁膜５，アモルファスシリコン膜７，上部絶縁膜をＣ
ＶＤ法を用いて順次成膜した後、レジストパタ−ン９を
形成し、これをマスクに上部絶縁膜をエッチングして保
護膜１１を形成する。Next, as shown in FIGS. 23, 28, and 33, a gate insulating film 5, an amorphous silicon film 7, and an upper insulating film are formed on the transparent insulating substrate 1 on which the gate line 3 is formed. C
After sequentially forming films using the VD method, a resist pattern 9 is formed, and the upper insulating film is etched using this as a mask to form a protective film 11.
【０００５】次に図２４，図２９，図３４に示すように
、フォトレジストパタ−ン９を除去した後、全面にｎ＋
アモルファスシリコン膜１５を堆積した後、アモルフ
ァスシリコン膜７，ｎ＋ アモルファスシリコン膜１５
を同時にパタ−ニングして活性層１３，コンタクト層１
９を形成する。Next, as shown in FIGS. 24, 29, and 34, after removing the photoresist pattern 9, an n +
After depositing the amorphous silicon film 15, the amorphous silicon film 7, n+ amorphous silicon film 15 is deposited.
The active layer 13 and the contact layer 1 are patterned simultaneously.
form 9.
【０００６】次に図２５，図３０，図３５に示すように
、ゲ−ト絶縁膜５上に導電膜を堆積し、これをパタ−ニ
ングして画素電極１７とする。このときコンタクトホ−
ルも形成しておく。Next, as shown in FIGS. 25, 30 and 35, a conductive film is deposited on the gate insulating film 5 and patterned to form the pixel electrode 17. At this time, the contact hole
Also form the file.
【０００７】次に図２６，図３１，図３６に示すように
、スパッタリング法等を用いて全面に電極材料を堆積し
、これをパタ−ニングしてソ−ス・ドレイン２１，信号
線２３を形成する。最後にゲ−ト線上の不要なアモルフ
ァスシリコン膜１５をエッチング除去して薄膜トランジ
スタが完成する。Next, as shown in FIGS. 26, 31, and 36, electrode material is deposited on the entire surface using a sputtering method or the like, and this is patterned to form the source/drain 21 and signal line 23. Form. Finally, the unnecessary amorphous silicon film 15 on the gate line is removed by etching to complete the thin film transistor.
【０００８】このようなＴＦＴの製造方法では、マスク
を用いて順次レジストを形成することになるが、精度良
く全てのマスク合わせができないのでパタ−ン同士の位
置関係のずれが生じる。このため、マスク合わせのマ−
ジンをとってパタ−ンずれにより生じる不都合を未然に
防止している。[0008] In such a TFT manufacturing method, resists are sequentially formed using masks, but since it is not possible to align all the masks with high precision, a shift in the positional relationship between the patterns occurs. For this reason, the mask alignment mark
This prevents inconveniences caused by pattern misalignment.
【０００９】ところで、ＴＦＴを用いて液晶表示装置用
のアクティブマトリクス型基板を製造するには、シリコ
ン基板によるＩＣとは異なり、大面積の基板を用いる必
要がある。しかも、生産性を向上するために一枚の基板
に複数のディスプレイを作るとなると、更に大面積の基
板が必要となる。しかしながら、露光装置による４００
ｍｍ角程度の基板のマスク合わせ精度は良くて２μｍ程
度であり、ＩＣの露光装置のそれより悪い。しかも、基
板はＣＶＤ法等による膜形成、即ち、熱工程の過程で変
形（塑性変形）を起こすのでマスク合わせ精度は更に悪
くなる。By the way, in order to manufacture an active matrix type substrate for a liquid crystal display device using TFT, it is necessary to use a large-area substrate, unlike an IC using a silicon substrate. Moreover, if a plurality of displays are to be made on a single substrate in order to improve productivity, a substrate with an even larger area is required. However, 400
The mask alignment accuracy for a substrate of about mm square is about 2 μm at best, which is worse than that of an IC exposure device. Moreover, since the substrate undergoes deformation (plastic deformation) during film formation by CVD or the like, that is, during a thermal process, the mask alignment accuracy becomes even worse.
【００１０】その結果、保護膜１１，活性層１３のチャ
ネル幅方向，チャネル長方向のマ−ジンを大きくとらな
いとパタ−ンずれにより所望の形状のＴＦＴが製造され
ず、設計通りの特性が得られなくなる。As a result, unless the protective film 11 and the active layer 13 have large margins in the channel width direction and the channel length direction, a TFT with the desired shape cannot be manufactured due to pattern misalignment, and the characteristics as designed may not be achieved. You won't be able to get it.
【００１１】しかしながら、マ−ジンを大きくとると、
図３１に示すように保護膜１１，活性層１３，コンタク
ト層１９のソ−ス・ドレイン２１からのはみだし部分１
１ａ，１３ａ、１９ａつまり、不要な部分が大きくなり
、これにより寄生素子が形成されて電極間容量などのＴ
ＦＴ特性が低下し、不良なＴＦＴが製造されるという問
題があった。However, if a large margin is taken,
As shown in FIG. 31, portions 1 of the protective film 11, active layer 13, and contact layer 19 protrude from the source/drain 21.
1a, 13a, 19a In other words, unnecessary portions become large, which forms parasitic elements and reduces T such as interelectrode capacitance.
There was a problem that FT characteristics deteriorated and defective TFTs were manufactured.
【００１２】0012
【発明が解決しようとする課題】上述の如く薄膜トラン
ジスタを用いて大画面のディスプレイを製造するには、
マスク合わせのマ−ジンを大きくとる必要があるが、そ
の際に生じる絶縁膜，半導体膜等のはみだし部分で寄生
素子が形成され、ＴＦＴが不良になるという問題があっ
た。[Problems to be Solved by the Invention] In order to manufacture a large screen display using thin film transistors as described above,
Although it is necessary to have a large margin for mask alignment, there is a problem in that parasitic elements are formed in protruding parts of the insulating film, semiconductor film, etc., resulting in defective TFTs.
【００１３】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、不要な活性層，コンタ
クト層に起因する素子特性の劣化を防止し、大画面の表
示デバイスにも用いることができるＴＦＴ及びその製造
方法を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and its purpose is to prevent the deterioration of device characteristics caused by unnecessary active layers and contact layers, and to make it suitable for large screen display devices. It is an object of the present invention to provide a TFT that can be used and a method for manufacturing the same.
【００１４】[0014]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の薄膜トランジスタは、基板上に所定パタ
−ンをもって形成された活性層と、この活性層にオ−ミ
ックコンタクト層を介してコンタクトすると共に保護膜
を介して対向して配設されたソ−ス及びドレイン電極と
、前記活性層の下部にゲ−ト絶縁膜を介して配設された
ゲ−ト電極とを有する薄膜トランジスタにおいて、チャ
ネル幅方向の寸法が全て同じである活性層，コンタクト
層及び保護膜を備えたことを特徴とする。[Means for Solving the Problems] In order to achieve the above object, the thin film transistor of the present invention includes an active layer formed with a predetermined pattern on a substrate, and an ohmic contact layer interposed between the active layer and the active layer. A thin film transistor having a source electrode and a drain electrode that are in contact with each other and are arranged opposite to each other with a protective film interposed therebetween, and a gate electrode that is arranged below the active layer with a gate insulating film interposed therebetween. The device is characterized in that the active layer, the contact layer, and the protective film all have the same dimensions in the channel width direction.
【００１５】また、本発明の薄膜トランジスタの製造方
法は、基板上にゲ−ト電極を形成する工程と、前記基板
上にゲ−ト絶縁膜，活性層になる第１の半導体膜，保護
膜になる上部絶縁膜を順次堆積する工程と、前記上部絶
縁膜上に第１のレジストパタ−ンを形成し、これをマス
クにして上部絶縁膜をパタ−ニングする工程と、前記第
１の半導体膜上に第２の半導体膜を形成する工程と、前
記第２の半導体膜上に第２のレジストパタ−ンを形成し
、これをマスクにして前記第１，第２の半導体膜及び上
部絶縁膜をパタ−ニングして活性層，コンタクト層及び
保護膜を形成する工程と、前記活性層の相対向する端面
に前記コンタクト層を介してコンタクトするソ−ス及び
ドレインを形成する工程とを備えたことを特徴とするな
お、上部絶縁膜上のレジストパタ−ンは、裏面露光によ
り形成されることが望ましい。また、ゲ−ト絶縁膜には
シリコン酸化膜とシリコン窒化膜との積層膜を用い、上
部絶縁膜にはシリコン窒化膜を用いることが望ましい。The method for manufacturing a thin film transistor of the present invention also includes a step of forming a gate electrode on a substrate, a gate insulating film on the substrate, a first semiconductor film to be an active layer, and a protective film. a step of sequentially depositing an upper insulating film, forming a first resist pattern on the upper insulating film and patterning the upper insulating film using this as a mask; a second resist pattern is formed on the second semiconductor film, and using this as a mask, the first and second semiconductor films and the upper insulating film are patterned. - forming an active layer, a contact layer, and a protective film, and forming a source and a drain in contact with opposing end surfaces of the active layer via the contact layer. Note that the resist pattern on the upper insulating film is preferably formed by backside exposure. Further, it is preferable to use a laminated film of a silicon oxide film and a silicon nitride film for the gate insulating film, and to use a silicon nitride film for the upper insulating film.
【００１６】[0016]
【作用】本発明の薄膜トランジスタでは、活性層，コン
タクト層及び保護膜のチャネル幅方向の寸法が全て同じ
あるため、保護膜からチャネル幅方向にはみだした活性
層，コンタクト層活性層により形成される寄生素子が無
くなる。その結果、オフ電流等のＴＦＴ特性が改善され
るので高信頼，高性能の薄膜トランジスタを得ることが
できる。[Operation] In the thin film transistor of the present invention, since the dimensions of the active layer, contact layer, and protective film in the channel width direction are all the same, parasitics formed by the active layer, contact layer, and active layer protruding from the protective film in the channel width direction The element disappears. As a result, TFT characteristics such as off-state current are improved, making it possible to obtain a highly reliable and high-performance thin film transistor.
【００１７】本発明の薄膜トランジスタの製造方法では
、第２の半導体膜上に形成されたレジストパタ−ンをマ
スクにして第１，第２の半導体膜及び上部絶縁膜を同時
にパタ−ニングしている。このため、第１，第２の半導
体膜と上部絶縁膜とのマスク合せのずれが無くなり、ソ
−ス，ドレインに対する第１，第２の半導体膜，上部絶
縁膜のマスク合せのマ−ジン量は、第１，第２の半導体
膜と上部絶縁膜とを別々にパタ−ニングする場合に比べ
て半分になると共に第１，第２の半導体膜は保護膜から
はみださない。したがって、寄生素子等を防止すること
ができ、素子特性の低下を招くこと無く小型の薄膜トラ
ンジスタを製造することができる。In the method for manufacturing a thin film transistor of the present invention, the first and second semiconductor films and the upper insulating film are simultaneously patterned using a resist pattern formed on the second semiconductor film as a mask. Therefore, there is no misalignment in mask alignment between the first and second semiconductor films and the upper insulating film, and the amount of margin for mask alignment between the first and second semiconductor films and the upper insulating film with respect to the source and drain is eliminated. is reduced to half compared to the case where the first and second semiconductor films and the upper insulating film are patterned separately, and the first and second semiconductor films do not protrude from the protective film. Therefore, parasitic elements and the like can be prevented, and small thin film transistors can be manufactured without deteriorating device characteristics.
【００１８】また、裏面露光により上部絶縁膜上のレジ
ストを露光することでゲ−ト絶縁膜に自己整合的なレジ
ストパタ−ンを形成することができ、これにより活性層
とゲ−ト電極との重なり部分が少なくなりＴＦＴ特性が
向上する。Furthermore, by exposing the resist on the upper insulating film by backside exposure, a self-aligned resist pattern can be formed on the gate insulating film, thereby forming a pattern between the active layer and the gate electrode. The overlapping portion is reduced and TFT characteristics are improved.
【００１９】また、ゲ−ト絶縁膜のエッチングレ−トが
上部絶縁膜のそれより遅くなるようにゲ−ト絶縁膜及び
上部絶縁膜の絶縁膜材料を選ぶことで、上部絶縁膜のエ
ッチング際にゲ−ト絶縁膜がエッチング除去されてゲ−
ト電極が露出するとことを防止することができる。Furthermore, by selecting the insulating film materials for the gate insulating film and the upper insulating film so that the etching rate of the gate insulating film is slower than that of the upper insulating film, the etching rate of the upper insulating film can be reduced. The gate insulating film is etched away and the gate is removed.
This can prevent the top electrode from being exposed.
【００２０】[0020]
【実施例】以下、図面を参照しながら実施例を説明する
。これは本発明を液晶表示装置用のアクティブ型マトリ
クスアレイ基板に適用したものである。Embodiments Hereinafter, embodiments will be described with reference to the drawings. This is an application of the present invention to an active matrix array substrate for a liquid crystal display device.
【００２１】図１〜図５には本発明の一実施例に係る薄
膜トランジスタの製造工程断面図，図６〜図１０には同
薄膜トランジスタの製造工程平面図，図１１〜図１５に
はそれぞれ図６〜図１０のＡ−Ａ´断面図が示されてい
る。なお、図２２〜図３６の従来例と対応する部分には
図２２〜図３６と同一符号を付し、詳細な説明は省略す
る。1 to 5 are cross-sectional views of the manufacturing process of a thin film transistor according to an embodiment of the present invention, FIGS. 6 to 10 are plan views of the manufacturing process of the same thin film transistor, and FIGS. - A cross-sectional view taken along line A-A' in FIG. 10 is shown. Note that parts corresponding to the conventional example in FIGS. 22 to 36 are designated by the same reference numerals as those in FIGS. 22 to 36, and detailed description thereof will be omitted.
【００２２】最初、図１，図６，図１１に示すように、
透光性絶縁基板１上にＭｏＴａ合金等の金属膜をスパッ
タ法を用いて堆積した後、この金属膜上にフォトレジス
トを塗布し、次いでマスク露光を用いてフォトレジスト
パタ−ンを形成し、これをマスクにしてエッチングを行
いゲ−ト線３を形成する。このとき、同時に補助容量の
グランド線２５も形成する。First, as shown in FIGS. 1, 6, and 11,
After depositing a metal film such as MoTa alloy on the transparent insulating substrate 1 using a sputtering method, a photoresist is applied on this metal film, and then a photoresist pattern is formed using mask exposure. Using this as a mask, etching is performed to form gate lines 3. At this time, the ground line 25 of the auxiliary capacitor is also formed at the same time.
【００２３】次に図２，図７，図１２に示すように、ゲ
−ト線３が形成された基板１上に原料ガスとしてＳｉＨ
４ ，Ｎ２ Ｏを用いたプラズマＣＶＤ法により厚さ３
５０ｎｍ程度のシリコン酸化膜を堆積した後、原料ガス
としてＳｉＨ４ ，ＮＨ３ を用いたプラズマＣＶＤ法
により厚さ５０ｎｍ程度のシリコン窒化膜をシリコン酸
化膜上に堆積して積層膜構造のゲ−ト絶縁膜５を形成す
る。次いでゲ−ト絶縁膜５が形成された基板１上にＳｉ
Ｈ４ ，Ｈ２ を原料ガスに用いたプラズマＣＶＤ法に
より厚さ５０ｎｍ程度のアンド−プのアモルファスシリ
コン膜７（第１の半導体膜）を形成する。次いでＣＶＤ
法により厚さ２００ｎｍ程度のシリコン窒化膜からなる
上部絶縁膜をアモルファスシリコン膜７上に形成する。Next, as shown in FIGS. 2, 7, and 12, SiH is applied as a raw material gas onto the substrate 1 on which the gate line 3 is formed.
4, thickness 3 by plasma CVD method using N2O
After depositing a silicon oxide film with a thickness of about 50 nm, a silicon nitride film with a thickness of about 50 nm is deposited on the silicon oxide film by plasma CVD using SiH4 and NH3 as raw material gases to form a gate insulating film with a laminated film structure. form 5. Next, Si is deposited on the substrate 1 on which the gate insulating film 5 is formed.
An undoped amorphous silicon film 7 (first semiconductor film) having a thickness of approximately 50 nm is formed by plasma CVD using H4 and H2 as source gases. Then CVD
An upper insulating film made of a silicon nitride film with a thickness of about 200 nm is formed on the amorphous silicon film 7 by a method.
【００２４】この後、上部絶縁膜上にポジ型のフォトレ
ジストを塗布し、ゲ−ト線３をマスクにして紫外線２７
を用いた裏面露光を行う。そしてフォトレジストを現像
してフォトレジストパタ−ン９（第１のレジストパタ−
ン）を形成する。次いでフォトレジストパタ−ン９をマ
スクにして上部絶縁膜を所定の形状にパタ−ニングして
保護膜１１を形成する。具体的には、上部絶縁膜保護膜
１１はゲ−ト線３より０．５μｍ程度内側にパタ−ニン
グされた。このように保護膜１１はゲ−ト線３に自己整
合的に形成されるのでマスク合わせのずれに起因するＴ
ＦＴ特性の低下を防止することができる。After that, a positive type photoresist is applied on the upper insulating film, and using the gate line 3 as a mask, ultraviolet rays 27 are applied.
Perform backside exposure using Then, the photoresist is developed to form a photoresist pattern 9 (first resist pattern).
form). Next, using the photoresist pattern 9 as a mask, the upper insulating film is patterned into a predetermined shape to form a protective film 11. Specifically, the upper insulating protective film 11 was patterned approximately 0.5 μm inward from the gate line 3. Since the protective film 11 is formed in a self-aligned manner with the gate line 3 in this way, T
Deterioration of FT characteristics can be prevented.
【００２５】次に図３，図８，図１３示すように、保護
膜１１が形成された基板１上にｎ＋アモルファスシリコ
ン膜１５（第２の半導体膜），フォトレジストを順次堆
積した後、マスク合せ、露光，現像を行いフォトレジス
トパタ−ン９ａ（第２のレジストパタ−ン）を形成する
。ＴＦＴのチャネル幅はこのフォトレジストパタ−ン９
ａにより規定される。次いで基板１をエッチング室に搬
入し、ドライエッチング例えばマイクロ波でＣＦ４ と
Ｏ２ の混合ガスを放電，分解し、エッチング室内に導
入してアモルファスシリコン膜７，保護膜１１，ｎ＋
アモルファスシリコン膜１５をエッチングする。このエ
ッチングでゲ−ト線３上以外の所ではアモルファスシリ
コン膜７，ｎ＋ アモルファスシリコン膜１５のみがエ
ッチングされ、ゲ−ト線上ではアモルファスシリコン膜
７，保護膜１１，ｎ＋ アモルファスシリコン膜１５が
エッチングされる。なお、ゲ−ト線３と信号線との交差
部２９にはアモルファスシリコン膜７，ｎ＋ アモルフ
ァスシリコン膜１５を残し、オ−バエッチングによる層
間ショ−トの低減を図った。また、ゲ−ト絶縁膜３はシ
リコン窒化膜とシリコン酸化膜と積層膜からなるのでエ
ッチングの際に保護膜１１（シリコン窒化膜）とともに
エッチングされてゲ−ト線が露出するという問題を防止
することができる。なお、上述したエッチングの他にリ
アクティブ・イオン・エッチングによりアモルファスシ
リコン膜７，保護膜１１，ｎ＋ アモルファスシリコン
膜１５をエッチングしても良い。本発明者等は基板１を
エッチング室に搬入してカソ−ド電極に置いた後、先の
エッチングと同じ混合ガスを１３．５６ＭＨｚの高周波
で放電して発生したイオンを用いることでアモルファス
シリコン膜７，保護膜１１，ｎ＋ アモルファスシリコ
ン膜１５を精度良くエッチングできることを確認した。
具体的には、シリコン窒化膜を含む領域も含まない領域
もサイドエッチング量を１μｍ以下にすることができた
。Next, as shown in FIGS. 3, 8, and 13, an n+ amorphous silicon film 15 (second semiconductor film) and a photoresist are sequentially deposited on the substrate 1 on which the protective film 11 is formed, and then a mask is deposited. A photoresist pattern 9a (second resist pattern) is formed by alignment, exposure, and development. The channel width of the TFT is determined by this photoresist pattern 9.
Defined by a. Next, the substrate 1 is carried into an etching chamber, and a mixed gas of CF4 and O2 is discharged and decomposed by dry etching using microwaves, for example, and introduced into the etching chamber to form an amorphous silicon film 7, a protective film 11, and an n+
The amorphous silicon film 15 is etched. In this etching, only the amorphous silicon film 7 and the n+ amorphous silicon film 15 are etched except on the gate line 3, and the amorphous silicon film 7, the protective film 11, and the n+ amorphous silicon film 15 are etched on the gate line. Ru. Note that the amorphous silicon film 7 and the n+ amorphous silicon film 15 are left at the intersection 29 between the gate line 3 and the signal line to reduce interlayer shorts caused by over-etching. Furthermore, since the gate insulating film 3 is made of a laminated film of a silicon nitride film and a silicon oxide film, it prevents the problem of the gate line being exposed due to being etched together with the protective film 11 (silicon nitride film) during etching. be able to. In addition to the etching described above, the amorphous silicon film 7, the protective film 11, and the n+ amorphous silicon film 15 may be etched by reactive ion etching. The present inventors transported the substrate 1 into an etching chamber and placed it on the cathode electrode, and then used ions generated by discharging the same gas mixture as in the previous etching at a high frequency of 13.56 MHz to form an amorphous silicon film. 7. Protective film 11, n+ It was confirmed that the amorphous silicon film 15 could be etched with high precision. Specifically, it was possible to reduce the side etching amount to 1 μm or less in both regions including the silicon nitride film and regions not including the silicon nitride film.
【００２６】次に図４，図９，図１４に示すように、レ
ジストパタ−ン９ａを除去した後、アモルファスシリコ
ン膜７，ｎ＋ アモルファスシリコン膜１５をパタ−ニ
ングして活性層１３，コンタクト層１９を形成する。次
いでゲ−ト線３を引き出すためのコンタクトホ−ルを設
けた後、ゲ−ト絶縁膜１３上にＩＴＯ（Ｉｎｄｉｕｍ
Ｔｉｎ Ｏｘｉｄｅ）等の導電膜をスパッタ法で堆積し
、この導電膜をパタ−ニングして画素電極１７を形成す
る。Next, as shown in FIGS. 4, 9 and 14, after removing the resist pattern 9a, the amorphous silicon film 7 and the n+ amorphous silicon film 15 are patterned to form the active layer 13 and the contact layer 19. form. Next, after forming a contact hole for drawing out the gate line 3, ITO (Indium
A conductive film such as tin oxide (tin oxide) is deposited by sputtering, and this conductive film is patterned to form the pixel electrode 17.
【００２７】次に図５，図１０，図１５に示すように、
アルミニウムとクロムとの積層膜を堆積した後、レジス
トパタ−ンを形成し、これをマスクにして積層膜をパタ
−ニングしてソ−ス・ドレイン２１，信号線２３を形成
する。そして、ドライエッチングを用いてチャネル上に
残っているｎ＋ アモルファスシリコン膜１５を除去し
てＴＦＴが完成する。なお、必要に応じて配線をシリコ
ン窒化膜等からなるパッシベ−ション膜で覆ってもよい
。Next, as shown in FIGS. 5, 10, and 15,
After depositing a laminated film of aluminum and chromium, a resist pattern is formed, and using this as a mask, the laminated film is patterned to form source/drain 21 and signal line 23. Then, the n+ amorphous silicon film 15 remaining on the channel is removed using dry etching to complete the TFT. Note that, if necessary, the wiring may be covered with a passivation film made of a silicon nitride film or the like.
【００２８】以上のようにして製造されたＴＦＴでは、
保護膜１１のはみだし部分１１ａでチャネル幅方向のも
のはフォトレジストパタ−ン９を形成する際のマスク合
せ精度で決定される。また、アモルファスシリコン膜７
，ｎ＋アモルファスシリコン膜１５及び上部絶縁膜は、
フォトレジストパタ−ン９ａをマスクにして同時にエッ
チングされるため、シリコン膜７，７ａと上部絶縁膜と
のマスク合せが不要になると共に保護膜１１からはみだ
しのない活性層１３，コンタクト層１９が形成される。
したがって、保護膜１１，活性層１３，コンタクト層１
９のソ−ス・ドレイン２１からのはみだし部分１３ａ，
１９ａは従来に比べて小さくなるため寄生素子が形成さ
れ難くなりＴＦＴ特性の低下を防止することができる。
更に、これにより従来の液晶表示装置で発生しやすい不
良、例えば、アモルファスシリコン膜７，ｎ＋ アモル
ファスシリコン膜１５が保護膜１１からはみだした状態
で、パッシベ−ション膜で被覆せずに液晶表示装置を製
造する場合に、ＴＦＴのリ−ク電流が時間と共に増加す
るという不良の発生を抑制できた。また、パッシベ−シ
ョン膜で被覆した場合でも高温長時間駆動時のＴＦＴの
リ−ク電流の増加を制御できた。In the TFT manufactured as described above,
The protruding portion 11a of the protective film 11 in the channel width direction is determined by the accuracy of mask alignment when forming the photoresist pattern 9. In addition, the amorphous silicon film 7
, n+ amorphous silicon film 15 and upper insulating film are as follows:
Since etching is performed simultaneously using the photoresist pattern 9a as a mask, there is no need to align the masks between the silicon films 7, 7a and the upper insulating film, and the active layer 13 and contact layer 19 are formed without protruding from the protective film 11. be done. Therefore, the protective film 11, the active layer 13, the contact layer 1
9 protruding portion 13a from the source/drain 21,
Since 19a is smaller than the conventional one, parasitic elements are less likely to be formed and deterioration of TFT characteristics can be prevented. Furthermore, this makes it possible to avoid defects that tend to occur in conventional liquid crystal display devices, such as when the amorphous silicon film 7, n+ amorphous silicon film 15 protrudes from the protective film 11, and the liquid crystal display device is not covered with a passivation film. During manufacturing, it was possible to suppress the occurrence of defects in which the leakage current of the TFT increases over time. Furthermore, even when the TFT was coated with a passivation film, it was possible to control the increase in leakage current of the TFT during long-term operation at high temperatures.
【００２９】また、保護膜１１，活性層１３，コンタク
ト層１９のはみだし部分１１ａ，１３ａ，１９ａが小さ
くなるのでＴＦＴのレイアウト設計のマ−ジンが大きく
なる。その結果、１つの画素に２つのＴＦＴ、つまり、
欠陥修復用のＴＦＴを設けることできたり、開口率を改
善できる。Furthermore, since the protruding portions 11a, 13a, and 19a of the protective film 11, active layer 13, and contact layer 19 become smaller, the margin for designing the TFT layout becomes larger. As a result, one pixel requires two TFTs, that is,
A TFT for defect repair can be provided, and the aperture ratio can be improved.
【００３０】また、裏面露光を用いてゲ−ト絶縁膜５を
形成したのでそのチャネル長方向の寸法はゲ−ト電極３
のそれと略同じである。その結果、ソ−ス・ドレイン２
１とコンタクトしている活性層１３とゲ−ト線３の重な
りがほとんど無くなるため、ゲ−ト・ソ−ス間容量が低
減する。更に、ゲ−ト・ソ−ス間容量を決める保護膜１
１，活性層１３，コンタクト層１９のはみだし部分１１
ａ，１３ａ，１５ａのチャネル幅方向の寸法の和は各Ｔ
ＦＴで一定で小さいのでゲ−ト・ソ−ス間容量の値及び
そのばらつきが小さくなる。その結果、ゲ−ト・ソ−ス
間容量の結合容量で生じるゲ−ト電圧の変動によりノイ
ズが画素電極１７の電圧に重畳するのを防止できるため
、フリッカ，焼き付き等が減少して画質が向上する。
更に、グランド線２５上のゲ−ト絶縁膜３は活性層１３
，コンタクト層１９に挟まれることがないので補助容量
の電圧による変動は起きない。また、同一のゲ−ト線に
接続された画素の間でゲ−ト線上に残留した活性層１３
を通してリ−ク電流が流れることがなくなり隣接画素間
のクロスト−クが抑制できる。Furthermore, since the gate insulating film 5 was formed using backside exposure, its dimension in the channel length direction was equal to that of the gate electrode 3.
It is almost the same as that of . As a result, source drain 2
Since there is almost no overlap between the active layer 13 and the gate line 3, which are in contact with the active layer 13, the gate-source capacitance is reduced. Furthermore, a protective film 1 that determines the gate-source capacitance is
1. Protruding portion 11 of active layer 13 and contact layer 19
The sum of dimensions in the channel width direction of a, 13a, and 15a is each T
Since it is constant and small in FT, the value of the gate-source capacitance and its variation become small. As a result, it is possible to prevent noise from being superimposed on the voltage of the pixel electrode 17 due to fluctuations in the gate voltage caused by the coupling capacitance between the gate and the source, reducing flicker, burn-in, etc., and improving image quality. improves. Furthermore, the gate insulating film 3 on the ground line 25 is connected to the active layer 13.
, the auxiliary capacitance does not fluctuate due to voltage since it is not sandwiched between the contact layers 19. In addition, the active layer 13 remaining on the gate line between pixels connected to the same gate line
Since no leakage current flows through the pixel, crosstalk between adjacent pixels can be suppressed.
【００３１】なお、ゲ−ト線（グランド線２５を含む）
上の大半の不要な上部絶縁膜は裏面露光を行う前後に基
板１の表面からのマスク露光により除去しても良い。こ
の場合、上部絶縁膜のチャネル幅方向の寸法は最終的な
ものより広くしておく。Note that the gate line (including the ground line 25)
Most of the unnecessary upper insulating film may be removed by mask exposure from the front surface of the substrate 1 before or after backside exposure. In this case, the dimension of the upper insulating film in the channel width direction is made larger than the final one.
【００３２】かくして本実施例によれば、ＴＦＴ特性が
不良になるということが無くなり、再現性、量産性の高
い液晶表示装置用のアクティブ型マトリクスアレイ基板
を製造することができる。次に本発明の他の実施例に係
るＴＦＴの製造方法を説明する。この実施例のＴＦＴの
製造方法が先に説明した実施例のそれと異なる点は、裏
面露光を用いないで保護膜１１を形成したことにある。Thus, according to this embodiment, there is no possibility that the TFT characteristics become defective, and it is possible to manufacture an active matrix array substrate for a liquid crystal display device with high reproducibility and mass productivity. Next, a method for manufacturing a TFT according to another embodiment of the present invention will be described. The TFT manufacturing method of this embodiment differs from that of the previously described embodiments in that the protective film 11 was formed without using backside exposure.
【００３３】即ち、最初、図１１，図１３に示すように
基板１上にゲ−ト線３，ゲ−ト絶縁膜５，アモルファス
シリコン７，上部絶縁膜を順次形成した後、全面にフォ
トレジストを塗布し、フォトマスクを用いて表面から露
光してフォトレジストパタ−ン９を形成する。次いでフ
ォトレジストパタ−ン９をマスクにして上部絶縁膜をパ
タ−ニングする。このとき、上部絶縁膜のチャネル幅方
向の寸法は最終的なものより広くしておく。That is, first, as shown in FIGS. 11 and 13, a gate line 3, a gate insulating film 5, an amorphous silicon 7, and an upper insulating film are sequentially formed on a substrate 1, and then a photoresist is applied over the entire surface. A photoresist pattern 9 is formed by applying and exposing the surface using a photomask. Next, the upper insulating film is patterned using the photoresist pattern 9 as a mask. At this time, the dimension of the upper insulating film in the channel width direction is made larger than the final one.
【００３４】次に図１２，図１４に示すように、フォト
レジストパタ−ン９を除去した後、ｎ＋ アモルファス
シリコン膜をアモルファスシリコン７上に形成し、次い
でフォトレジストパタ−ンを形成し、これをマスクにし
て不要部分のアモルファスシリコン，上部絶縁膜，ｎ＋
アモルファスシリコン膜１５を除去して保護膜１１，
活性層１３，コンタクト層１９を形成する。この後の工
程は先の実施例と同様である。Next, as shown in FIGS. 12 and 14, after removing the photoresist pattern 9, an n+ amorphous silicon film is formed on the amorphous silicon 7, and then a photoresist pattern is formed. Using the mask as a mask, remove unnecessary parts of amorphous silicon, upper insulating film, and n+
After removing the amorphous silicon film 15, the protective film 11,
An active layer 13 and a contact layer 19 are formed. The subsequent steps are similar to those in the previous example.
【００３５】このような製造方法でもｎ＋ アモルファ
スシリコン膜，アモルファスシリコン７膜及び上部絶縁
膜を同時にパタ−ニングしているので、活性層１３，コ
ンタクト層１９と保護膜１１とのマスク合わせずれがな
くなり、活性層１３及びコンタクト層１９のチャネル幅
方向の寸法を小さくできるので寄生素子の形成を防止で
きる。なお、交差部２７は従来通りのマスク合せのレイ
アウトとしたが、先の実施例と同様にアモルファスシリ
コン膜７，１５のエッチングで決まるレイアウトにして
も良い。Even in this manufacturing method, since the n+ amorphous silicon film, the amorphous silicon 7 film, and the upper insulating film are patterned at the same time, mask misalignment between the active layer 13, the contact layer 19, and the protective film 11 is eliminated. Since the dimensions of the active layer 13 and the contact layer 19 in the channel width direction can be reduced, the formation of parasitic elements can be prevented. Although the intersection 27 is laid out using conventional mask alignment, the layout may be determined by etching the amorphous silicon films 7 and 15 as in the previous embodiment.
【００３６】なお、本発明は上述した実施例に限定され
るものではない。実施例では基板１上に直接ゲ−ト線３
を形成したがこれらの間にシリコン酸化膜や金属膜酸化
膜等のアンダ−コ−トを設けても良い。更に、上部絶縁
膜上に直接フォトレジストを塗布する代わりに、密着性
を向上するなどのために上部絶縁膜上に他の層を形成し
た後にフォトレジストを塗布しても良い。また、コンタ
クト層１９の半導体の上に直接フォトレジストを塗布せ
ず、金属例えばＭｏなどを堆積した上に塗布しても良い
。更にまた、ゲ−ト絶縁膜５としてシリコン酸化膜とシ
リコン窒化膜との積層膜を用いたが、一部が上部絶縁膜
と異なる絶縁膜材料であれば他の絶縁膜を用いても良い
。要はゲ−ト絶縁膜５のエッチングレ−トが上部絶縁膜
のそれより遅くなれば良い。その他、本発明の要旨を逸
脱しない範囲で、種々変形して実施できる。Note that the present invention is not limited to the embodiments described above. In the embodiment, the gate line 3 is placed directly on the substrate 1.
However, an undercoat such as a silicon oxide film or a metal oxide film may be provided between these. Further, instead of applying the photoresist directly on the upper insulating film, the photoresist may be applied after forming another layer on the upper insulating film in order to improve adhesion. Further, the photoresist may not be applied directly onto the semiconductor of the contact layer 19, but may be applied after depositing a metal such as Mo. Furthermore, although a laminated film of a silicon oxide film and a silicon nitride film is used as the gate insulating film 5, other insulating films may be used as long as a portion thereof is made of a different insulating film material from the upper insulating film. The point is that the etching rate of the gate insulating film 5 should be slower than that of the upper insulating film. In addition, various modifications can be made without departing from the gist of the present invention.
【００３７】[0037]
【発明の効果】以上述べたように本発明の薄膜トランジ
スタでは、活性層，コンタクト層活性層及び保護膜のチ
ャネル幅方向の寸法が全て同じであるため、不要な活性
層，コンタクト層活性層が少なくなりＴＦＴ特性が改善
される。[Effects of the Invention] As described above, in the thin film transistor of the present invention, the dimensions of the active layer, contact layer active layer, and protective film in the channel width direction are all the same, so unnecessary active layers and contact layer active layers are reduced. Therefore, the TFT characteristics are improved.
【００３８】また、本発明の薄膜トランジスタの製造方
法では、第１，第２の半導体膜上部絶縁膜を同時にパタ
−ニングしているため、活性層，コンタクト層が保護膜
からチャネル方向にはみだすことなく形成されるのでＴ
ＦＴ特性の低下を引き起こす無く小型な薄膜トランジス
タを得ることができる。Furthermore, in the method for manufacturing a thin film transistor of the present invention, since the upper insulating films of the first and second semiconductor films are patterned simultaneously, the active layer and the contact layer do not protrude from the protective film in the channel direction. T because it is formed
A small thin film transistor can be obtained without causing deterioration of FT characteristics.
【図１】本発明一実施例に係るＴＦＴの製造工程断面図
。FIG. 1 is a sectional view showing the manufacturing process of a TFT according to an embodiment of the present invention.
【図２】本発明一実施例に係るＴＦＴの製造工程断面図
。FIG. 2 is a cross-sectional view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図３】本発明一実施例に係るＴＦＴの製造工程断面図
。FIG. 3 is a cross-sectional view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図４】本発明一実施例に係るＴＦＴの製造工程断面図
。FIG. 4 is a cross-sectional view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図５】本発明一実施例に係るＴＦＴの製造工程断面図
。FIG. 5 is a sectional view showing the manufacturing process of a TFT according to an embodiment of the present invention.
【図６】本発明一実施例に係るＴＦＴの製造工程平面図
。FIG. 6 is a plan view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図７】本発明一実施例に係るＴＦＴの製造工程平面図
。FIG. 7 is a plan view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図８】本発明一実施例に係るＴＦＴの製造工程平面図
。FIG. 8 is a plan view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図９】本発明一実施例に係るＴＦＴの製造工程平面図
。FIG. 9 is a plan view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図１０】本発明一実施例に係るＴＦＴの製造工程平面
。FIG. 10 is a plan view of the manufacturing process of a TFT according to an embodiment of the present invention.
【図１１】図６のＴＦＴのＡ−Ａ´断面図[Figure 11] A-A' cross-sectional view of the TFT in Figure 6
【図１２】図
７のＴＦＴのＡ−Ａ´断面図[Figure 12] A-A' cross-sectional view of the TFT in Figure 7
【図１３】図８のＴＦＴの
Ａ−Ａ´断面図[Figure 13] A-A' cross-sectional view of the TFT in Figure 8
【図１４】図９のＴＦＴのＡ−Ａ´断面
図[Figure 14] A-A' cross-sectional view of the TFT in Figure 9
【図１５】図１０のＴＦＴのＡ−Ａ´断面図[Figure 15] A-A' cross-sectional view of the TFT in Figure 10
【図１６
】本発明の他の実施例に係るＴＦＴの製造工程断面図。[Figure 16
]A sectional view showing the manufacturing process of a TFT according to another embodiment of the present invention.
【図１７】本発明の他の実施例に係るＴＦＴの製造工程
断面図。FIG. 17 is a sectional view showing the manufacturing process of a TFT according to another embodiment of the present invention.
【図１８】本発明の他の実施例に係るＴＦＴの製造工程
平面図。FIG. 18 is a plan view of the manufacturing process of a TFT according to another embodiment of the present invention.
【図１９】本発明の他の実施例に係るＴＦＴの製造工程
平面図。FIG. 19 is a plan view of the manufacturing process of a TFT according to another embodiment of the present invention.
【図２０】図１８のＴＦＴのＡ−Ａ´断面図[Figure 20] A-A' cross-sectional view of the TFT in Figure 18
【図２１】
図１９のＴＦＴのＡ−Ａ´断面図[Figure 21]
A-A' cross-sectional view of TFT in Figure 19
【図２２】従来のＴＦ
Ｔの製造工程断面図。[Figure 22] Conventional TF
A sectional view of the manufacturing process of T.
【図２３】従来のＴＦＴの製造工程断面図。FIG. 23 is a cross-sectional view of a conventional TFT manufacturing process.
【図２４】従来のＴＦＴの製造工程断面図。FIG. 24 is a cross-sectional view of a conventional TFT manufacturing process.
【図２５】従来のＴＦＴの製造工程断面図。FIG. 25 is a cross-sectional view of a conventional TFT manufacturing process.
【図２６】従来のＴＦＴの製造工程断面図。FIG. 26 is a cross-sectional view of a conventional TFT manufacturing process.
【図２７】従来のＴＦＴの製造工程平面図。FIG. 27 is a plan view of a conventional TFT manufacturing process.
【図２８】従来のＴＦＴの製造工程平面図。FIG. 28 is a plan view of a conventional TFT manufacturing process.
【図２９】従来のＴＦＴの製造工程平面図。FIG. 29 is a plan view of a conventional TFT manufacturing process.
【図３０】従来のＴＦＴの製造工程平面図。FIG. 30 is a plan view of a conventional TFT manufacturing process.
【図３１】従来のＴＦＴの製造工程平面図。FIG. 31 is a plan view of a conventional TFT manufacturing process.
【図３２】図２７のＴＦＴのＡ−Ａ´断面図。32 is a sectional view taken along line AA' of the TFT in FIG. 27;
【図３３】図２８のＴＦＴのＡ−Ａ´断面図。33 is a sectional view taken along line AA' of the TFT shown in FIG. 28;
【図３４】図２９のＴＦＴのＡ−Ａ´断面図。34 is a sectional view taken along line AA' of the TFT in FIG. 29;
【図３５】図３０のＴＦＴのＡ−Ａ´断面図。35 is a sectional view taken along line AA' of the TFT in FIG. 30;
【図３６】図３１のＴＦＴのＡ−Ａ´断面図。FIG. 36 is a sectional view taken along line AA' of the TFT in FIG. 31;
１…基板、３…ゲ−ト線、５…ゲ−ト絶縁膜、７…アモ
ルファスシリコン膜、７ａ…アモルファスシリコン膜の
はみだし部分、９，９ａ…フォトレジストパタ−ン、１
１…保護膜、１１ａ…保護膜のはみだし部分、１３…活
性層、１３ａ…活性層のはみだし部分、１５…ｎ＋ ア
モルファスシリコン膜、１７…画素電極、１９…コンタ
クト層、１９ａ…コンタクト層のはみだし部分、２１…
ソ−ス・ドレイン、２３…信号線、２５…グランド線、
２７…紫外線、２９…交差部。DESCRIPTION OF SYMBOLS 1... Substrate, 3... Gate line, 5... Gate insulating film, 7... Amorphous silicon film, 7a... Protruding part of amorphous silicon film, 9, 9a... Photoresist pattern, 1
DESCRIPTION OF SYMBOLS 1... Protective film, 11a... Protruding part of protective film, 13... Active layer, 13a... Protruding part of active layer, 15... N+ amorphous silicon film, 17... Pixel electrode, 19... Contact layer, 19a... Protruding part of contact layer , 21...
Source/drain, 23...signal line, 25...ground line,
27...Ultraviolet light, 29...Intersection.
Claims (2)
活性層と、この活性層にコンタクト層を介してコンタク
トすると共に保護膜を介して対向して配設されたソ−ス
及びドレイン電極と、前記活性層の下部にゲ−ト絶縁膜
を介して配設されたゲ−ト電極とを有する薄膜トランジ
スタにおいて、前記活性層，前記コンタクト層及び前記
保護膜のチャネル幅方向の寸法が全て同じであることを
特徴とする薄膜トランジスタ。1. An active layer formed with a predetermined pattern on a substrate, and source and drain electrodes that are in contact with this active layer via a contact layer and are disposed facing each other with a protective film interposed therebetween. and a gate electrode disposed below the active layer via a gate insulating film, wherein the active layer, the contact layer, and the protective film all have the same dimensions in the channel width direction. A thin film transistor characterized by:
記基板上にゲ−ト絶縁膜，活性層になる第１の半導体膜
，保護膜になる上部絶縁膜を順次堆積する工程と、前記
上部絶縁膜上に第１のレジストパタ−ンを形成し、これ
をマスクにして上部絶縁膜をパタ−ニングする工程と、
前記第１の半導体膜上に第２の半導体膜を形成する工程
と、前記第２の半導体膜上に第２のレジストパタ−ンを
形成し、これをマスクにして前記第１，第２の半導体膜
及び上部絶縁膜をパタ−ニングして活性層，コンタクト
層及び保護膜を形成する工程と、前記活性層の相対向す
る端面に前記コンタクト層を介してコンタクトするソ−
ス及びドレインを形成する工程とを有することを特徴と
する薄膜トランジスタの製造方法。2. A step of forming a gate electrode on a substrate, and a step of sequentially depositing a gate insulating film, a first semiconductor film to become an active layer, and an upper insulating film to become a protective film on the substrate. forming a first resist pattern on the upper insulating film, and patterning the upper insulating film using this as a mask;
forming a second semiconductor film on the first semiconductor film; forming a second resist pattern on the second semiconductor film; using this as a mask, forming a second semiconductor film on the first and second semiconductor films; A step of patterning the film and the upper insulating film to form an active layer, a contact layer, and a protective film, and a step of contacting opposing end surfaces of the active layer through the contact layer.
1. A method for manufacturing a thin film transistor, the method comprising: forming a source and a drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4508391A JPH04282839A (en) | 1991-03-11 | 1991-03-11 | Thin film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4508391A JPH04282839A (en) | 1991-03-11 | 1991-03-11 | Thin film transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04282839A true JPH04282839A (en) | 1992-10-07 |
Family
ID=12709435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4508391A Pending JPH04282839A (en) | 1991-03-11 | 1991-03-11 | Thin film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04282839A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000235190A (en) * | 1999-02-12 | 2000-08-29 | Internatl Business Mach Corp <Ibm> | Liquid crystal display panel and its production |
| JP2004241769A (en) * | 2003-01-17 | 2004-08-26 | Semiconductor Energy Lab Co Ltd | Method of framing resist pattern and method of manufacturing semiconductor device |
| JP2010192935A (en) * | 2003-01-17 | 2010-09-02 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| US8053174B2 (en) | 2003-02-05 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
-
1991
- 1991-03-11 JP JP4508391A patent/JPH04282839A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000235190A (en) * | 1999-02-12 | 2000-08-29 | Internatl Business Mach Corp <Ibm> | Liquid crystal display panel and its production |
| JP4674926B2 (en) * | 1999-02-12 | 2011-04-20 | エーユー オプトロニクス コーポレイション | Liquid crystal display panel and manufacturing method thereof |
| JP2004241769A (en) * | 2003-01-17 | 2004-08-26 | Semiconductor Energy Lab Co Ltd | Method of framing resist pattern and method of manufacturing semiconductor device |
| JP2010192935A (en) * | 2003-01-17 | 2010-09-02 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| JP2010258473A (en) * | 2003-01-17 | 2010-11-11 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| JP2011054994A (en) * | 2003-01-17 | 2011-03-17 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JP4656843B2 (en) * | 2003-01-17 | 2011-03-23 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4667532B2 (en) * | 2003-01-17 | 2011-04-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4667529B2 (en) * | 2003-01-17 | 2011-04-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US8053174B2 (en) | 2003-02-05 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
| US8460857B2 (en) | 2003-02-05 | 2013-06-11 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
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