JPH0428243A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0428243A JPH0428243A JP2133012A JP13301290A JPH0428243A JP H0428243 A JPH0428243 A JP H0428243A JP 2133012 A JP2133012 A JP 2133012A JP 13301290 A JP13301290 A JP 13301290A JP H0428243 A JPH0428243 A JP H0428243A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- flip chip
- circuit device
- holes
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000010354 integration Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は混成集積回路装置に係り、詳しくは、ヒート
シンクに接合される厚膜抵抗基板上に実装されたフリッ
プチップ素子の実装方向に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to the mounting direction of a flip-chip element mounted on a thick film resistor substrate bonded to a heat sink.
近年、電子回路装置における高密度実装技術はめざまし
く進展しており、その進展を支える素子実装方法の一つ
として、フリップチップ素子を用いたフェースダウンポ
ンディングを採用する例が数多くなっている。そして、
このフェースダウンボンディングを採用した電子回路装
置の一例としζば、自動車用機器などに搭載される混成
集積回路装置が知られている。BACKGROUND ART In recent years, high-density packaging technology for electronic circuit devices has made remarkable progress, and face-down bonding using flip-chip elements is increasingly being adopted as one of the element mounting methods that support this progress. and,
As an example of an electronic circuit device employing this face-down bonding, a hybrid integrated circuit device installed in automobile equipment and the like is known.
この混成集積回路装置は、第３図及び第４図で示すよう
に、矩形平板状とされたヒートシンク１と、これの表面
上に接着用樹脂２を介して接合された矩形平板状の厚膜
抵抗基板３と、その表面上に実装された平面視矩形状の
フリップチップ素子４とを備えている。そして、これら
のヒートシンク１、厚膜抵抗基板３及びフリップチップ
素子４は、第４図で示すように、互いの平面視形状が揃
う状態、すなわち、各々の角部が同一方向を向くように
して重ね合わされるのが一般的であり、厚膜抵抗基板３
及びフリップチップ素子４はヒートシンク１の表面−ト
に固着されたケース５によって封ｔｌニされている。As shown in FIGS. 3 and 4, this hybrid integrated circuit device includes a rectangular flat heat sink 1 and a rectangular flat thick film bonded to the surface of the heat sink 1 via an adhesive resin 2. It includes a resistor substrate 3 and a flip chip element 4 which is rectangular in plan view and mounted on the surface of the resistor substrate 3. As shown in FIG. 4, these heat sink 1, thick film resistance substrate 3, and flip chip element 4 are arranged so that their mutual planar shapes are aligned, that is, their respective corners face in the same direction. Generally, the thick film resistor substrate 3 is overlaid.
The flip chip device 4 is sealed by a case 5 fixed to the surface of the heat sink 1.
また、このヒートシンク１における一方の対角線り上の
端部、すなわち、その互いに対向する角部位置それぞれ
には、完成した混成集積回路装置を所要機器などに取り
付けるための取付用孔６゜６が形成される一方、セラミ
ックなどからなる厚膜抵抗基板３の表面上には所定形状
の導体配線（図示していない）が形成されている。そし
て、この厚膜抵抗基板３上の導体配線にはフリップチッ
プ素子４の裏面側に形成された複数の突起電極、いわゆ
るバンプ７、・・・がそれぞれ対応して接続されている
。なお、これらのバンプ７、・・・は半田などによって
形成されており、第５図で示すように、パターン設計上
の効率が最も良いフリップチップ素子４の最外周端縁に
沿って並列配置されている。Further, at one diagonal end of the heat sink 1, that is, at each corner position facing each other, a mounting hole 6°6 is formed for mounting the completed hybrid integrated circuit device to a required device, etc. On the other hand, conductor wiring (not shown) in a predetermined shape is formed on the surface of the thick film resistance substrate 3 made of ceramic or the like. A plurality of protruding electrodes, so-called bumps 7, . . . formed on the back side of the flip chip element 4 are connected to the conductive wiring on the thick film resistive substrate 3 in correspondence with each other. These bumps 7, . . . are formed of solder or the like, and are arranged in parallel along the outermost edge of the flip chip element 4, which is most efficient in terms of pattern design, as shown in FIG. ing.
ところで、完成した前記従来構成の混成集積回路装置は
、第３図で示すように、そのヒートシンク１の取（す用
孔６．６を挿通ずる取付用ネジ８゜８によって所要機器
（図示していない）に取り付けられる。そこで、ヒート
シンク１の平面度が良好でなかったり、取付用ネジ８．
８の締め付は力によってヒートシンク１が反ったりした
場合には、ごれらの締め付は力に伴って発生した応力が
取付用孔６，６を結ぶヒートシンク１の対角線りに沿っ
て作用することになる。そして、このとき、ヒートシン
ク１、厚膜抵抗基板３及びフリップチップ素子４各々の
角部が対角線りに沿う同一方向を向いて重ね合わされて
いることから、取付用ネジ８．８の締め（−１け力に伴
って発生した応力はフリップチップ素子４の角部に位置
するバンプ７゜による接続部分に対して集中的に加わる
ことになり、この接続部分の半田付けが破損して断線に
到ることがあった。By the way, as shown in FIG. 3, the completed hybrid integrated circuit device having the conventional configuration can be attached to the required equipment (not shown) using the mounting screws 8.8 inserted through the mounting holes 6.6 of the heat sink 1. Therefore, if the flatness of the heat sink 1 is not good or the mounting screws 8.
If the heat sink 1 warps due to force, the stress generated by the force acts along the diagonal line of the heat sink 1 connecting the mounting holes 6, 6. It turns out. At this time, since the corners of the heat sink 1, thick film resistance substrate 3, and flip chip element 4 are stacked on top of each other with their respective corners facing in the same direction along the diagonal line, the mounting screws 8.8 are tightened (-1 The stress generated due to the stress is concentratedly applied to the connection portion formed by the bump 7° located at the corner of the flip chip element 4, and the soldering at this connection portion is damaged, leading to disconnection. Something happened.
本発明は、このような不都合に鑑みて創案されたもので
あって、取付用ネジの締め付は力に伴う応力がフリップ
チップ素子に形成された特定のバンプによる接続部分の
みに集中して加わることを防止することができ、信頼性
の向上を図ることが可能な構成の混成集積回路装置を提
供することを目的としている。The present invention was devised in view of these inconveniences, and the stress associated with the tightening of the mounting screw is concentrated only on the connection portion formed by the specific bump formed on the flip chip element. It is an object of the present invention to provide a hybrid integrated circuit device having a configuration that can prevent such problems and improve reliability.
この発明は、矩形平板状とされ、対角線上に取付用孔が
形成されたヒートシンクと、これに接合される厚膜抵抗
基板上に実装された平面視矩形状のフリップチップ素子
とを備えた混成集積回路装置において、前記フリップチ
ップ素子を、その互いに対向する２辺が前記取付用孔を
結ぶ対角線と直交するよう位置決めして前記厚膜抵抗基
板上に実装したことを特徴とするものである。The present invention provides a hybrid heat sink that has a rectangular flat plate shape and has mounting holes formed on diagonal lines, and a flip chip element that is rectangular in plan view and that is mounted on a thick film resistor board that is bonded to the heat sink. The integrated circuit device is characterized in that the flip chip element is mounted on the thick film resistor substrate with the flip chip element positioned such that two opposing sides thereof are perpendicular to a diagonal line connecting the mounting holes.
上記構成によれば、ヒートシンクに形成された取付用孔
を結ぶ対角線と、フリップチップ素子の互いに対向する
２辺とを直交させているので、取付用ネジの締め付は力
に伴って発生し、かつ、前記対角線に沿って作用する応
力はフリソプチ・ノブ素子の前記２辺それぞれに沿って
並列配置されたバンプの接続部分それぞれに分散して加
わることになる。According to the above configuration, since the diagonal line connecting the mounting holes formed in the heat sink and the two mutually opposing sides of the flip chip element are perpendicular to each other, the tightening of the mounting screw occurs with force. Moreover, the stress acting along the diagonal line is distributed and applied to each of the connecting portions of the bumps arranged in parallel along each of the two sides of the Frisopti knob element.
以下、本発明に係る一実施例を図面に基づいて説明する
。EMBODIMENT OF THE INVENTION Hereinafter, one Example based on this invention is described based on drawing.
第１図は本実施例に係る混成集積回路装置の構成を示す
一部破断側面図であり、第２図は第１図のｎ−ｎ線に沿
う一部破断側面図である。なお、この混成集積回路装置
の構成は、フリップチップ素子の実装方向が異なる点を
除き、前述した従来例と基本的に異ならない。そこで、
本実施例を示す第１図及び第２図において、従来例を示
す第３図及び第４図と互いに同一もしくは相当する部品
、部分については同一符号を付している。FIG. 1 is a partially cutaway side view showing the configuration of a hybrid integrated circuit device according to this embodiment, and FIG. 2 is a partially cutaway side view taken along line nn in FIG. 1. The configuration of this hybrid integrated circuit device is basically the same as the conventional example described above, except for the mounting direction of the flip-chip elements. Therefore,
In FIGS. 1 and 2 showing this embodiment, parts and portions that are the same or corresponding to those in FIGS. 3 and 4 showing the conventional example are given the same reference numerals.
この混成集積回路装置は、矩形平板状とされ、かつ、対
角線り上の端部となる角部位置それぞれに取イ１用孔６
．６が形成されたヒートシンク１と、これの表面上に接
着用樹脂２を介して接合された矩形平板状の厚膜抵抗基
板３と、その表面上に実装された平面視矩形状のフリッ
プチップ素子４とを備えている。そして、このフリップ
チップ素子４は、その互いに対向する２辺４ａ、４ａが
取付用孔６．６を結ぶ対角線りと直交するように位置決
めされたうえで厚膜抵抗基板３上に実装されている。す
なわち、このフリップチップ素子４の実装方向は、ヒー
トシンク１及び厚膜抵抗基板３の角部が同一方向を向く
ように接合されることにより、これらの両者の対角線ｒ
、に対して共に直交していることになる。This hybrid integrated circuit device has a rectangular flat plate shape, and has holes for holes 1 at each corner position on the diagonal line.
．． 6 is formed on the heat sink 1, a rectangular flat thick film resistance substrate 3 bonded to the surface of the heat sink 1 via an adhesive resin 2, and a flip chip element having a rectangular shape in plan view mounted on the surface of the heat sink 1. 4. The flip chip element 4 is mounted on the thick film resistor substrate 3 with its two opposing sides 4a, 4a positioned orthogonal to the diagonal line connecting the mounting holes 6.6. . That is, the mounting direction of the flip-chip element 4 is aligned with the diagonal line r of the heat sink 1 and the thick film resistor substrate 3 by joining them so that their corners face in the same direction.
, are both orthogonal to .
したがって、このフリップチップ素子４の裏面側に形成
されたバンプ７、・・・の内、その２辺４ａ４ａに沿っ
て並列配置されたバンプ７、、・・・による接続部分は
、ヒートシンク１に形成された取付用孔６．６を結ぶ対
角線■７と直交した状態で配置されていることになる。Therefore, among the bumps 7, . . . formed on the back side of the flip chip element 4, the connection portions by the bumps 7, . The mounting hole 6.6 is arranged perpendicular to the diagonal line 7 connecting the mounting holes 6.6.
そこで、完成した混成集積回路装置を、第１図で示すよ
うに、そのヒートシンク１の取イζＪ用孔６，６を挿通
ずる取付用ネジ８．８によって所要機器（図示していな
い）に取り付けた際、これらの取付用ネジ８．８の締め
付は力に伴う応力が発生し、この応力が取付用孔６６を
結ふヒートシンク１の対角線■、に沿って作用すること
があっても、この応力はフリップチップ素子４の２辺４
ａ、４ａに沿って並列配置されたバンプ７１．・・・に
よる接続部分それぞれに分散して加わることになる。Therefore, as shown in FIG. 1, the completed hybrid integrated circuit device is attached to the required equipment (not shown) using mounting screws 8.8 inserted through the holes 6, 6 for the holes 6, 6 in the heat sink 1. When these mounting screws 8.8 are tightened, stress occurs due to the force, and even though this stress may act along the diagonal line (■) of the heat sink 1 connecting the mounting holes 66, This stress is applied to the two sides 4 of the flip chip element 4.
Bumps 71.a and 4a arranged in parallel. ... will be distributed and added to each connection part.
取手説明したように、この発明によれば、取イ」用ネジ
の締めイ」げ力に伴って発生し、前記対角線に沿って作
用する応力はフリップチップ素子の前記２辺それぞれに
沿って＼１１列配電“されたハンプの接続部分それぞれ
に分散して加わることになる。Handle As explained above, according to the present invention, the stress generated along with the tightening force of the handle screw and acting along the diagonal line is applied along each of the two sides of the flip chip element. The power will be distributed and applied to each of the connection parts of the hump with 11 rows of power distribution.
そのため、取付用ネジの締め付は力に伴う応力が、従来
例のように、特定のハンプによる接続部分のみ乙こ集中
して作用することはなく、その断線を招くことがなくな
る結果、信頼性の大幅な向１−を図ることができるとい
う優れた効果が得られる。Therefore, when tightening the mounting screws, the stress associated with the force does not concentrate on only the connection part made by a specific hump, as in the conventional example, and as a result, there is no possibility of wire breakage, resulting in improved reliability. An excellent effect can be obtained in that it is possible to achieve a significant improvement in
第１図及び第２図は本発明の一実施例に係り、第１図は
混成集積回路装置の構成を示す−・部破断側面図であり
、第２図は第１図の■■−ＩＩ線に沿う一部破断平面図
である。また、第３図ないし第５図は従来例に係り、第
３図は混成集積回路装置の構成を示す−・部破断側面図
、第４図は第３図の■ＩＶ線に沿う一部破断″ｆ；面図
であり、第５図はフリップチップ素子の裏面図である。
図における符号］はヒートシンク、３は厚膜抵抗基板、
４はフリップチップ素子、６は取付用孔、Ｉ７は対角線
である。
なお、図中の同一符号は、互いに同一もしくは相当する
部品、部分を示している。1 and 2 relate to one embodiment of the present invention, FIG. 1 is a partially cutaway side view showing the configuration of a hybrid integrated circuit device, and FIG. FIG. 3 is a partially cutaway plan view taken along a line. 3 to 5 relate to a conventional example, FIG. 3 shows the configuration of a hybrid integrated circuit device, and FIG. 4 is a partially cutaway side view taken along line IV in FIG. 3. ``f; is a side view, and FIG. 5 is a back view of the flip chip element. Code] in the figure is a heat sink, 3 is a thick film resistor substrate,
4 is a flip chip element, 6 is a mounting hole, and I7 is a diagonal line. Note that the same reference numerals in the drawings indicate parts and portions that are the same or correspond to each other.
Claims (1)
れたヒートシンクと、これに接合される厚膜抵抗基板上
に実装された平面視矩形状のフリップチップ素子とを備
えた混成集積回路装置において、前記フリップチップ素
子を、その互いに対向する２辺が前記取付用孔を結ぶ対
角線と直交するよう位置決めして前記厚膜抵抗基板上に
実装したことを特徴とする混成集積回路装置。(1) Hybrid integration comprising a rectangular flat heat sink with mounting holes formed diagonally, and a flip-chip element that is rectangular in plan view and mounted on a thick film resistor board that is bonded to the heat sink. In the circuit device, the hybrid integrated circuit device is characterized in that the flip chip element is mounted on the thick film resistor substrate with the flip chip element positioned such that two opposing sides thereof are perpendicular to a diagonal line connecting the mounting hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133012A JPH0428243A (en) | 1990-05-23 | 1990-05-23 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133012A JPH0428243A (en) | 1990-05-23 | 1990-05-23 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0428243A true JPH0428243A (en) | 1992-01-30 |
Family
ID=15094732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2133012A Pending JPH0428243A (en) | 1990-05-23 | 1990-05-23 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0428243A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034436A1 (en) | 1997-12-24 | 1999-07-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
-
1990
- 1990-05-23 JP JP2133012A patent/JPH0428243A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034436A1 (en) | 1997-12-24 | 1999-07-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| US6303998B1 (en) | 1997-12-24 | 2001-10-16 | Shinko Electric Industries Co., Ltd. | Semiconductor device having a chip mounted on a rectangular substrate |
| KR100365349B1 (en) * | 1997-12-24 | 2002-12-18 | 신꼬오덴기 고교 가부시키가이샤 | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6239012B1 (en) | Vertically mountable semiconductor device and methods | |
| US6501157B1 (en) | Substrate for accepting wire bonded or flip-chip components | |
| US4435740A (en) | Electric circuit packaging member | |
| TW512498B (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
| US5627405A (en) | Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer | |
| US5367435A (en) | Electronic package structure and method of making same | |
| US5724230A (en) | Flexible laminate module including spacers embedded in an adhesive | |
| WO2000070677A1 (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
| JP2001185640A (en) | Surface mounting package, electronic device and method for manufacturing electronic device | |
| US6034437A (en) | Semiconductor device having a matrix of bonding pads | |
| US6537852B2 (en) | Spacer - connector stud for stacked surface laminated multichip modules and methods of manufacture | |
| JPH0428243A (en) | Hybrid integrated circuit device | |
| WO2000049652A1 (en) | Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device | |
| JPH10189655A (en) | Wiring board, semiconductor device and mounting of electronic component | |
| JP3334816B2 (en) | Semiconductor device and method of mounting semiconductor device | |
| JP2738232B2 (en) | Printed board | |
| JP3838524B2 (en) | Semiconductor device | |
| JPH0440277Y2 (en) | ||
| JPH0645763A (en) | Printed wiring board | |
| JP2002252304A (en) | Semiconductor device and support substrate used therefor | |
| JPH04167553A (en) | Semiconductor device | |
| JPH0631723Y2 (en) | Semiconductor device | |
| JPH11251473A (en) | Insulating substrate, semiconductor device and semiconductor mounting device | |
| JPH0751794Y2 (en) | Semiconductor mounting structure | |
| JPH0634437B2 (en) | Board connection structure |