JPH0426199A - Mounting structure of multilayer board - Google Patents
Mounting structure of multilayer boardInfo
- Publication number
- JPH0426199A JPH0426199A JP2130310A JP13031090A JPH0426199A JP H0426199 A JPH0426199 A JP H0426199A JP 2130310 A JP2130310 A JP 2130310A JP 13031090 A JP13031090 A JP 13031090A JP H0426199 A JPH0426199 A JP H0426199A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer board
- flip
- component
- via hole
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 7
- 150000002739 metals Chemical class 0.000 abstract description 3
- 230000008602 contraction Effects 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 238000007747 plating Methods 0.000 description 5
- 238000010304 firing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、多層基板の実装構造に関し、特に多層基板の
外部表面にフリップチップ構造のＩＣ部品をフェイスダ
ウン装着してなる多層基板の実装構造に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mounting structure of a multilayer board, and particularly to a mounting structure of a multilayer board in which IC components of a flip-chip structure are mounted face-down on the external surface of the multilayer board. It is related to.
〔従来の技術ｌ
ＩＣ−ＬＳＩ素子から端子を引き出す方法は、ワイヤボ
ンディング、テープキャリヤ及びフリップチップに大別
されるが、そのうちフリップチップはフェイスダウン装
着されるため、素子全面から端子を取出すことができ、
素子の多端子化に対応でき、かつ、基板上の実装密度を
高めることができる。[Conventional technology l Methods for extracting terminals from IC-LSI elements are broadly classified into wire bonding, tape carrier, and flip chip. Of these, flip chips are mounted face down, so it is not possible to extract terminals from the entire surface of the element. I can,
It is possible to cope with the increase in the number of terminals of elements, and to increase the mounting density on the substrate.
従来、多層基板へのフリップチップ実装構造は、図−３
に示すように、多層基板１４の外部表面にヴァイアホー
ル１５と接続する外部配線１１を印刷し、更にオーバー
コート１２を塗布し、フリップチップ構造のＩＣ部品ｌ
の端子の半田バンブ３に対応する基板上のボンディング
箇所でオーバーコート１２に窓開けし、露出した外部配
線部に金メツキ１３を施した後、その上に半田バンブ１
８を形成させ、フリップチップ構造のＩＣ部品ｌをフェ
イスダウン載置して両者の半田バンブ３と１８とを接触
させ、加熱して半田を溶融接合して得られた構造であっ
た。Conventionally, the flip-chip mounting structure on a multilayer board is shown in Figure 3.
As shown in FIG. 2, external wiring 11 connecting to via hole 15 is printed on the external surface of multilayer substrate 14, and overcoat 12 is further applied to form an IC component with a flip-chip structure.
After opening a window in the overcoat 12 at the bonding point on the board corresponding to the solder bump 3 of the terminal, and applying gold plating 13 to the exposed external wiring part, solder bump 1 is placed on top of it.
8 was formed, an IC component 1 having a flip-chip structure was placed face down, the solder bumps 3 and 18 of both were placed in contact with each other, and the solder was melted and bonded by heating.
［発明が解決しようとする課題］
前記したように、このようなフリップチップボンディン
グは、多端子化に対応でき、かつ、素子の実装密度を高
めることが可能であると共に、その接合プロセスもテー
プキャリヤに比較すれば簡単であるが、それでもオーバ
ーコートの塗布やその窓開け、半田バンブ形成のための
メツキ処理等の工程が必要であり、これらの工程の簡略
化が課題であった。[Problems to be Solved by the Invention] As mentioned above, such flip chip bonding can support multi-terminals and increase the packaging density of elements, and the bonding process can also be performed using tape carriers. However, it still requires steps such as applying an overcoat, opening the window, and plating to form solder bumps, and the challenge was to simplify these steps.
従来、多層基板のヴァイアホール抜き用のパンチャー径
は２５０〜３００μｌあり、そのためヴァイアホールの
最小ピッチは５００〜６００１ｍ＋が限度であるのに対
し、搭載フリップチップ素子のボンディングピッチは２
００〜３００ ｕｔｎであった。そのため、フリップチ
ップ素子の接点に合わせて基板上にボンディングのため
の接点を設けるには、基板上の対応位置まで配線形成す
る必要があり、がっ、半田の流れによる短絡を防止する
ためのオーバーコート塗布及び素子の接点位置に合わせ
てのオーバーコートの窓開けを必要としていた。Conventionally, the diameter of a puncher for punching via holes in multilayer substrates is 250 to 300 μl, and therefore the minimum pitch of via holes is limited to 500 to 6001 m+, whereas the bonding pitch of mounted flip chip elements is 2.
It was 00-300 utn. Therefore, in order to provide bonding contacts on the board to match the contacts of the flip-chip element, it is necessary to form wiring to the corresponding position on the board. It was necessary to apply a coat and open a window in the overcoat to match the contact position of the element.
［課題を解決するための手段〕
最近、ヴァイアホール抜き用パンチャーとして、径が６
０〜１００μｍのものが使用されてきており、これによ
ってヴァイアホールのピッチを１２０〜２００μｍまで
近接することが可能になった０本発明はこれに対応して
、従来のオーバーコート及びその窓開は工程を省略し、
ヴァイアホール端部に直接フリップチップボンディング
した実装構造を提供するものである。[Means for solving the problem] Recently, a puncher with a diameter of 6 mm has been used as a puncher for punching via holes.
0 to 100 μm has been used, and this has made it possible to close the pitch of via holes to 120 to 200 μm.The present invention corresponds to this, and the conventional overcoat and its aperture are Skip the process,
This provides a mounting structure in which flip-chip bonding is performed directly on the end of the via hole.
すなわち、本発明は、多層基板の外部表面にフリップチ
ップ構造のＩＣ部品をフェイスダウン装着してなる多層
基板の実装構造において、ＩＣ部品が多層基板表面のヴ
ァイアホール充填金属層に直接フリップチップボンディ
ングされていることを特徴とする多層基板の実装構造で
ある。That is, the present invention provides a mounting structure for a multilayer board in which IC components of a flip-chip structure are mounted face-down on the external surface of the multilayer board, in which the IC components are directly flip-chip bonded to the via hole filling metal layer on the surface of the multilayer board. This is a multilayer board mounting structure characterized by:
図−１は本発明の実装構造を示す断面図で。Figure 1 is a sectional view showing the mounting structure of the present invention.
フェイスタウン載置されるＩＣ部品１の半田バンブ３と
多層基板４の内部配線７から導かれたヴァイアホール５
の基板表面に露出したヴァイアホール充填金属６の端部
６゛とが接触する前の状態を示す。A via hole 5 led from the solder bump 3 of the IC component 1 mounted on the face town and the internal wiring 7 of the multilayer board 4
This shows the state before the exposed end 6' of the via hole filling metal 6 comes into contact with the surface of the substrate.
本発明の実装構造は１図＝１の相互に対応するヴァイア
ホール充填金属端部６゛とＩＣ部品の半田バンブ３とが
加熱により融着した構造である。The mounting structure of the present invention is a structure in which the mutually corresponding via hole filling metal ends 6' and the solder bumps 3 of the IC component are fused together by heating.
また充填金属は、銀、銀−パラジウム、銀−白金、銅、
金などを使用することができる。Filling metals include silver, silver-palladium, silver-platinum, copper,
You can use gold etc.
ヴァイアホール充填金属端部６゛には、更に充填金属の
土に他の金属２錫、金、半田等をメツキ、デイツプ等に
より形成してもよい、すなわち、ヴァイアホール端部６
′は、そのままでもＩＣ部品の半田バンブ３と融着によ
り接続が行われるが、例えば錫メツキを施すことにより
、チップ側の半田バンブ３と接触溶融する際、接触部で
半田の融点が低下し、溶融が確実に行われる。The via hole filling metal end 6' may be further formed with other metals such as tin, gold, solder, etc. on the soil of the filling metal by plating, dipping, etc.
' can be connected to the solder bump 3 of the IC component by fusion even if it is as it is, but by applying tin plating, for example, when it comes into contact with the solder bump 3 on the chip side and melts, the melting point of the solder decreases at the contact part. , ensuring melting.
また、ヴァイアホール充填金属端部６°に予め半田デイ
ツプをしてもよい。Further, a solder dip may be applied in advance to the 6° end of the metal filling the via hole.
本発明の実装構造においては、基板表面のヴァイアホー
ル端部の位置は、搭載される部品の接点位置に合わせて
設計される。ただし、多層基板においては、内部配線及
びそれから外部へ導くヴァイアホールの穿孔及び導体金
属の充填は、基板の積層前のグリーンシートに対して行
われ、積層後の焼成によって基板の収縮により接点位置
が変化するので、設計に際しては基板の収縮率許容範囲
を、例えばセラミックグリーンシートにおいては±０．
３％以下程度におくことが必要である。In the mounting structure of the present invention, the position of the end of the via hole on the substrate surface is designed to match the contact position of the component to be mounted. However, in multilayer boards, the internal wiring and via holes leading from there to the outside are drilled and filled with conductive metal on the green sheet before the board is laminated, and the contact positions are changed due to shrinkage of the board during baking after lamination. Therefore, during design, the allowable range of shrinkage rate of the substrate should be set, for example, ±0.0 for ceramic green sheets.
It is necessary to keep it at about 3% or less.
多層基板の焼成の際の収縮は、ヴァイアホールに充填さ
れた導体金属１例えば銀の収縮より一般に大きいので、
焼成された多層基板においてはヴァイアホールの端部は
基板表面に盛り上がっており、特に半田バンブを設けな
くても容易にフリップチップボンディングが可能となる
。The shrinkage during firing of a multilayer board is generally larger than that of the conductive metal 1, such as silver, filled in the via hole.
In the fired multilayer substrate, the ends of the via holes are raised on the surface of the substrate, and flip chip bonding is easily possible without the need for providing solder bumps.
〔実施例］ 本発明の実施例を図面に基づいて詳述する。〔Example] Embodiments of the present invention will be described in detail based on the drawings.
図−２は、本発明の実装構造を実現するための製造途中
の断面図である。フリップチップＩＣ搭載側（最外層）
のグリーンシート２０は厚さ １５０ｕＩｌで、 １０
０ ｐｍ径のヴァイアホール５と銀ペーストを用いた充
填金属６及び同様に銀ペーストを用いた内部配線７が形
成されている。この最外層に積層される内層のグリーン
シー１−２１は、厚さ １５０ｕｚで、 ｌＯｈｍ径の
ヴァイアホール５とダミーヴァイアホール１９、銀ペー
ストを用いた充填金属６及び同様に銀ペーストを用いた
内部配置１７が形成されている。ダミーヴァイアホール
１９は、焼成後のヴァイアホールの盛り上がり高さを一
様にするのに必要である。FIG. 2 is a cross-sectional view during manufacturing to realize the mounting structure of the present invention. Flip chip IC mounting side (outermost layer)
The green sheet 20 has a thickness of 150 uIl and 10
A via hole 5 with a diameter of 0 pm, a filling metal 6 using silver paste, and an internal wiring 7 similarly using silver paste are formed. The inner layer Green Sea 1-21 laminated on this outermost layer has a thickness of 150 uz and includes a via hole 5 with a diameter of 1 Ohm, a dummy via hole 19, a filling metal 6 using silver paste, and an inner layer using silver paste as well. An arrangement 17 is formed. The dummy via hole 19 is necessary to make the raised height of the via hole uniform after firing.
他の内層は、図示を省略した。Other inner layers are omitted from illustration.
これら各層のグリーンシートを位置合わせして積層し、
プレスした後、グリーンシートの一構成物であるバイン
ダーを焼き飛ばし、次いで焼成することにより図−１の
多層基板４を得た。These green sheets of each layer are aligned and stacked,
After pressing, the binder, which is a component of the green sheet, was burned off and then fired to obtain the multilayer substrate 4 shown in FIG. 1.
グリーンシート２０．２１は、ガラス・セラミックス系
で焼成による収縮率が１４％のグリーンシートを使用し
、充填金属６は焼成による収縮率が１０％の銀ペースト
を用いた。その場合、ヴァイアホール充填金属６の端部
６゛における盛り上がり高さは１５Ｈであった。The green sheets 20 and 21 were glass-ceramic green sheets with a shrinkage rate of 14% upon firing, and the filling metal 6 was a silver paste with a shrinkage rate of 10% upon firing. In this case, the height of the swell at the end 6'' of the via hole filling metal 6 was 15H.
上記充填金属６の盛り上がり高さは、最外層から３層目
（図示していない）にまでダミーヴァイアホールを形成
し、充填金属を形成することで更に高くでき、２０１１
ａ＋どなった。The height of the filling metal 6 can be further increased by forming a dummy via hole from the outermost layer to the third layer (not shown) and forming a filling metal.
a+ What happened?
これらの多層基板に半田バンブ付きＩＣを一般的な方法
でフリップチップ実装し、良好な接続が得られた。ICs with solder bumps were flip-chip mounted on these multilayer boards using a conventional method, and good connections were obtained.
〔発明の効果］
本発明のフリップチップ実装構造は、多層基板表面のヴ
ァイアホール端部が直接フリップチップボンディングさ
れた構造であり、従来のフリップチップ実装に際しての
ヴァイアホールと接続する外部配線形成、オーバーコー
ト塗布、接点部の窓開け、めっき、などの工程が不要と
なり、実装工程が簡略化され、実装密度も更に高度化さ
れる。[Effects of the Invention] The flip-chip mounting structure of the present invention has a structure in which the ends of the via holes on the surface of the multilayer substrate are directly flip-chip bonded. Processes such as coating, opening of contact areas, and plating are no longer necessary, simplifying the mounting process and further increasing the packaging density.
図−１は本発明の実装構造を示す部分断面図で、ＩＣ部
品の半田バンブと基板表面のヴァイアホール充填金属の
端部とが接触する前の状態を示す。
図−２は２本発明の実装構造を実現するための製造途中
の部分断面図で、積層されるグリーンシートの最外層及
び内層を示す。
図−３は従来のフリップチップボンディングを示す部分
断面図である。
Ｉ−・・ＩＣ部品、３．１８−・−半田バンブ、４・・
・多層基板、５．１５・・・ヴァイアホール、６・・−
ヴァイアホール充填金属、６゛・・−ヴァイアホール端
部、７．１７・・・内部配線、１１・・・外部配線、１
２・・・オーバーコート、１８・・−半田バンブ、１９
・・・ダミーヴァイアホール、２０−・・フリップチッ
プＩＣ搭載側グリーンシート、２１・・・内層グリーン
シート。FIG. 1 is a partial cross-sectional view showing the mounting structure of the present invention, and shows the state before the solder bump of the IC component and the end of the via hole filling metal on the surface of the board come into contact. FIG. 2 is a partial cross-sectional view during the manufacturing process for realizing the mounting structure of the present invention, showing the outermost layer and inner layer of the green sheets to be laminated. FIG. 3 is a partial cross-sectional view showing conventional flip chip bonding. I-...IC parts, 3.18--Solder bumps, 4...
・Multilayer board, 5.15... Via hole, 6...-
Via hole filling metal, 6゛... - Via hole end, 7.17... Internal wiring, 11... External wiring, 1
2...Overcoat, 18...-Solder bump, 19
...Dummy via hole, 20-.Flip chip IC mounting side green sheet, 21..Inner layer green sheet.
Claims (1)
部品をフェイスダウン装着してなる多層基板の実装構造
において、ＩＣ部品が多層基板表面のヴァイアホール充
填金属層に直接フリップチップボンディングされている
ことを特徴とする多層基板の実装構造。(1) IC with flip-chip structure on the external surface of the multilayer board
A mounting structure for a multilayer board in which components are mounted face-down, wherein an IC component is directly flip-chip bonded to a metal layer filling a via hole on the surface of the multilayer board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130310A JPH0426199A (en) | 1990-05-22 | 1990-05-22 | Mounting structure of multilayer board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130310A JPH0426199A (en) | 1990-05-22 | 1990-05-22 | Mounting structure of multilayer board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0426199A true JPH0426199A (en) | 1992-01-29 |
Family
ID=15031265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2130310A Pending JPH0426199A (en) | 1990-05-22 | 1990-05-22 | Mounting structure of multilayer board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0426199A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511306A (en) * | 1994-04-05 | 1996-04-30 | Compaq Computer Corporation | Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process |
| US5822856A (en) * | 1996-06-28 | 1998-10-20 | International Business Machines Corporation | Manufacturing circuit board assemblies having filled vias |
-
1990
- 1990-05-22 JP JP2130310A patent/JPH0426199A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511306A (en) * | 1994-04-05 | 1996-04-30 | Compaq Computer Corporation | Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process |
| US5822856A (en) * | 1996-06-28 | 1998-10-20 | International Business Machines Corporation | Manufacturing circuit board assemblies having filled vias |
| US6127025A (en) * | 1996-06-28 | 2000-10-03 | International Business Machines Corporation | Circuit board with wiring sealing filled holes |
| US6138350A (en) * | 1996-06-28 | 2000-10-31 | International Business Machines Corporation | Process for manufacturing a circuit board with filled holes |
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