JPH04259986A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH04259986A JPH04259986A JP3021189A JP2118991A JPH04259986A JP H04259986 A JPH04259986 A JP H04259986A JP 3021189 A JP3021189 A JP 3021189A JP 2118991 A JP2118991 A JP 2118991A JP H04259986 A JPH04259986 A JP H04259986A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- ring oscillator
- external power
- voltage
- vcc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000010355 oscillation Effects 0.000 claims abstract description 14
- 230000014759 maintenance of location Effects 0.000 claims description 33
- 230000004044 response Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
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Abstract
Description
【０００１】0001
【産業上の利用分野】この発明はＤＲＡＭに必要な記憶
保持動作の周期を設定する周期設定回路に関するもので
ある。近年のＤＲＡＭでは外部からのクロック信号を必
要とすることなく、内部回路で記憶保持動作の周期を設
定するセルフ−リフレッシュモードを備えている。この
セルフ−リフレッシュモードでは記憶保持動作の周期を
電源電圧あるいは周囲温度等に関わらず一定とするか、
あるいは記憶セルのデータ保持能力が高い場合すなわち
電源電圧が高い場合には記憶保持動作の周期を長くする
とともに、記憶セルのデータ保持能力が低い場合すなわ
ち電源電圧が低い場合には記憶保持動作の周期を短くす
る必要がある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cycle setting circuit for setting the cycle of memory retention operations necessary for a DRAM. Recent DRAMs are equipped with a self-refresh mode in which the cycle of memory retention operation is set by an internal circuit without requiring an external clock signal. In this self-refresh mode, the period of memory retention operation is constant regardless of the power supply voltage or ambient temperature, etc.
Alternatively, if the data retention capacity of the memory cell is high, that is, the power supply voltage is high, the cycle of the memory retention operation is lengthened, and if the data retention capacity of the memory cell is low, that is, the power supply voltage is low, the cycle of the memory retention operation is lengthened. needs to be shortened.
【０００２】0002
【従来の技術】セルフ−リフレッシュモードを備えた従
来のＤＲＡＭにおける記憶保持動作の周期設定回路を図
６に従って説明すると、奇数段のインバータ回路１を直
列に接続して構成したリングオシレータ２は外部電源Ｖ
ｃｃの供給に基づいて所定の周波数で発振し、そのリン
グオシレータ２の出力信号は例えばｎビットのカウンタ
３に出力される。そして、カウンタ３はリングオシレー
タ２から出力されるパルス信号をカウントし、所定数の
パルス信号をカウントすると記憶保持動作を行うための
動作制御信号ΦＲ を出力し、その動作制御信号ΦＲ
に基づいて多数の記憶セルの格納データが順次リフレッ
シュされる。2. Description of the Related Art A cycle setting circuit for a memory retention operation in a conventional DRAM with a self-refresh mode will be explained with reference to FIG. V
The ring oscillator 2 oscillates at a predetermined frequency based on the supply of cc, and the output signal of the ring oscillator 2 is output to, for example, an n-bit counter 3. The counter 3 counts the pulse signals output from the ring oscillator 2, and when a predetermined number of pulse signals are counted, outputs an operation control signal ΦR for performing a memory retention operation, and outputs the operation control signal ΦR.
Data stored in a large number of memory cells is sequentially refreshed based on the data.
【０００３】0003
【発明が解決しようとする課題】上記のような周期設定
回路では外部電源Ｖｃｃの電圧変動に基づいてその発振
周波数が変化し、図７に示すように同電源電圧が上昇し
た場合には発振周波数が上がり、低下した場合には発振
周波数が下がる。この結果、外部電源Ｖｃｃの電圧が上
昇すると前記記憶保持動作の周期は短くなり、外部電源
Ｖｃｃの電圧が下降すると記憶保持動作の周期は長くな
る。[Problems to be Solved by the Invention] In the above-described period setting circuit, the oscillation frequency changes based on the voltage fluctuation of the external power supply Vcc, and as shown in FIG. 7, when the power supply voltage increases, the oscillation frequency changes. increases, and if it decreases, the oscillation frequency decreases. As a result, when the voltage of the external power supply Vcc increases, the cycle of the memory retention operation becomes shorter, and when the voltage of the external power supply Vcc decreases, the cycle of the memory retention operation becomes longer.
【０００４】一方、外部電源Ｖｃｃが高い状態で各記憶
セルにデータが書き込まれると、各記憶セルにおいてデ
ータ保持能力が向上するため記憶保持動作の周期は長く
てもよく、外部電源Ｖｃｃが低い状態で各記憶セルにデ
ータが書き込まれると、各記憶セルにおいてデータ保持
能力が低下するため記憶保持動作の周期を短くする必要
がある。On the other hand, when data is written to each memory cell while the external power supply Vcc is high, the data retention capacity of each memory cell improves, so the period of the memory retention operation may be long, and when the external power supply Vcc is low, When data is written into each memory cell, the data retention capacity of each memory cell decreases, so it is necessary to shorten the period of memory retention operation.
【０００５】従って、上記のような周期設定回路では特
定の外部電源電圧で設定された記憶保持動作の周期に対
し外部電源Ｖｃｃの電源電圧が低下して記憶保持動作の
周期を短くする必要があるときには反対にその周期が長
くなり、外部電源Ｖｃｃの電源電圧が上昇して記憶保持
動作の周期が長くてもよい場合にはその周期が反対に短
くなってしまうという問題点がある。Therefore, in the above-described cycle setting circuit, it is necessary to reduce the power supply voltage of the external power supply Vcc and shorten the cycle of the memory retention operation with respect to the cycle of the memory retention operation set with a specific external power supply voltage. On the contrary, sometimes the cycle becomes longer, and when the power supply voltage of the external power supply Vcc increases and the cycle of the memory retention operation can be long, there is a problem that the cycle becomes shorter.
【０００６】この発明の目的は、外部電源の変動にとも
なう記憶セルのデータ保持能力の変動に対応した記憶保
持動作の周期を自動的に設定し得る周期設定回路を備え
た半導体記憶装置を提供することにある。An object of the present invention is to provide a semiconductor memory device equipped with a cycle setting circuit that can automatically set the cycle of memory retention operation in response to variations in the data retention capacity of memory cells due to variations in external power supply. There is a particular thing.
【０００７】[0007]
【課題を解決するための手段】図１は第一及び第三の発
明の原理説明図である。すなわち、第一の発明では外部
電源Ｖｃｃの電圧変動に対し逆方向に変動するリングオ
シレータ電源Ｖｏｓｃ を電源回路５から前記リングオ
シレータ２に供給し、そのリングオシレータ電源Ｖｏｓ
ｃ により発振するリングオシレータ２の発振周波数に
基づく周期で記憶セルに対し記憶保持動作を行う。[Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principles of the first and third inventions. That is, in the first invention, the ring oscillator power supply Vosc, which fluctuates in the opposite direction to the voltage fluctuation of the external power supply Vcc, is supplied from the power supply circuit 5 to the ring oscillator 2, and the ring oscillator power supply Vosc is supplied from the power supply circuit 5 to the ring oscillator 2.
A memory holding operation is performed on the memory cell at a period based on the oscillation frequency of the ring oscillator 2 oscillated by c.
【０００８】また、図２に示す第二の発明ではしきい値
の異なる複数のトランジスタＴｒ１〜Ｔｒ４のゲートに
前記外部電源Ｖｃｃの変動にともなって変動する基準電
圧ＶＦ を入力し、該基準電圧ＶＦ の変動にともなっ
て順次オン・オフ動作する該トランジスタＴｒ１〜Ｔｒ
４の動作に基づいて該外部電源Ｖｃｃと前記リングオシ
レータ２との間に並列に接続された抵抗Ｒ７〜Ｒ１１の
合成抵抗値を変更することにより該外部電源Ｖｃｃの電
圧変動に対し逆方向に変動する前記リングオシレータ電
源Ｖｏｓｃ を形成する電源回路５を構成した。Further, in the second invention shown in FIG. 2, a reference voltage VF that fluctuates with fluctuations in the external power supply Vcc is input to the gates of a plurality of transistors Tr1 to Tr4 having different threshold values, and the reference voltage VF The transistors Tr1 to Tr sequentially turn on and off as the
By changing the combined resistance value of the resistors R7 to R11 connected in parallel between the external power source Vcc and the ring oscillator 2 based on the operation of step 4, the voltage changes in the opposite direction to the voltage fluctuation of the external power source Vcc. A power supply circuit 5 that forms the ring oscillator power supply Vosc was constructed.
【０００９】また、第三の発明では前記外部電源Ｖｃｃ
の電圧変動に関わらず一定の前記リングオシレータ電源
Ｖｏｓｃ を電源回路５から前記リングオシレータ２に
供給し、該リングオシレータ電源Ｖｏｓｃ により発振
するリングオシレータ２の発振周波数に基づく周期で記
憶セルに対し記憶保持動作を行う。Further, in the third invention, the external power supply Vcc
A constant ring oscillator power supply Vosc is supplied from the power supply circuit 5 to the ring oscillator 2 regardless of voltage fluctuations, and memory is held in the memory cell at a period based on the oscillation frequency of the ring oscillator 2 oscillated by the ring oscillator power supply Vosc. perform an action.
【００１０】0010
【作用】第一の発明では、外部電源Ｖｃｃの電圧が上昇
して記憶セルのデータ保持能力が高くなるとリングオシ
レータ２の発振周波数が低下して記憶保持動作の周期は
長くなり、外部電源Ｖｃｃの電圧が下降して記憶セルの
データ保持能力が低くなるとリングオシレータ２の発振
周波数が上昇して記憶保持動作の周期は短くなる。[Operation] In the first invention, when the voltage of the external power supply Vcc rises and the data retention capacity of the memory cell increases, the oscillation frequency of the ring oscillator 2 decreases and the period of the memory retention operation becomes longer. When the voltage decreases and the data retention ability of the memory cell decreases, the oscillation frequency of the ring oscillator 2 increases and the period of the memory retention operation becomes shorter.
【００１１】また、第三の発明では外部電源Ｖｃｃの変
動に関わらずリングオシレータ２の発振周波数は一定と
なって記憶保持動作の周期は一定となる。Furthermore, in the third aspect of the invention, the oscillation frequency of the ring oscillator 2 remains constant regardless of fluctuations in the external power supply Vcc, and the period of the memory holding operation remains constant.
【００１２】0012
【実施例】以下、この発明を具体化した一実施例を図２
及び図３に従って説明する。なお、前記従来例と同一構
成部分は同一符号を付してその説明を省略する。この実
施例の周期設定回路は図２に示すように例えば４つのＮ
チャネルＭＯＳトランジスタＴｒ１〜Ｔｒ４のドレイン
にはそれぞれ抵抗Ｒ１〜Ｒ４を介して外部電源Ｖｃｃが
供給され、ソースはグランドＧに接続されている。そし
て、各トランジスタＴｒ１〜Ｔｒ４のしきい値Ｖｔｈ１
〜Ｖｔｈ４ はＶｔｈ１ ＜Ｖｔｈ２ ＜Ｖｔｈ３
＜Ｖｔｈ４ の関係となるように設定されている。[Example] An example embodying this invention is shown below in Figure 2.
and will be explained according to FIG. Incidentally, the same components as those of the conventional example are given the same reference numerals, and the explanation thereof will be omitted. As shown in FIG. 2, the period setting circuit of this embodiment has, for example, four N
The drains of the channel MOS transistors Tr1 to Tr4 are supplied with an external power supply Vcc via resistors R1 to R4, respectively, and the sources are connected to ground G. And threshold value Vth1 of each transistor Tr1 to Tr4
~Vth4 is Vth1 <Vth2 <Vth3
The relationship is set to be <Vth4.
【００１３】各トランジスタＴｒ１〜Ｔｒ４のゲートに
は抵抗Ｒ５を介して外部電源Ｖｃｃが供給されるととも
に抵抗Ｒ６を介してグランドＧに接続されている。従っ
て、トランジスタＴｒ１〜Ｔｒ４のゲートには外部電源
Ｖｃｃを抵抗Ｒ５，Ｒ６で分圧した基準電圧ＶＦ が入
力されている。
各トランジスタＴｒ１〜Ｔｒ４のドレインはそれぞれイ
ンバータ回路４を介してＰチャネルＭＯＳトランジスタ
Ｔｒ５〜Ｔｒ８のゲートに接続され、各トランジスタＴ
ｒ５〜Ｔｒ８のソースにはそれぞれ抵抗Ｒ７〜Ｒ１０を
介して外部電源Ｖｃｃが供給され、ドレインはリングオ
シレータ２を構成する各インバータ回路１の電源端子に
接続されてリングオシレータ電源Ｖｏｓｃ を供給して
いる。また、トランジスタＴｒ５〜Ｔｒ８及び抵抗Ｒ７
〜Ｒ１０に対し並列に抵抗Ｒ１１が接続されている。そ
して、リングオシレータ２の出力信号は前記カウンタ３
に出力されている。The gates of each of the transistors Tr1 to Tr4 are supplied with an external power supply Vcc via a resistor R5 and are connected to ground G via a resistor R6. Therefore, a reference voltage VF obtained by dividing the external power supply Vcc by resistors R5 and R6 is input to the gates of the transistors Tr1 to Tr4. The drains of each transistor Tr1 to Tr4 are connected to the gates of P channel MOS transistors Tr5 to Tr8 via an inverter circuit 4, respectively, and each transistor T
The external power supply Vcc is supplied to the sources of r5 to Tr8 through resistors R7 to R10, respectively, and the drains are connected to the power supply terminals of each inverter circuit 1 constituting the ring oscillator 2 to supply the ring oscillator power supply Vosc. . In addition, transistors Tr5 to Tr8 and resistor R7
A resistor R11 is connected in parallel to ~R10. Then, the output signal of the ring oscillator 2 is transmitted to the counter 3.
It is output to .
【００１４】さて、上記のような構成では外部電源Ｖｃ
ｃに基づく基準電圧ＶＦ が各トランジスタＴｒ１〜Ｔ
ｒ４のしきい値Ｖｔｈ１ 〜Ｖｔｈ４ より低いと、各
トランジスタＴｒ１〜Ｔｒ４はオフされてインバータ回
路４はＬレベルの信号を出力するため、トランジスタＴ
ｒ５〜Ｔｒ８がオンされる。従って、抵抗Ｒ７〜Ｒ１１
の合成抵抗に基づいてリングオシレータ２に外部電源Ｖ
ｃｃより低い電圧のリングオシレータ電源Ｖｏｓｃ が
供給される。Now, in the above configuration, the external power supply Vc
The reference voltage VF based on c is applied to each transistor Tr1 to T
When it is lower than the threshold value Vth1 to Vth4 of r4, each transistor Tr1 to Tr4 is turned off and the inverter circuit 4 outputs an L level signal.
r5 to Tr8 are turned on. Therefore, resistors R7 to R11
The external power supply V is applied to ring oscillator 2 based on the combined resistance of
A ring oscillator power supply Vosc having a voltage lower than cc is supplied.
【００１５】一方、図３に示すように外部電源Ｖｃｃの
電圧の上昇にともなって基準電圧ＶＦ が上昇してトラ
ンジスタＴｒ１〜Ｔｒ４のしきい値Ｖｔｈ１ 〜Ｖｔｈ
４ を超えると、各トランジスタＴｒ１〜Ｔｒ４は基準
電圧ＶＦ の上昇にともなって順次オンされ、これにと
もなってトランジスタＴｒ５〜Ｔｒ８が順次オフされて
抵抗Ｒ７〜Ｒ１０とリングオシレータ２の接続は順次切
断されるため、抵抗Ｒ７〜Ｒ１１の合成抵抗は順次増大
する。この結果、リングオシレータ電源Ｖｏｓｃ は外
部電源Ｖｃｃの電圧上昇にともなって下降するため、リ
ングオシレータ２の発振周波数が低下する。On the other hand, as shown in FIG. 3, as the voltage of the external power supply Vcc increases, the reference voltage VF increases and the threshold voltages Vth1 to Vth of the transistors Tr1 to Tr4 increase.
4, each of the transistors Tr1 to Tr4 is sequentially turned on as the reference voltage VF rises, and accordingly, the transistors Tr5 to Tr8 are sequentially turned off, and the connection between the resistors R7 to R10 and the ring oscillator 2 is sequentially disconnected. Therefore, the combined resistance of the resistors R7 to R11 increases sequentially. As a result, the ring oscillator power supply Vosc decreases as the voltage of the external power supply Vcc increases, so that the oscillation frequency of the ring oscillator 2 decreases.
【００１６】従って、この周期設定回路では外部電源Ｖ
ｃｃの変動に基づいて基準電圧ＶＦ がトランジスタＴ
ｒ１〜Ｔｒ４のしきい値Ｖｔｈ１ 〜Ｖｔｈ４ を含む
範囲で変動すると、外部電源Ｖｃｃの電圧上昇にともな
ってリングオシレータ２の発振周波数が４段階に低下し
て記憶保持動作のための周期を４段階で長くすることが
でき、反対に外部電源Ｖｃｃの電圧下降にともなってリ
ングオシレータ２の発振周波数が４段階に上昇して記憶
保持動作のための周期を４段階で短くすることができる
。この結果、常に記憶セルのデータ保持能力に見合った
記憶保持動作周期を自動的に設定することができる。Therefore, in this period setting circuit, the external power supply V
The reference voltage VF is set to the transistor T based on the variation of cc.
When the threshold values of r1 to Tr4 vary within a range including Vth1 to Vth4, the oscillation frequency of the ring oscillator 2 decreases in four steps as the voltage of the external power supply Vcc increases, and the cycle for memory retention operation changes in four steps. On the other hand, as the voltage of the external power supply Vcc decreases, the oscillation frequency of the ring oscillator 2 increases in four steps, and the period for memory retention operation can be shortened in four steps. As a result, it is possible to automatically set a memory retention operation cycle that always matches the data retention capacity of the memory cell.
【００１７】次に、この発明を具体化した第二の実施例
を図４に従って説明する。この実施例は外部電源Ｖｃｃ
を定電圧電源回路５により定電圧化してリングオシレー
タ２にリングオシレータ電源Ｖｏｓｃ として供給した
ものであり、定電圧電源回路５は公知の定電圧回路で構
成する。このような構成により図５に示すように外部電
源Ｖｃｃの電圧が上昇してもリングオシレータ電源Ｖｏ
ｓｃ は一定となるため、記憶保持動作の周期は一定に
保つことができる。Next, a second embodiment embodying the present invention will be described with reference to FIG. In this embodiment, the external power supply Vcc
is made into a constant voltage by a constant voltage power supply circuit 5 and supplied to the ring oscillator 2 as a ring oscillator power supply Vosc, and the constant voltage power supply circuit 5 is constituted by a known constant voltage circuit. With this configuration, as shown in FIG. 5, even if the voltage of the external power supply Vcc increases, the ring oscillator power supply Vo
Since sc is constant, the period of the memory retention operation can be kept constant.
【００１８】[0018]
【発明の効果】以上詳述したように、この発明は外部電
源の電圧変動にともなう記憶セルのデータ保持能力の変
動に対応した記憶保持動作の周期を自動的に設定し得る
半導体記憶装置を提供することができる優れた効果を発
揮する。As described in detail above, the present invention provides a semiconductor memory device that can automatically set the period of memory retention operation in response to variations in the data retention capacity of memory cells due to variations in the voltage of an external power supply. It can exhibit excellent effects.
【図１】本発明の原理説明図である。FIG. 1 is a diagram explaining the principle of the present invention.
【図２】本発明の第一の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a first embodiment of the present invention.
【図３】第一の実施例の動作特性を示す特性図である。FIG. 3 is a characteristic diagram showing the operating characteristics of the first embodiment.
【図４】本発明の第二の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
【図５】第二の実施例の動作特性を示す特性図である。FIG. 5 is a characteristic diagram showing the operating characteristics of the second embodiment.
【図６】従来例を示す回路図である。FIG. 6 is a circuit diagram showing a conventional example.
【図７】従来例の動作特性を示す特性図である。FIG. 7 is a characteristic diagram showing the operating characteristics of a conventional example.
２ リングオシレータ ５ 電源回路 Ｖｃｃ 外部電源 Ｖｏｓｃ リングオシレータ電源 ＶＦ 基準電圧 Ｔｒ１〜Ｔｒ４ トランジスタ Ｒ７〜Ｒ１１ 抵抗 2 Ring oscillator 5 Power supply circuit Vcc External power supply Vosc ring oscillator power supply VF Reference voltage Tr1~Tr4 Transistor R7~R11 Resistance
Claims (3)
ングオシレータ（２）の発振周波数に基づく周期で記憶
セルに対し記憶保持動作を行う半導体記憶装置であって
、外部電源（Ｖｃｃ）の電圧変動に対し逆方向に変動す
るリングオシレータ電源（Ｖｏｓｃ ）を電源回路（５
）から前記リングオシレータ（２）に供給したことを特
徴とする半導体記憶装置。Claim 1: A semiconductor memory device that performs a memory retention operation on a memory cell at a period based on the oscillation frequency of a ring oscillator (2) that oscillates when power is supplied, the semiconductor memory device being capable of retaining memory in response to voltage fluctuations in an external power supply (Vcc). On the other hand, the ring oscillator power supply (Vosc) which fluctuates in the opposite direction is
) to the ring oscillator (2).
る複数のトランジスタ（Ｔｒ１〜Ｔｒ４）のゲートに前
記外部電源（Ｖｃｃ）の変動にともなって変動する基準
電圧（ＶＦ ）を入力し、該基準電圧（ＶＦ ）の変動
にともなって順次オン・オフ動作する該トランジスタ（
Ｔｒ１〜Ｔｒ４）により該外部電源（Ｖｃｃ）と前記リ
ングオシレータ（２）との間に並列に接続された抵抗（
Ｒ７〜Ｒ１１）の合成抵抗値を変更することにより該外
部電源（Ｖｃｃ）の電圧変動に対し逆方向に変動する前
記リングオシレータ電源（Ｖｏｓｃ ）を形成する請求
項１記載の半導体記憶装置。2. The power supply circuit (5) inputs a reference voltage (VF) that fluctuates with fluctuations in the external power supply (Vcc) to the gates of a plurality of transistors (Tr1 to Tr4) having different threshold values; The transistor (
resistors (Tr1 to Tr4) connected in parallel between the external power supply (Vcc) and the ring oscillator (2);
2. The semiconductor memory device according to claim 1, wherein the ring oscillator power supply (Vosc) fluctuates in a direction opposite to the voltage fluctuation of the external power supply (Vcc) by changing a combined resistance value of R7 to R11).
記リングオシレータ（２）の発振周波数に基づく周期で
記憶セルに対し記憶保持動作を行う半導体記憶装置であ
って、前記外部電源（Ｖｃｃ）の電圧変動に関わらず一
定の前記リングオシレータ電源（Ｖｏｓｃ ）を電源回
路（５）から前記リングオシレータ（２）に供給したこ
とを特徴とする請求項１記載の半導体記憶装置。3. A semiconductor memory device that performs a memory retention operation on a memory cell at a period based on the oscillation frequency of the ring oscillator (2) that oscillates when power is supplied, wherein the voltage of the external power supply (Vcc) 2. The semiconductor memory device according to claim 1, wherein the ring oscillator power (Vosc), which is constant regardless of fluctuations, is supplied from a power supply circuit (5) to the ring oscillator (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3021189A JPH04259986A (en) | 1991-02-14 | 1991-02-14 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3021189A JPH04259986A (en) | 1991-02-14 | 1991-02-14 | Semiconductor memory device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000004771A Division JP3300322B2 (en) | 1991-02-14 | 2000-01-13 | Semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04259986A true JPH04259986A (en) | 1992-09-16 |
Family
ID=12048009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3021189A Pending JPH04259986A (en) | 1991-02-14 | 1991-02-14 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04259986A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100768A (en) * | 1997-07-25 | 2000-08-08 | Nec Corporation | Ring oscillator generating pulse signal at constant pulse period under unstable power voltage |
| US6809605B2 (en) | 2002-01-10 | 2004-10-26 | Fujitsu Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
| US6947345B2 (en) | 2001-04-02 | 2005-09-20 | Nec Electronics Corporation | Semiconductor memory device |
| JP2007042223A (en) * | 2005-08-04 | 2007-02-15 | Sony Corp | Semiconductor memory device and storage circuit |
| WO2008018276A1 (en) * | 2006-08-11 | 2008-02-14 | Nec Corporation | Voltage controlled oscillator, frequency synthesizer and oscillating frequency control method |
-
1991
- 1991-02-14 JP JP3021189A patent/JPH04259986A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100768A (en) * | 1997-07-25 | 2000-08-08 | Nec Corporation | Ring oscillator generating pulse signal at constant pulse period under unstable power voltage |
| US6947345B2 (en) | 2001-04-02 | 2005-09-20 | Nec Electronics Corporation | Semiconductor memory device |
| US6809605B2 (en) | 2002-01-10 | 2004-10-26 | Fujitsu Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
| US7042300B2 (en) | 2002-01-10 | 2006-05-09 | Fujitsu Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
| US7239210B2 (en) | 2002-01-10 | 2007-07-03 | Fujitsu Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
| US7492232B2 (en) | 2002-01-10 | 2009-02-17 | Fujitsu Microelectronics Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
| JP2007042223A (en) * | 2005-08-04 | 2007-02-15 | Sony Corp | Semiconductor memory device and storage circuit |
| WO2008018276A1 (en) * | 2006-08-11 | 2008-02-14 | Nec Corporation | Voltage controlled oscillator, frequency synthesizer and oscillating frequency control method |
| JPWO2008018276A1 (en) * | 2006-08-11 | 2009-12-24 | 日本電気株式会社 | Voltage-controlled oscillator, frequency synthesizer, and oscillation frequency control method |
| US7940139B2 (en) | 2006-08-11 | 2011-05-10 | Nec Corporation | Voltage-controlled oscillator, frequency synthesizer, and oscillation frequency control method |
| JP4735870B2 (en) * | 2006-08-11 | 2011-07-27 | 日本電気株式会社 | Voltage-controlled oscillator, frequency synthesizer, and oscillation frequency control method |
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