JPH04258044A - In-equipment monitor system - Google Patents

In-equipment monitor system

Info

Publication number
JPH04258044A
JPH04258044A JP3019607A JP1960791A JPH04258044A JP H04258044 A JPH04258044 A JP H04258044A JP 3019607 A JP3019607 A JP 3019607A JP 1960791 A JP1960791 A JP 1960791A JP H04258044 A JPH04258044 A JP H04258044A
Authority
JP
Japan
Prior art keywords
circuit
path pattern
alarm
unit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3019607A
Other languages
Japanese (ja)
Inventor
Kiyohisa Yamada
山田 規容久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3019607A priority Critical patent/JPH04258044A/en
Publication of JPH04258044A publication Critical patent/JPH04258044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Maintenance And Management Of Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To attain in-equipment monitor without increasing the circuit scale even when number of monitor object circuits is increased. CONSTITUTION:The system is provided with a selection circuit 1 in which each output data of n-sets of monitor object circuits 4 is sequentially selected to extract a path pattern inserted in the data, the pattern is subject to n- multiplex in the unit of frames to output a multiplexed path pattern, an error detection circuit 2 checking an error of each path pattern of the multiplexed path pattern signal and an alarm circuit 3 protecting an error signal and outputting an alarm for each unit circuit.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、装置内監視方式に関し
、特に装置を構成する単位回路毎に障害を監視する場合
に使用される装置内監視方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device monitoring system, and more particularly to an in-device monitoring system used to monitor failures in each unit circuit constituting the device.

【0002】0002

【従来の技術】伝送装置等一般に通信装置においては、
運用中の装置が故障しそれにより回線障害となった場合
、特に迅速な故障復旧が強く求められる。回線障害に対
しては、システム的に冗長回路、或いはパイロット監視
等の対策がとられているが、完全な故障復旧には先ず故
障箇所の特定が重要である。この為に装置自身で自己の
故障診断を行う装置内監視方式が重要となる。
[Prior Art] In general communication devices such as transmission devices,
When a device in operation breaks down, resulting in a line failure, there is an especially strong need for quick failure recovery. Systematic measures such as redundant circuits and pilot monitoring have been taken to deal with line failures, but for complete failure recovery, it is important to first identify the failure location. For this reason, an in-device monitoring system in which the device itself performs its own failure diagnosis is important.

【0003】従来、この種装置内監視方式として、監視
対象となるパネル,或いはパネルの集合体等の単位回路
毎に、入力デ―タの空ビットにパスパタ―ンを挿入し、
その出力側のデ―タからこれを抽出し、誤りをチェック
することにより故障診断し、若し、誤りであれば更に保
護を行って後、警報を出力していた。この一連の動作を
行う監視回路は単位回路毎に設けられていた。
[0003] Conventionally, as an internal monitoring method of this type, a path pattern is inserted into empty bits of input data for each unit circuit of a panel to be monitored or a collection of panels, etc.
This was extracted from the data on the output side, and the failure was diagnosed by checking for errors, and if there was an error, further protection was performed and then an alarm was output. A monitoring circuit that performs this series of operations is provided for each unit circuit.

【0004】0004

【発明が解決しようとする課題】上述したように従来の
装置内監視回路は、監視対象の単位回路毎に監視回路を
要し、監視対象の単位回路の数が多くなるとその数だけ
監視回路が必要となり回路規模が多きくなる欠点がある
[Problems to be Solved by the Invention] As mentioned above, the conventional internal monitoring circuit requires a monitoring circuit for each unit circuit to be monitored, and as the number of unit circuits to be monitored increases, the number of monitoring circuits increases by the number of unit circuits to be monitored. This has the drawback of increasing the circuit scale.

【0005】[0005]

【課題を解決するための手段】本発明の装置内監視方式
は、装置を構成するn個の単位回路の各入力デ―タにパ
スパタ―ンを挿入しその各出力側で障害を監視する装置
内監視方式において、1フレ―ム毎に1からnまでの前
記単位回路の各出力デ―タを順次選択しその中に挿入さ
れた前記パスパタ―ンを抽出しこれを前記フレ―ム毎に
n多重し多重化パスパタ―ン信号として出力する選択回
路と、前記多重化パスパタ―ン信号の各パスパタ―ンの
誤りを検出し誤り信号を出力する誤り検出回路と、前記
誤り信号の保護を行い前記単位回路毎に警報を出力する
警報回路とを備え構成している。
[Means for Solving the Problems] The in-device monitoring method of the present invention is a device that inserts a path pattern into each input data of n unit circuits constituting the device and monitors failures on each output side. In the internal monitoring method, each output data of the unit circuit from 1 to n is selected in sequence for each frame, the path pattern inserted therein is extracted, and this is extracted for each frame. a selection circuit that multiplexes the signal and outputs it as a multiplexed path pattern signal, an error detection circuit that detects errors in each path pattern of the multiplexed path pattern signal and outputs an error signal, and protects the error signal. The unit circuit includes an alarm circuit that outputs an alarm for each unit circuit.

【0006】[0006]

【実施例】次に本発明の実施例につき図を参照し説明す
る。図1は実施例の構成を示すブロック図である。
Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment.

【0007】監視対象回路4がn個あり、それぞれの出
力デ―タは選択回路1に入力されている。監視対象回路
4の入力デ―タは、例えばフレ―ム構成の多重信号でそ
のデ―ダ毎にパスパタ―ンが挿入されている。このパス
パタ―ンは通常4〜8ビットの任意のパタ―ンで空ビッ
トを利用し挿入されている。
There are n monitoring target circuits 4, and the output data of each circuit is input to the selection circuit 1. The input data to the circuit to be monitored 4 is, for example, a frame-structured multiplexed signal in which a path pattern is inserted for each data. This path pattern is usually an arbitrary pattern of 4 to 8 bits and is inserted using empty bits.

【0008】選択回路1はn周期の制御パルスを出力す
るカウンタ12と、この制御パルスによって動作する選
択回路本体11とから構成されている。出力デ―タは選
択回路本体11に入り、出力デ―タ1〜nは順次選択さ
れて、その中に挿入されたパスパタ―ンが抽出される。 抽出されたパスパタ―ンはデ―タのフレ―ム毎にn多重
されて、次の誤り検出回路2へ出力される。
The selection circuit 1 is composed of a counter 12 that outputs n-cycle control pulses, and a selection circuit main body 11 that operates in response to the control pulses. The output data enters the selection circuit main body 11, output data 1 to n are sequentially selected, and the path pattern inserted therein is extracted. The extracted path pattern is multiplexed n times for each frame of data and is output to the next error detection circuit 2.

【0009】誤り検出回路2では、この多重化された出
力パスパタ―ン列を入力側のパスパタ―ンと照合して一
致不一致をチェックし、このチェック結果を次の警報回
路3へ出力する。警報回路3では不一致時の誤り信号を
受けた場合、その確認判断、即ち保護を行って後、監視
対象回路別に警報を出力する。
The error detection circuit 2 compares this multiplexed output path pattern string with the path pattern on the input side to check for coincidence, and outputs the check result to the next alarm circuit 3. When the alarm circuit 3 receives an error signal at the time of non-coincidence, it performs confirmation judgment, that is, protection, and then outputs an alarm for each circuit to be monitored.

【0010】0010

【発明の効果】以上説明したように本発明は、複数の監
視対象回路のパスパタ―ンを逐次選択抽出し多重化して
から、時分割でチェックするので、監視対象回路の数が
多くなっても回路規模を大きくせずに装置内監視を行え
る効果がある。
[Effects of the Invention] As explained above, the present invention sequentially selects and extracts the path patterns of a plurality of circuits to be monitored, multiplexes them, and then checks them in a time-sharing manner. This has the effect of being able to monitor the inside of the device without increasing the circuit scale.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の実施例の構成を示すブロック図である
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1    選択回路 2    誤り検出回路 3    警報回路 4    監視対象回路 1 Selection circuit 2 Error detection circuit 3 Alarm circuit 4 Monitored circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  装置を構成するn個の単位回路の各入
力デ―タにパスパタ―ンを挿入しその各出力側で障害を
監視する装置内監視方式において、1フレ―ム毎に1か
らnまでの前記単位回路の各出力デ―タを順次選択しそ
の中に挿入された前記パスパタ―ンを抽出しこれを前記
フレ―ム毎にn多重し多重化パスパタ―ン信号として出
力する選択回路と、前記多重化パスパタ―ン信号の各パ
スパタ―ンの誤りを検出し誤り信号を出力する誤り検出
回路と、前記誤り信号の保護を行い前記単位回路毎に警
報を出力する警報回路とを備え構成したことを特徴とす
る装置内監視方式。
Claim 1: In an in-device monitoring method that inserts a path pattern into each input data of n unit circuits constituting the device and monitors failures on each output side, A selection of sequentially selecting each output data of the unit circuits up to n, extracting the path pattern inserted therein, multiplexing it n every frame, and outputting it as a multiplexed path pattern signal. a circuit, an error detection circuit that detects errors in each path pattern of the multiplexed path pattern signal and outputs an error signal, and an alarm circuit that protects the error signal and outputs an alarm for each unit circuit. An in-device monitoring method characterized by a prepared configuration.
JP3019607A 1991-02-13 1991-02-13 In-equipment monitor system Pending JPH04258044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3019607A JPH04258044A (en) 1991-02-13 1991-02-13 In-equipment monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3019607A JPH04258044A (en) 1991-02-13 1991-02-13 In-equipment monitor system

Publications (1)

Publication Number Publication Date
JPH04258044A true JPH04258044A (en) 1992-09-14

Family

ID=12003884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3019607A Pending JPH04258044A (en) 1991-02-13 1991-02-13 In-equipment monitor system

Country Status (1)

Country Link
JP (1) JPH04258044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350554A (en) * 1993-06-11 1994-12-22 Nec Corp Monitor system inside device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350554A (en) * 1993-06-11 1994-12-22 Nec Corp Monitor system inside device

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