JPH0425155A - Multilayer circuit board and manufacture thereof - Google Patents
Multilayer circuit board and manufacture thereofInfo
- Publication number
- JPH0425155A JPH0425155A JP12973190A JP12973190A JPH0425155A JP H0425155 A JPH0425155 A JP H0425155A JP 12973190 A JP12973190 A JP 12973190A JP 12973190 A JP12973190 A JP 12973190A JP H0425155 A JPH0425155 A JP H0425155A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- polyimide layer
- hole
- lower conductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 claims abstract description 113
- 239000004642 Polyimide Substances 0.000 claims abstract description 62
- 229920001721 polyimide Polymers 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 51
- 239000011229 interlayer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 210000004916 vomit Anatomy 0.000 description 1
- 230000008673 vomiting Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
Description
【発明の詳細な説明】
〔概要〕
層間絶縁層にポリイミドを使用した多層回路基板、！１
１にポリイミド層を挟む下部！９体と上部導体との接続
部の構造とその製造方法に関し、該接続部における上部
導体のランＩ・を小形化することによって、導体パター
ンを高密度化せしめることを１．１的とし、
ポリイミド層の−にに形成した上部導体が該ポリイミド
層にあけた貫通孔の側壁に沿って該ポリイミド層の下に
形成した下部導体と接続する導体接続において、
該１部１通孔か該ポリイミド層の厚さ方向の中間で側方
に広がる平坦面を有する段付き形状であり、該下部導体
に接続する該−１−布導体の接続部のラン）・か該平坦
面に形成されてなることを特徴とする構成の多層回路基
板、
および、前記下部導体の形成された絶縁基板に第１のポ
リイミド層を被着し、
該下部導体の所定部が表呈する第１の貫通孔を該第１の
ポリイミド層に設け、
該下部導体の所定部および該第１のポリイミド層を覆う
第２のポリイミド層を被着し、該第１の貫通孔とその開
口部の周囲を表呈せしめる第２の貫通孔を該第２のポリ
イミド層に設け、該第１の貫通孔の側壁に沿って該下部
導体に接続し該第１の貫通孔の開口部周囲にランＩ・を
有する１−布導体を、該第２のポリイミド層の上に形成
することを特徴とする、
または、前記下部導体の形成された絶縁基板にポリイミ
ド層を被着し、
該下部導体に対向する凹所を該ポリイミド層に形成し、
該凹所の中心部に該下部導体の所定部を表ハ゛−せしめ
る貫通孔を形成し、
該貫通孔の側壁に沿って該下部導体に接続し該１′ｉ通
孔の開口部周囲にランドを有する上部導体を、該ポリイ
ミド層の］−に形成することを特徴とし構成する多層回
路基板の製造方法である。[Detailed Description of the Invention] [Summary] A multilayer circuit board using polyimide as an interlayer insulating layer! 1
The lower part sandwiching the polyimide layer in 1! Regarding the structure of the connection part between the 9 body and the upper conductor and its manufacturing method, the objective is to increase the density of the conductor pattern by miniaturizing the run I of the upper conductor in the connection part, In a conductor connection in which an upper conductor formed on the bottom of the layer is connected to a lower conductor formed under the polyimide layer along the side wall of a through hole drilled in the polyimide layer, the 1 part 1 through hole is connected to the lower conductor formed in the polyimide layer. It has a stepped shape with a flat surface that spreads laterally at the middle in the thickness direction, and is formed on the flat surface with a run of the connecting portion of the cloth conductor connected to the lower conductor. A multilayer circuit board having a structure characterized in that a first polyimide layer is applied to the insulating substrate on which the lower conductor is formed, and a first through hole in which a predetermined portion of the lower conductor is exposed is formed in the first polyimide layer. a second polyimide layer covering a predetermined portion of the lower conductor and the first polyimide layer, and exposing the first through hole and the periphery of the opening thereof; A through hole is provided in the second polyimide layer, and a fabric conductor is connected to the lower conductor along the side wall of the first through hole and has a run I around the opening of the first through hole. , characterized in that it is formed on the second polyimide layer, or a polyimide layer is applied to the insulating substrate on which the lower conductor is formed, and a recess facing the lower conductor is formed in the polyimide layer. A through hole is formed in the center of the recess to expose a predetermined portion of the lower conductor, and the opening of the 1'i through hole is connected to the lower conductor along the side wall of the through hole. This is a method of manufacturing a multilayer circuit board characterized by forming an upper conductor having a land around the polyimide layer.
［産業上の利用分野〕
本発明は、層間絶縁層にポリイミＩ’を使用した多層回
路基板、特にポリイミド層を挟む下部導体と上部導体と
の接続部の構造とその製造方法に関する。[Industrial Field of Application] The present invention relates to a multilayer circuit board using polyimide I' as an interlayer insulating layer, and particularly to a structure of a connecting portion between a lower conductor and an upper conductor sandwiching a polyimide layer, and a method for manufacturing the same.
第・１図は従来の多層回路基板における導体接続部を示
す断面図である。FIG. 1 is a sectional view showing a conductor connection portion in a conventional multilayer circuit board.
第、１図において、多層回路基板ｌは絶縁基板２の表面
に形成された下部導体３の」−に被着したボッイト層４
に貫通孔５を設け、ポリイミド層１１の−上に形成した
上部導体６の一部（バイアホール２８体） ６ａは１”
４通孔５の側壁に沿って下部導体３に接続し、十部導体
６の他の一部（ランド）６ｂは貫通孔５の開口部の周囲
に形成される。In FIG. 1, a multilayer circuit board 1 has a vomit layer 4 deposited on a lower conductor 3 formed on the surface of an insulating substrate 2.
A through hole 5 is provided in the upper conductor 6 (28 via holes) formed on top of the polyimide layer 11. 6a is 1"
The other part (land) 6b of the four-part conductor 6 is connected to the lower conductor 3 along the side wall of the four-through hole 5, and is formed around the opening of the through-hole 5.
一般に、」−布導体６のバイアホール導体６ａが被着す
る貫通孔５の側壁は４５°〜６０°の傾斜角度であり、
貫通孔５の底部径（下部導体３の表呈径）はポリイミド
層４の厚さと同程度である。そしてポリイト層４の厚さ
は、クロスオーバ配線の絶縁性を十分に確保するため配
線（下部導体３）の厚さの３倍程度を必要とし、さらに
大型電子計算機等に使用される高速回路において所定の
誘電率を確保するため、２０〜３０μｍに形成すること
がある。Generally, the side wall of the through hole 5 to which the via hole conductor 6a of the fabric conductor 6 is attached has an inclination angle of 45° to 60°,
The bottom diameter of the through hole 5 (the exposed diameter of the lower conductor 3) is approximately the same as the thickness of the polyimide layer 4. The thickness of the polyite layer 4 needs to be about three times the thickness of the wiring (lower conductor 3) in order to ensure sufficient insulation of the crossover wiring. In order to ensure a predetermined dielectric constant, it may be formed to have a thickness of 20 to 30 μm.
従って、例えばポリイミド層１１の厚さｔが約３０μｍ
のときランド径Ｂは１００μｍ程度となり、１１部導体
６との確実な接続を考慮した下部導体３の幅Ａは、貫通
孔５を形成する際の位置合わせ誤差を見込んで４０μｍ
以−１＝ （例えば６０μｍ）に設定される。Therefore, for example, the thickness t of the polyimide layer 11 is about 30 μm.
In this case, the land diameter B is approximately 100 μm, and the width A of the lower conductor 3, which takes into account the reliable connection with the conductor 6 of the 11th section, is 40 μm, taking into account the alignment error when forming the through hole 5.
-1 = (for example, 60 μm).
以上説明したように、従来の多層配線基板において、厚
さ３０μｍのポリイミド層４を挟んで下部導体３と−に
１部２０体６とを接続させたとき、ランド６ｂの径は１
００μｍ程度になることにより、下部導体３より広い面
積を必要とする。そのため、ランド６ｂによって上部導
体６の高密度化が妨げられるという問題点があった。As explained above, in the conventional multilayer wiring board, when the lower conductor 3 and - are connected to the 1 part 20 body 6 with the 30 μm thick polyimide layer 4 in between, the land 6b has a diameter of 1
Since it is about 0.00 μm, a larger area than the lower conductor 3 is required. Therefore, there is a problem in that the lands 6b prevent the upper conductor 6 from becoming denser.
上記問題点の除去を目的とした本発明の多層配線基板は
、その実施例を示す第１図によれば、ボリイミｌ’層１
３の」−に形成した」−電導体１５がポリイミド層１３
にあけた貫通孔１＝１の側壁に沿ってポリイミド層１３
の下に形成した下部導体１２と接続する導体接続におい
て、
貫通孔１４がボリイミｌ’層１３の厚さ方向の中間で側
方に広がる平坦面１＝Ｉａを有する段付き形状であり、
下部導体１２に接続する上部導体１５の接続部のランｌ
” Ｉ ５ ｃが平坦面１４ａに形成されてなることを
特徴とする構成である。According to FIG. 1 showing an embodiment of the multilayer wiring board of the present invention aimed at eliminating the above-mentioned problems, a polyimide l' layer 1
3, the electrical conductor 15 formed on the polyimide layer 13
A polyimide layer 13 is placed along the side wall of the through hole 1=1 drilled in the
In the conductor connection to the lower conductor 12 formed under the lower conductor, the through hole 14 has a stepped shape with a flat surface 1 = Ia that spreads laterally at the middle of the thickness direction of the polyimide layer 13, and the lower conductor Run l of the connection of the upper conductor 15 connecting to 12
This structure is characterized in that I 5 c is formed on the flat surface 14a.
さらに、本発明による多層配線基板の製造方法を示す第
２図および第３図によれば、
下部導体１２の形成された絶縁基板１１に第１のポリイ
ミド層１３ａを被着し、
下部導体１２の所定部が表呈する第１の貫通孔１（ｉａ
を第１のポリイミド層１３ａに設け、下部導体１２の所
定部および第１のボリイミｌ’層１３ａを覆う第２のポ
リイミド層１３ｂを被着し、第１の貫通イ旧６ａとその
開口部の周囲を表呈せしめる第２の貫通孔１６ｂを第２
のボリイミｌ’層１３ｂに設け、
第１の貫通孔１６ａの側壁に沿って下部導体１２に接続
し第１の貫°通孔１６ａの開口部周囲にランド１５ｃを
有する上部導体１５を、第２のポリイミド層＋３ｂの」
二に形成することを特徴とした多層回路基板の製造方法
、
および、下部導体１２の形成された絶縁基板１１にポリ
イミド層２１を被着し、
下部導体ｊ２に対向する凹所２２をポリイミド層２１に
形成し、
凹所２２の中心部に］パ部導体１２の所定部を表呈せし
める１′１通孔２３を形成し、
貫通孔２３の側壁に沿って下部導体１２に接続し貫通孔
２３の開口１部周囲にランｌ”１５ｃを有する上部導体
１５を、ボリイミｌ’層２１の」−に形成することを特
徴とした多層回路基板の製造方法である。Furthermore, according to FIGS. 2 and 3 showing the method for manufacturing a multilayer wiring board according to the present invention, a first polyimide layer 13a is applied to the insulating substrate 11 on which the lower conductor 12 is formed, and the lower conductor 12 is First through hole 1 (ia
is provided on the first polyimide layer 13a, and a second polyimide layer 13b covering a predetermined portion of the lower conductor 12 and the first polyimide layer 13a is deposited, and the first through hole 6a and its opening are covered. The second through hole 16b that exposes the surrounding area is
An upper conductor 15 is provided on the polyimide layer 13b of the first through hole 16a, is connected to the lower conductor 12 along the side wall of the first through hole 16a, and has a land 15c around the opening of the first through hole 16a. polyimide layer + 3b
A method for manufacturing a multilayer circuit board, characterized in that a polyimide layer 21 is applied to an insulating substrate 11 on which a lower conductor 12 is formed, and a recess 22 facing the lower conductor j2 is covered with the polyimide layer 21. A through hole 23 is formed in the center of the recess 22 to expose a predetermined portion of the conductor 12, and the through hole 23 is connected to the lower conductor 12 along the side wall of the through hole 23. This method of manufacturing a multilayer circuit board is characterized in that an upper conductor 15 having a run l'' 15c around an opening 1 of the polyimide layer 21 is formed on the upper conductor 15 having a run l'' 15c around the opening 1 of the polyimide layer l'.
−」−記手段によれば、下部導体に接続する」−電導体
接続部のランドを、従来技術より下部導体に接近せしめ
た構成およびそのための製造方法を提供したことにより
、ランド径を小さくすることができる。- According to the means described, the land diameter of the land is reduced by providing a configuration in which the land of the conductor connection portion is brought closer to the lower conductor than in the prior art and a manufacturing method therefor. be able to.
従って、上部導体の高密度化が可能となり、多層回路基
板の高集積化が実現される。Therefore, it is possible to increase the density of the upper conductor, and achieve high integration of the multilayer circuit board.
以−ドに、図面を用いて本発明による多層回路基板とそ
の製造方法について説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer circuit board and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による多層回路基板の層間導
体接続部を示す断面図、第２図は本発明の一実施例によ
る該層間導体接続部の製造工程の説明図、第３図は本発
明の他の実施例による該層間導体接続部の製造］１程の
説明図である。FIG. 1 is a sectional view showing an interlayer conductor connection portion of a multilayer circuit board according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the manufacturing process of the interlayer conductor connection portion according to an embodiment of the present invention, and FIG. FIG. 1 is an explanatory diagram of 1 of the manufacturing of the interlayer conductor connection portion according to another embodiment of the present invention.
第１図において、多層回路基板１０は絶縁基板１１の表
面に、例えばＣｒ／Ｃｕ／Ｃｒ構成の下部導体１２と、
下部より」一部で大きい漏斗状の段イτｊき貫通孔１４
のあけられた厚さ３０μｍのポリイミド層１３と、ポリ
イミド層１３の」二に例えばＣｒ／Ｃｕ／Ｃｒ構成て形
成した−」−電導体１５が形成されてなる。In FIG. 1, a multilayer circuit board 10 includes a lower conductor 12 having a Cr/Cu/Cr configuration, for example, on the surface of an insulating substrate 11.
A funnel-shaped stepped through hole 14 that is partially large from the bottom.
A polyimide layer 13 having a thickness of 30 .mu.m is formed with an opening, and a conductor 15 formed of, for example, Cr/Cu/Cr is formed on the second side of the polyimide layer 13.
下部導体１２の所定部を表呈せしめる貫通孔ｌ１１は、
ポリイミド層１３の厚さ方向の中央に側方へ広がる平坦
面＋４ａを有する段イ」きの漏斗状であり、上部導体１
５の一部１５ａは下部導体１２の所定部に積重し、他の
一部（バイアホール導体用５ｂは平坦面Ｈａより下部に
傾斜する貫通孔１４の側壁に被着し、さらに他の一部（
ランド月５０は平坦面１４ａに被着するようになる。The through hole l11 that exposes a predetermined portion of the lower conductor 12 is
The polyimide layer 13 has a stepped funnel shape with a flat surface +4a extending laterally at the center in the thickness direction of the polyimide layer 13, and the upper conductor 1
A part 15a of the conductor 5 is stacked on a predetermined part of the lower conductor 12, and the other part (5b for via hole conductor is attached to the side wall of the through hole 14 which is inclined downward from the flat surface Ha, and Department (
The land 50 comes to adhere to the flat surface 14a.
従って、ポリイミド層■３の厚さを３０７１ｍ、下部導
体１２の幅Ａを６０μｍ、Ｊ−電導体１５の一部１５ａ
の径を３０μｍ１貫通孔１４の側壁傾斜角度が４５°と
し、ボリイト層１３の厚さ１５μｍの位置に平坦面１４
ａを形成したとき、ランド径Ｂは約６０μｍにすること
ができる。Therefore, the thickness of the polyimide layer 3 is 3071 m, the width A of the lower conductor 12 is 60 μm, and the part 15a of the J-conductor 15 is
The diameter of the through hole 14 is 30 μm, and the side wall inclination angle of the through hole 14 is 45°.
When a is formed, the land diameter B can be about 60 μm.
さらに、平坦面１４ａがポリイミド層１３の厚さ１５μ
ｍの位置に形成されたとき、−１―部導体１５の一部１
５ａの径は１５μｍ程度にすることが可能であり、その
ことによって下部導体１２の幅Ａおよびランド径Ｂは５
０μｍ以下にすることが可能である。Further, the flat surface 14a is made of polyimide layer 13 having a thickness of 15 μm.
When formed at position m, part 1 of -1- part conductor 15
The diameter of 5a can be set to about 15 μm, thereby making the width A and land diameter B of the lower conductor 12 about 5 μm.
It is possible to reduce the thickness to 0 μm or less.
第２図（イ）において、絶縁基板１１の表面によく知ら
れた成膜技術およびエッヂンク技術により下部導体１２
を形成し、第２図（ロ）では絶縁基板Ｉ＋の表面に下部
導体１２を覆う第１の感光性ポリイミド層１３ａを被着
する。ポリイミド層１３ａの厚さは約１５μｍである。In FIG. 2(A), a lower conductor 12 is formed on the surface of an insulating substrate 11 by well-known film formation technology and edging technology.
In FIG. 2(b), a first photosensitive polyimide layer 13a covering the lower conductor 12 is deposited on the surface of the insulating substrate I+. The thickness of the polyimide layer 13a is about 15 μm.
第２図（ハ）において、ポリイミド層１３ａに貫通孔１
６ａを設けたのち、第２図（ニ）に示す如く、貫通イ旧
６ａを覆う第２の感光性ポリイミド層１３ｂを厚さ約１
５７１ｍに被着する。In FIG. 2(c), a through hole 1 is formed in the polyimide layer 13a.
6a, as shown in FIG.
Covers 571m.
しかるのち第２図（ホ）に示す如く、貫通孔１６ａの周
囲に平坦部１４ａを形成せしめる１１″通孔１６ｂをポ
リイミド層１３ａに設（プたのち、よく知られた成膜技
術およびエツヂンク技術により第２図（へ）に示す如（
、バイアホール導体１５ｂおよびランド１５Ｃを具え下
部導体１２に接続された上部導体１５を形れた成膜技術
およびエッチンク技術により下部導体１２を形成し、第
３図（ロ）では、下部導体１２を覆う非感光性ポリイミ
ド層２１を厚さ約３０μｍに被着する。Then, as shown in FIG. 2(e), an 11" through hole 16b is formed in the polyimide layer 13a to form a flat portion 14a around the through hole 16a. As shown in Figure 2 (f),
, the lower conductor 12 is formed using a film forming technique and an etching technique that form the upper conductor 15 which includes the via hole conductor 15b and the land 15C and which is connected to the lower conductor 12. In FIG. A covering non-photosensitive polyimide layer 21 is applied to a thickness of approximately 30 μm.
次いて、第３図（ハ）に示す如く下部導体１２にｉｔ向
し深さが約１５μｍの凹所２２を、等方性ドライエッチ
ンクまたはウェットエツチンクにより形成したのち、第
３図（ニ）に示す如く、凹所２２の中心部に貫通孔２３
を異方性ドライエッチンクまたはりアクディブイオンエ
ッチンクにて穿設し、貫通孔２３の周囲に平坦部１４ａ
を形成せしめると共に、下部導体１２の所定部を表呈さ
せる。Next, as shown in FIG. 3(C), a recess 22 having a depth of approximately 15 μm in the IT direction is formed in the lower conductor 12 by isotropic dry etching or wet etching, and then, as shown in FIG. ), there is a through hole 23 in the center of the recess 22.
is formed using anisotropic dry etching or active ion etching, and a flat portion 14a is formed around the through hole 23.
is formed, and a predetermined portion of the lower conductor 12 is exposed.
しかるのぢ、第３図（ホ）に示すように、下部導体Ｉ２
の所定部に積重する部分１５ａ、■’ｊ通孔２３の傾斜
部に被着するバイアホール導体１５ｂ１貫通孔２３の開
口の周囲に被着するランＩ” Ｉ ５ ｃを具えた上部
導体１５をポリイミド層２１の」−に形成する。However, as shown in Figure 3 (e), the lower conductor I2
an upper conductor 15 having a portion 15a stacked on a predetermined portion of the through hole 23, a via hole conductor 15b1 attached to an inclined portion of the through hole 23, and a run I''I5c attached around the opening of the through hole 23; is formed on the polyimide layer 21.
以上説明したように本発明によれば、下部導体に接続す
る上部導体接続部のランドを小型化し、そのため上部導
体の高密度化が可能となり、多層回路基板の高集積化を
実現し７４７だ効果がある。As explained above, according to the present invention, the land of the upper conductor connecting portion connected to the lower conductor is miniaturized, which makes it possible to increase the density of the upper conductor, and realizes high integration of the multilayer circuit board. There is.
第１図は本発明の一実施例による多層回路基板の層間導
体接続部、
第２図は本発明の一実施例により第１図に示す層間導体
接続部を製造する工程説明図、第３図は本発明の他の実
施例により第１図に示す層間導体接続部を製造する工（
）゛説明図、第１１図は従来の多層回路基板における層
間導体接続部、
である。、
図中において、
０は多層回路基板、
１は絶縁基板、
２は下部導体、
３、１３ａ、 １３ｂ、 ２１はポリイミド層、４、１
６ａ、 ２３は貫通孔、
４ａはポリイミド層中間の平坦面、
５は上部導体、
５ｃはランＩ・、
２２は凹所、
を示す。FIG. 1 is an interlayer conductor connection portion of a multilayer circuit board according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a process for manufacturing the interlayer conductor connection portion shown in FIG. 1 according to an embodiment of the present invention, and FIG. The following is a process for manufacturing the interlayer conductor connection shown in FIG. 1 according to another embodiment of the present invention.
11 is an explanatory diagram showing an interlayer conductor connection portion in a conventional multilayer circuit board. , In the figure, 0 is a multilayer circuit board, 1 is an insulating substrate, 2 is a lower conductor, 3, 13a, 13b, 21 is a polyimide layer, 4, 1
6a, 23 are through holes, 4a is a flat surface in the middle of the polyimide layer, 5 is an upper conductor, 5c is a run I, and 22 is a recess.
Claims (3)
上に形成した上部導体（１５）が該ポリイミド層（１３
、２１、１３ａと１３ｂ）にあけた貫通孔（１４、１６
ａ、２３）の側壁に沿って該ポリイミド層（１３、２１
、１３ａと１３ｂ）の下に形成した下部導体（１２）と
接続する導体接続において、該貫通孔（１４、１６ａ、
２３）が該ポリイミド層（１３、２１、１３ａと１３ｂ
）の厚さ方向の中間で側方に広がる平坦面（１４ａ）を
有する段付き形状であり、 該下部導体（１２）に接続する該上部導体（１５）の接
続部のランド（１５ｃ）が該平坦面（１４ａ）に形成さ
れてなることを特徴とする多層回路基板。(1) The upper conductor (15) formed on the polyimide layer (13, 21, 13a and 13b)
, 21, 13a and 13b) through holes (14, 16
a, 23) along the side walls of the polyimide layer (13, 21).
, 13a and 13b), the through holes (14, 16a,
23) is the polyimide layer (13, 21, 13a and 13b)
) has a stepped shape with a flat surface (14a) that spreads laterally in the middle of the thickness direction, and the land (15c) of the connection part of the upper conductor (15) connected to the lower conductor (12) is connected to the lower conductor (12). A multilayer circuit board characterized by being formed on a flat surface (14a).
１）に第１のポリイミド層（１３ａ）を被着し、 該下部導体（１２）の所定部が表呈する第１の貫通孔（
１６ａ）を該第１のポリイミド層（１３ａ）に設け、該
下部導体（１２）の所定部および該第１のポリイミド層
（１３ａ）を覆う第２のポリイミド層（１３ｂ）を被着
し、 該第１の貫通孔（１６ａ）とその開口部の周囲を表呈せ
しめる第２の貫通孔（１６ｂ）を該第２のポリイミド層
（１３ｂ）に設け、 該第１の貫通孔（１６ａ）の側壁に沿って該下部導体（
１２）に接続し該第１の貫通孔（１６ａ）の開口部周囲
にランド（１５ｃ）を有する上部導体（１５）を、該第
２のポリイミド層（１３ｂ）の上に形成することを特徴
とした多層回路基板の製造方法。(2) The insulating substrate (1) on which the lower conductor (12) is formed
1), a first polyimide layer (13a) is applied to the lower conductor (12), and a first through hole (13a) is formed in which a predetermined portion of the lower conductor (12) is exposed.
16a) on the first polyimide layer (13a), depositing a second polyimide layer (13b) covering a predetermined portion of the lower conductor (12) and the first polyimide layer (13a); A first through hole (16a) and a second through hole (16b) exposing the periphery of the opening thereof are provided in the second polyimide layer (13b), and a side wall of the first through hole (16a) is provided. along the lower conductor (
12) and having a land (15c) around the opening of the first through hole (16a) is formed on the second polyimide layer (13b). A method for manufacturing a multilayer circuit board.
１）にポリイミド層（２１）を被着し、 該下部導体（１２）に対向する凹所（２２）を該ポリイ
ミド層（２１）に形成し、 該凹所（２２）の中心部に該下部導体（１２）の所定部
を表呈せしめる貫通孔（２３）を形成し、 該貫通孔（２３）の側壁に沿って該下部導体（１２）に
接続し該貫通孔（２３）の開口部周囲にランド（１５ｃ
）を有する上部導体（１５）を、該ポリイミド層（２１
）の上に形成することを特徴とした多層回路基板の製造
方法。(3) The insulating substrate (1) on which the lower conductor (12) is formed
A polyimide layer (21) is applied to 1), a recess (22) facing the lower conductor (12) is formed in the polyimide layer (21), and the lower conductor is placed in the center of the recess (22). A through hole (23) is formed that exposes a predetermined portion of the conductor (12), and is connected to the lower conductor (12) along the side wall of the through hole (23) and connected to the opening of the through hole (23). niland (15c
) with the polyimide layer (21
) A method for producing a multilayer circuit board, characterized by forming the circuit board on the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12973190A JPH0425155A (en) | 1990-05-18 | 1990-05-18 | Multilayer circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12973190A JPH0425155A (en) | 1990-05-18 | 1990-05-18 | Multilayer circuit board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425155A true JPH0425155A (en) | 1992-01-28 |
Family
ID=15016809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12973190A Pending JPH0425155A (en) | 1990-05-18 | 1990-05-18 | Multilayer circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425155A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6828514B2 (en) | 2003-01-30 | 2004-12-07 | Endicott Interconnect Technologies, Inc. | High speed circuit board and method for fabrication |
| US6894228B2 (en) | 2001-04-12 | 2005-05-17 | International Business Machines Corporation | High performance dense wire for printed circuit board |
| US6992896B2 (en) | 2003-01-30 | 2006-01-31 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
| US7023707B2 (en) | 2003-01-30 | 2006-04-04 | Endicott Interconnect Technologies, Inc. | Information handling system |
| US7161810B2 (en) | 2003-01-30 | 2007-01-09 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
| WO2015192526A1 (en) * | 2014-06-18 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
-
1990
- 1990-05-18 JP JP12973190A patent/JPH0425155A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894228B2 (en) | 2001-04-12 | 2005-05-17 | International Business Machines Corporation | High performance dense wire for printed circuit board |
| US6828514B2 (en) | 2003-01-30 | 2004-12-07 | Endicott Interconnect Technologies, Inc. | High speed circuit board and method for fabrication |
| US6992896B2 (en) | 2003-01-30 | 2006-01-31 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
| US7023707B2 (en) | 2003-01-30 | 2006-04-04 | Endicott Interconnect Technologies, Inc. | Information handling system |
| US7035113B2 (en) | 2003-01-30 | 2006-04-25 | Endicott Interconnect Technologies, Inc. | Multi-chip electronic package having laminate carrier and method of making same |
| US7152319B2 (en) | 2003-01-30 | 2006-12-26 | Endicott Interconnect Technologies, Inc. | Method of making high speed circuit board |
| US7161810B2 (en) | 2003-01-30 | 2007-01-09 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
| US7665207B2 (en) | 2003-01-30 | 2010-02-23 | Endicott Interconnect Technologies, Inc. | Method of making a multi-chip electronic package having laminate carrier |
| WO2015192526A1 (en) * | 2014-06-18 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
| US9966389B2 (en) | 2014-06-18 | 2018-05-08 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and display device |
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