JPH0424878B2 - - Google Patents
Info
- Publication number
- JPH0424878B2 JPH0424878B2 JP58151405A JP15140583A JPH0424878B2 JP H0424878 B2 JPH0424878 B2 JP H0424878B2 JP 58151405 A JP58151405 A JP 58151405A JP 15140583 A JP15140583 A JP 15140583A JP H0424878 B2 JPH0424878 B2 JP H0424878B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- type
- silicon
- type semiconductor
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 69
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 12
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 229910001887 tin oxide Inorganic materials 0.000 claims description 6
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 15
- 230000006866 deterioration Effects 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000004770 highest occupied molecular orbital Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Description
【発明の詳細な説明】
この発明はPI、NIまたはPIN接合を少なくと
も１つ有する光電変換装置（以下PVCという）
における透光性導電膜とＰまたはＮ型の非単結晶
半導体との界面即ち電極近傍の構造に関するもの
である。[Detailed Description of the Invention] This invention relates to a photoelectric conversion device (hereinafter referred to as PVC) having at least one PI, NI or PIN junction.
This relates to the structure at the interface between the transparent conductive film and the P or N type non-single crystal semiconductor, that is, near the electrode.
従来、これら光電変換半導体装置においてはＰ
またはＮ型のアモルフアス珪素上にアルミニユー
ムを真空蒸着方法で形成することが知られてい
た。しかしかかるアモルフアス珪素とアルミニユ
ームとの電極を100〜150℃で加熱処理を50時間位
行うと、アルミニユームが半導体中にマイグレイ
ト（異常拡散）して、電気的劣化をおこしてしま
う。このため、PIまたはNI接合において、この
アルミニユームがきわめて深くPIまたNI接合に
至り、接合特性を変質させてしまつていた。 Conventionally, in these photoelectric conversion semiconductor devices, P
Alternatively, it has been known to form aluminum on N-type amorphous silicon by vacuum deposition. However, when such an amorphous silicon and aluminum electrode is heat-treated at 100 to 150° C. for about 50 hours, the aluminum migrates (abnormal diffusion) into the semiconductor, causing electrical deterioration. For this reason, in the PI or NI junction, this aluminum reaches extremely deeply into the PI or NI junction, deteriorating the joint characteristics.
このため、ＰまたはＮ型半導体上にはこのよう
な金属を真空蒸着させるのではなく、酸化物導電
膜を形成することが試みられている。即ちＰ型ア
モルフアス珪素に対しては透光性導電酸化膜（以
下CTOという）の酸化スズを、またＮ型アモル
フアス珪素に対しては酸化インジユームを主成分
とするCTO即ちITO（酸化スズを10重量％以下添
加した酸化インジユーム）を密接させるというこ
とが試みられている。さらに必要に応じてこの
CTO上に反射性金属であるアルミニユームまた
は銀を形成させる方法が知られている。 For this reason, attempts have been made to form an oxide conductive film on a P- or N-type semiconductor, rather than vacuum-depositing such a metal. That is, for P-type amorphous silicon, tin oxide is used as a transparent conductive oxide film (hereinafter referred to as CTO), and for N-type amorphous silicon, CTO (ITO) whose main component is indium oxide (tin oxide 10% by weight) is used. Attempts have been made to bring the amount of indium oxide (indium oxide added up to % or less) into close contact with each other. Additionally, if necessary,
A method of forming reflective metals such as aluminum or silver on CTO is known.
かくのごとき構造とすると、150℃で作製して
も500時間までは電気特性の劣化を10％以内に防
ぐことができた。しかし500時間〜2000時間たつ
と、例えばPIN接合を有するPVCにおいて、初
期の効率が8.3％（1.05cm2）であつたのが、その
変化量において５％（500時間）〜25％（2000時
間）もの特性劣化（低下）がおこつてしまつた。 With this structure, even when fabricated at 150°C, the deterioration of electrical properties could be prevented to within 10% for up to 500 hours. However, after 500 to 2000 hours, for example, in PVC with PIN junction, the initial efficiency was 8.3% (1.05 cm 2 ), but the change in efficiency was 5% (500 hours) to 25% (2000 hours). ) property deterioration (deterioration) has occurred.
その原因を詳細に検討していくと、ＰまたはＮ
領域のアモルフアス半導体とCTOとの界面に酸
化珪素が薄く形成されてしまつていることが判明
した。特にＮ型アモルフアス珪素においては、
PSG（リンガラス）、Ｐ型アモルフアス珪素にお
いてはBSG（ホウ素ガラス）が形成される。これ
らガラスは最終的に絶縁性を有するものであり、
これらが特性劣化の原因であることが判明した。 When we examine the causes in detail, we find that P or N
It was found that a thin layer of silicon oxide had been formed at the interface between the amorphous semiconductor in the region and the CTO. Especially in N-type amorphous silicon,
BSG (boron glass) is formed in PSG (phosphorus glass) and P-type amorphous silicon. These glasses ultimately have insulating properties,
These were found to be the cause of characteristic deterioration.
アモルフアス珪素は化学的に結晶半導体に比べ
て不安定でありかつ反応しやすいため、これらの
劣化はアモルフアス半導体に特有の劣化特性であ
ることが判明した。 Since amorphous silicon is chemically more unstable and more reactive than crystalline semiconductors, these deteriorations were found to be unique to amorphous semiconductors.
また半導体としてアモルフアス珪素の代わりに
微結晶または多結晶の結晶性を有する半導体を用
いた場合、その成分中のアモルフアス分は約50％
となつているため、ITOとCTOとの反応をアモ
ルフアス珪素のみの場合に比べて約1/2とするこ
とができる。しかしこれでも本質的には劣化特性
を有することには変わりなく、さらに抜本的な解
決法が求められていた。 Furthermore, when a semiconductor with microcrystalline or polycrystalline crystallinity is used instead of amorphous silicon, the amorphous content in the component is approximately 50%.
Therefore, the reaction between ITO and CTO can be reduced to about 1/2 compared to when only amorphous silicon is used. However, even with this, it still essentially has deterioration characteristics, and a more drastic solution was required.
本発明はかかる劣化の発生を防止して高信頼性
を有せしめることを目的とするものである。 The present invention aims to prevent the occurrence of such deterioration and provide high reliability.
本発明はかかる目的のため、Ｐ型半導体及びＮ
型半導体を有する半導体装置であり、前記Ｐ型半
導体及びＮ型半導体の各々が透光性導電膜と密接
した構造のものにおいて、前記Ｐ型半導体又はＮ
型半導体は珪素非単結晶半導体層とSixC1-x（０＜
Ｘ＜１）で示される炭化珪素半導体層との二層か
ら成るものであり、前記Ｐ型半導体を構成する炭
化珪素半導体層は酸化物透光性導電膜と密接され
ており、前記Ｎ型半導体を構成する炭化珪素半導
体層は酸化インジユームを主成分とする透光性導
電膜と密接されている構造としたものであり、つ
まりこの発明はＰまたはＮ型の導電型を有し、か
つ透光性をアモルフアス珪素に比べて大きく有す
る半導体と、この半導体に密接して導電性を有す
る透光性導電膜の電極とを密接させてオーム接触
を有せしめるに際し、この電極−半導体界面での
反応による絶縁物の発生を防ぐため、その間にア
モルフアス珪素よりも透光性を有し、前記半導体
の導電型と同一のＰまたＮ型の導電型を有する
SixC1-x（０＜Ｘ＜１）で示される炭化珪素を介在
せしめて電極と半導体界面での熱化学反応の発生
を防ぎ、その結果この炭化珪素が酸素に対しブロ
ツク（阻止）効果を有し、CTOを構成している
酸素が珪素中に拡散してPSG、BSGを作ること
を防ぐことができ、高信頼性の半導体装置が得ら
れるものである
SixC1-x（０＜Ｘ＜１）で示される炭化珪素半導
体は、特に、ｘ＝0.95〜0.8においてその酸素を
ブロツクする作用が十分機能し、かつその厚さも
トンネル電流を引き出す程度の100Å以下（代表
的には平均膜厚15〜40Åと推定される）の厚さで
十分のブロツク作用がある。その結果、例えば
PIN結合を有さない光電変換装置を150℃で保持
し、1000〜2000時間をへても、その劣化は０〜２
％（1000時間）ないし０〜３％（2000時間）と熱
劣化をまつたくなくすことができた。 For this purpose, the present invention provides a P-type semiconductor and an N-type semiconductor.
In a semiconductor device having a type semiconductor, in which each of the P-type semiconductor and the N-type semiconductor has a structure in close contact with a transparent conductive film, the P-type semiconductor or the N-type semiconductor
type semiconductor is a silicon non-single crystal semiconductor layer and Si x C 1-x (0<
The silicon carbide semiconductor layer is in close contact with the oxide transparent conductive film, and the silicon carbide semiconductor layer constituting the P-type semiconductor is in close contact with the N-type semiconductor. The silicon carbide semiconductor layer constituting the silicon carbide semiconductor layer has a structure in which it is in close contact with a transparent conductive film containing indium oxide as a main component. When a semiconductor, which has a higher conductivity than amorphous silicon, and an electrode of a transparent conductive film that has conductivity are brought into close contact with this semiconductor to form an ohmic contact, a reaction occurs at the electrode-semiconductor interface. In order to prevent the formation of insulators, the material has a higher translucency than amorphous silicon and has a conductivity type of P or N type, which is the same as the conductivity type of the semiconductor.
Silicon carbide represented by Si x C 1-x (0<X<1) is interposed to prevent thermochemical reactions from occurring at the interface between the electrode and the semiconductor, and as a result, this silicon carbide has a blocking effect against oxygen. Si x C 1-x (0 <X<1), the silicon carbide semiconductor exhibits a sufficient oxygen blocking effect especially when A film thickness of 15 to 40 Å (estimated to be 15 to 40 Å) has sufficient blocking effect. As a result, for example
Even if a photoelectric conversion device without PIN bonding is kept at 150℃ for 1000 to 2000 hours, its deterioration is 0 to 2.
% (1000 hours) to 0-3% (2000 hours), and thermal deterioration could be completely eliminated.
本発明においては、層に接する半導体は非単
結晶半導体であつて、特に微結晶または多結晶の
ＰまたはＮ型の珪素半導体を用いても良い。 In the present invention, the semiconductor in contact with the layer is a non-single crystal semiconductor, and in particular, a microcrystalline or polycrystalline P or N type silicon semiconductor may be used.
それはPIまたはNI接合においては、またはＮ
型半導体層がアモルフアス珪素においては、その
電気伝導度は10-7〜10-5（Ωcm）-1であり、かつそ
の活性化エネルギも0.3〜0.4eVと大きい。 In PI or NI junctions, it is
When the type semiconductor layer is amorphous silicon, its electrical conductivity is 10 -7 to 10 -5 (Ωcm) -1 and its activation energy is as large as 0.3 to 0.4 eV.
このため活性状態の真性または実質的に真性
（Ｐ型用ホウ素またはＮ型用リンが1017cm-3以下
である、または意図的にまたは価の不純物を
添加しない）の型半導体との接合の内部電界を
有せしめんとするには、かかるアモルフアス珪素
では不十分であり、さらにこのＰまたはＮ型半導
体を透光して光を型半導体に注入せんとする
時、この半導体層での光吸収損をより少なくする
ことが求められる。 For this reason, junctions with active intrinsic or substantially intrinsic (P-type boron or N-type phosphorus less than 10 17 cm -3 or no intentional or valent impurity addition) type semiconductors are possible. Such amorphous silicon is insufficient to provide an internal electric field, and furthermore, when trying to inject light into a type semiconductor by transmitting light through this P or N type semiconductor, light absorption in this semiconductor layer There is a need to minimize losses.
そこで微結晶または多結晶のＰまたはＮ型の珪
素半導体を用いたのである。この微結晶または多
結晶のＰまたはＮ型の珪素半導体は電気伝導度が
10-1〜102（Ωcm）-1を有し、さらに光吸収係数も
例えば500nｍにて１×105（Ωcm）-1とアモルフア
ス珪素が３×105（Ωcm）-1であるのに対して1/3減
少させることができるのである。 Therefore, a microcrystalline or polycrystalline P or N type silicon semiconductor was used. This microcrystalline or polycrystalline P or N type silicon semiconductor has a high electrical conductivity.
10 -1 to 10 2 (Ωcm) -1 , and the light absorption coefficient is 1 x 10 5 (Ωcm) -1 at 500 nm, for example, whereas amorphous silicon is 3 x 10 5 (Ωcm) -1 . However, it can be reduced by 1/3.
かかる微結晶または多結晶の珪素の粒径はそれ
ぞれ５〜200Å及び200〜2000Åである。 The grain size of such microcrystalline or polycrystalline silicon is 5-200 Å and 200-2000 Å, respectively.
以下に図面に従つて本発明を示す。 The present invention will be illustrated below with reference to the drawings.
実施例 １
第１図Ａは基板１、透光性絶縁基板１５を通つ
て光１０が照射されたPVCを示す。Embodiment 1 FIG. 1A shows a PVC irradiated with light 10 through a substrate 1 and a transparent insulating substrate 15.
図面において、ガラス基板１上に第１のCTO
２を形成した。図面ではこれをフツ素のごときハ
ロゲン元素が添加された酸化スズ（300〜2000Å）
またはITO（300〜1500Å）＋酸化スズ（200〜400
Å）の２層構造とした。さらに、このCTO２上
にＰ型のSixC1-x（０＜ｘ＜１例えばｘ＝0.8）を
プラズマ気相法（PCVD法）によりSiH4とCH4
で実施した。その際、B2H6を0.5濃度％添加して
200℃の温度、出力20Wにて形成させた。その平
均厚さは約100Åであつた。 In the drawing, the first CTO is placed on the glass substrate 1.
2 was formed. In the drawing, this is tin oxide (300-2000Å) to which a halogen element such as fluorine is added.
or ITO (300~1500Å) + tin oxide (200~400Å)
A) two-layer structure. Furthermore, P-type Si x C 1-x (0<x<1, e.g. x=0.8) is deposited on this CTO2 using a plasma vapor phase method (PCVD method) to form SiH 4 and CH 4
It was carried out in At that time, B 2 H 6 was added at a concentration of 0.5%.
It was formed at a temperature of 200°C and an output of 20W. Its average thickness was about 100 Å.
さらにこの上面に型非晶質または半非晶質珪
素をPCVD法、光CVD法、光プラズマ気相法ま
たはLT CVD法（低温気相法）（HOMO CVD法
ともいう）またはこれらを組み合わせた気相法に
より0.2〜0.8μ例えば0.5μの厚さに形成させた。こ
の時同時にホウ素を平均濃度が1017cm-3以下添加
し、かつ濃度勾配をＰ型側に大きくして設け、効
率の向上を図ることは有効であつた。またこの水
素およびハロゲン元素が添加された珪素半導体中
の酸素は少なくとも５×1019cm-3以下好ましくは
５×1018cm-3以下にし、酸素による光照射劣化を
防ぎ、かつ酸化珪素絶縁物の存在による電気的導
電性の低下を防いだ。 Furthermore, amorphous or semi-amorphous silicon is deposited on this upper surface using a PCVD method, optical CVD method, optical plasma vapor phase method, LT CVD (low temperature vapor phase method) (also referred to as HOMO CVD method), or a combination of these methods. It was formed to a thickness of 0.2 to 0.8μ, for example 0.5μ, by a phase method. At this time, it was effective to simultaneously add boron to an average concentration of 10 17 cm -3 or less and to increase the concentration gradient toward the P type side in order to improve the efficiency. Furthermore, the oxygen content in the silicon semiconductor to which hydrogen and halogen elements are added is at least 5×10 19 cm -3 or less, preferably 5×10 18 cm -3 or less, to prevent light irradiation deterioration caused by oxygen, and to prevent silicon oxide insulators from deteriorating due to oxygen. This prevented the decrease in electrical conductivity due to the presence of
次にＮ型の非単結晶半導体層５をPH3／SiH4
＝１％、SiH4／H2＝30％として、PCVD法によ
り10Wの出力で100〜300Å例えば200Åの厚さに
形成せしめた。するとこの場合は微結晶性を含む
Ｎ型珪素（水素が５〜15原子％添加されている）
が形成された。さらにこの上面にPH3／SiH4＝
１％、CH4／（SiH4＋CH4）＝５〜50％とし、
SixC1-x（例えばｘ＝0.95〜0.8）２１として作製
した。この膜厚は100Å以下例えば30Åとした。
さらにこの後、ITOを裏面電極１９として公知の
電子ビーム蒸着法により形成せしめた。 Next, the N-type non-single crystal semiconductor layer 5 is formed using PH 3 /SiH 4
= 1%, SiH 4 /H 2 = 30%, and was formed to a thickness of 100 to 300 Å, for example, 200 Å, by the PCVD method at an output of 10 W. In this case, N-type silicon containing microcrystallinity (with 5 to 15 atomic percent hydrogen added)
was formed. Furthermore, on this upper surface, PH 3 /SiH 4 =
1%, CH 4 / (SiH 4 + CH 4 ) = 5 to 50%,
SixC 1-x (for example, x=0.95 to 0.8)21 was prepared. The film thickness was set to 100 Å or less, for example, 30 Å.
Furthermore, after this, ITO was formed as a back electrode 19 by a known electron beam evaporation method.
これに対応したエネルギバンド図を第１図Ｂに
示す。 An energy band diagram corresponding to this is shown in FIG. 1B.
かかる構造において、AM1（100ｍＷ／cm2）に
て1.05cm2（3.5cm×３mm）において、8.91％（開放
電圧0.89V、短絡電流18ｍＡ／cm2、曲線因子0.55）
を得た。これを150℃で大気中に放置すると、
1000〜2000時間を経てその劣化は初期に比べて０
〜３％（1000時間）、また０〜５％（2000時間）
を試料数30にて得ることができ、その劣化は３％
以内で従来が20％を越えていたことに比べて実用
上きわめて著しい信頼性の向上であつた。 In this structure, 8.91% (open circuit voltage 0.89V, short circuit current 18mA/cm 2 , fill factor 0.55) at 1.05cm 2 (3.5cm x 3mm) at AM1 (100mW/cm 2 )
I got it. When this is left in the air at 150℃,
After 1000 to 2000 hours, the deterioration is 0 compared to the initial stage.
~3% (1000 hours) and 0~5% (2000 hours)
can be obtained with 30 samples, and the deterioration is 3%.
This is an extremely significant improvement in reliability in practice compared to the conventional method, which had a rate of less than 20%.
実施例 ２
この実施例は第１図Ａに対し、Ｎ型半導体上の
ITO７上にさらに反射性電極として銀（500〜
1000Å）およびこの上にアルミニユーム3000Åを
電子ビーム蒸着法により作製した。するとこの反
射性電極により600〜800nｍの長波長光を照射し
て型半導体層中に閉じ込めることができるた
め、初期変換効率は9.82％（開放電圧0.89V、短
絡電流19.3ｍＡ、曲線因子0.57）を得ることがで
きた。その信頼性特性に関しても、150℃、1000
時間放置の条件でも初期値に比べて３％以下の劣
化しかなかつた。Example 2 This example differs from FIG.
Silver (500 ~
1000 Å) and 3000 Å aluminum was fabricated thereon by electron beam evaporation. Then, this reflective electrode can irradiate long wavelength light of 600 to 800 nm and confine it in the mold semiconductor layer, so the initial conversion efficiency is 9.82% (open circuit voltage 0.89 V, short circuit current 19.3 mA, fill factor 0.57). I was able to get it. Regarding its reliability characteristics, 150℃, 1000℃
Even under the condition of being left for a long time, the deterioration was only 3% or less compared to the initial value.
本発明において、以上の実施例はＮ型非単結晶
半導体にITO等の酸化インジユームを主成分とす
る電極を作製した。しかしＰ型珪素半導体−Ｐ型
炭化珪素（SixC1-x ０＜ｘ＜１）半導体−酸化
スズのCTOによる電極構造を同時に作ることは
有効である。 In the present invention, in the above embodiments, an electrode containing indium oxide such as ITO as a main component was fabricated on an N-type non-single crystal semiconductor. However, it is effective to simultaneously produce an electrode structure using CTO of a P-type silicon semiconductor, a P-type silicon carbide (Si x C 1-x 0<x<1) semiconductor, and a tin oxide.
以上の説明のごとく、本発明は光電変換装置の
非単結晶半導体を用いる半導体装置における電極
構造において、型半導体に密接した電気伝導度
のよい結晶性の非単結晶半導体を形成し、さらに
その上面に化学的にきわめて安定なSixC1-x（０＜
ｘ＜１）の炭化珪素を設け、この結果非単結晶珪
素半導体とCTOとの反応による絶縁膜の形成を
防ぐことができ、高信頼性の半導体層を作ること
が可能となつた。 As described above, in an electrode structure of a semiconductor device using a non-single crystal semiconductor of a photoelectric conversion device, the present invention forms a crystalline non-single crystal semiconductor with good electrical conductivity in close contact with a type semiconductor, and Si x C 1-x (0<
By providing silicon carbide with x<1), it was possible to prevent the formation of an insulating film due to the reaction between the non-single crystal silicon semiconductor and CTO, and it became possible to create a highly reliable semiconductor layer.
第１図は光電変換装置に本発明を応用した場合
の縦断面図を示す。
FIG. 1 shows a longitudinal sectional view when the present invention is applied to a photoelectric conversion device.
Claims (1)
装置であり、前記Ｐ型半導体およびＮ型半導体の
各々が透光性導電膜と密接した構造のものにおい
て、前記Ｐ型半導体またはＮ型半導体は珪素非単
結晶半導体層とSixC1-x（０＜Ｘ＜１）で示される
炭化珪素半導体層との二層から成るものであり、
前記Ｐ型半導体を構成する炭化珪素半導体層は酸
化錫透光性導電膜と密接されており、前記Ｎ型半
導体を構成する炭化珪素半導体層は酸化インジユ
ームを主成分とする透光性導電膜と密接されてい
ることを特徴とする半導体装置。 ２ 特許請求の範囲第１項において珪素非単結晶
半導体層が微結晶性を有する珪素半導体であるこ
とを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device having a P-type semiconductor and an N-type semiconductor, in which each of the P-type semiconductor and the N-type semiconductor has a structure in close contact with a transparent conductive film, wherein the P-type semiconductor or The N-type semiconductor consists of two layers: a silicon non-single crystal semiconductor layer and a silicon carbide semiconductor layer represented by Si x C 1-x (0<X<1),
The silicon carbide semiconductor layer constituting the P-type semiconductor is in close contact with a transparent conductive film of tin oxide, and the silicon carbide semiconductor layer constituting the N-type semiconductor is in close contact with a transparent conductive film containing indium oxide as a main component. A semiconductor device characterized by being closely connected. 2. A semiconductor device according to claim 1, wherein the silicon non-single crystal semiconductor layer is a microcrystalline silicon semiconductor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151405A JPS6043869A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
| JP1274697A JPH0669096B2 (en) | 1983-08-19 | 1989-10-20 | Insulated gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151405A JPS6043869A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1274697A Division JPH0669096B2 (en) | 1983-08-19 | 1989-10-20 | Insulated gate type field effect transistor |
| JP1274696A Division JPH0340470A (en) | 1989-10-20 | 1989-10-20 | Insulated-gate field-effect transistor |
| JP3352883A Division JPH05267700A (en) | 1991-12-17 | 1991-12-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6043869A JPS6043869A (en) | 1985-03-08 |
| JPH0424878B2 true JPH0424878B2 (en) | 1992-04-28 |
Family
ID=15517867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58151405A Granted JPS6043869A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043869A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63245964A (en) * | 1987-03-31 | 1988-10-13 | Kanegafuchi Chem Ind Co Ltd | Laminated solar cell |
| DE69107101T2 (en) | 1990-02-06 | 1995-05-24 | Semiconductor Energy Lab | Method of making an oxide film. |
| JPH03278466A (en) * | 1990-03-27 | 1991-12-10 | Toshiba Corp | Thin film transistor and manufacture thereof |
| DE69120574T2 (en) * | 1990-03-27 | 1996-11-28 | Toshiba Kawasaki Kk | Ohmic contact thin film transistor |
| EP0459763B1 (en) * | 1990-05-29 | 1997-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistors |
| US5172485A (en) * | 1991-10-17 | 1992-12-22 | Mitutoyo Corporation | Precision linear measuring suspension system having sliding contact between the scale and the pick-off |
| JPH05267700A (en) * | 1991-12-17 | 1993-10-15 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| KR100291971B1 (en) | 1993-10-26 | 2001-10-24 | 야마자끼 순페이 | Substrate processing apparatus and method and thin film semiconductor device manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664476A (en) * | 1979-08-30 | 1981-06-01 | Plessey Overseas | Armophous silicon solar battery |
-
1983
- 1983-08-19 JP JP58151405A patent/JPS6043869A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664476A (en) * | 1979-08-30 | 1981-06-01 | Plessey Overseas | Armophous silicon solar battery |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6043869A (en) | 1985-03-08 |
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