JPH04245817A - Data reception circuit - Google Patents
Data reception circuitInfo
- Publication number
- JPH04245817A JPH04245817A JP3029023A JP2902391A JPH04245817A JP H04245817 A JPH04245817 A JP H04245817A JP 3029023 A JP3029023 A JP 3029023A JP 2902391 A JP2902391 A JP 2902391A JP H04245817 A JPH04245817 A JP H04245817A
- Authority
- JP
- Japan
- Prior art keywords
- level
- circuit
- transmission line
- differential amplifier
- balanced transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 47
- 238000001514 detection method Methods 0.000 claims description 15
- 230000010354 integration Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
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- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、擬似ＥＣＬレベルで伝
送されたデータを受信するデータ受信回路に関する。装
置間を平衡伝送路により接続し、データを平衡伝送する
システムが知られている。このようなシステムに於ける
データ受信回路は、平衡伝送路により伝送された平衡信
号によるデータを差動増幅器により受信検出するもので
あり、ＴＴＬ（トランジスタ・トランジスタ・ロジック
）回路により構成されるのが一般的である。更に高速で
データを伝送する必要がある場合は、高速動作が可能の
ＥＣＬ（エミッタ・カップルド・ロジック）回路により
構成される。このＥＣＬ回路は少なくとも２電源を必要
とするから、ＴＴＬ回路と同様に１電源で動作できる擬
似ＥＣＬ回路が用いられる場合がある。ＴＴＬレベルは
、例えば、ハイレベルを２．７Ｖ，ローレベルを０．５
Ｖとしたものであり、又ＥＣＬレベルは、例えば、ハイ
レベルを−０．８Ｖ，ローレベルを−１．８Ｖとしたも
のである。これに対して、擬似ＥＣＬレベルは、ＥＣＬ
レベルを約＋５Ｖシフトして、ハイレベルを＋４Ｖ，ロ
ーレベルを＋３Ｖとしたものである。このような擬似Ｅ
ＣＬ回路によるデータ受信回路に於いて簡単な構成で送
信側の電源断やケーブル抜けを検出できることが要望さ
れている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit that receives data transmitted at a pseudo ECL level. 2. Description of the Related Art A system is known in which devices are connected by a balanced transmission line and data is transmitted in a balanced manner. The data receiving circuit in such a system receives and detects data from a balanced signal transmitted through a balanced transmission line using a differential amplifier, and is composed of a TTL (transistor-transistor-logic) circuit. Common. If it is necessary to transmit data at even higher speeds, an ECL (emitter coupled logic) circuit capable of high speed operation is used. Since this ECL circuit requires at least two power supplies, a pseudo ECL circuit that can operate with one power supply like a TTL circuit is sometimes used. For example, the TTL level is 2.7V for high level and 0.5V for low level.
The ECL level is, for example, -0.8V for high level and -1.8V for low level. On the other hand, the pseudo-ECL level is
The level is shifted by approximately +5V, with the high level being +4V and the low level being +3V. Such a pseudo E
There is a demand for a data receiving circuit using a CL circuit to be able to detect power failure or cable disconnection on the transmitting side with a simple configuration.
【０００２】0002
【従来の技術】従来例の装置間でデータを伝送する場合
、例えば、図５に示す構成が知られている。同図に於い
て、Ａ，Ｂは中央処理装置，入出力装置，チャネル制御
装置等の各種の装置、３１は平衡伝送路、３２は差動増
幅器、３３は終端抵抗、３４，３５は接地抵抗、３７は
送信回路、３８，３９はコネクタ、４０はアンド回路、
４１は平衡伝送路、４２，４３，４４は抵抗、４５は送
信回路、４６は差動増幅器である。データは送信回路３
７から平衡信号として平衡伝送路３１により装置Ａから
装置Ｂへ伝送され、装置Ｂの受信回路を構成する差動増
幅器３２により受信される。2. Description of the Related Art When transmitting data between conventional devices, for example, the configuration shown in FIG. 5 is known. In the figure, A and B are various devices such as a central processing unit, input/output device, and channel control device, 31 is a balanced transmission line, 32 is a differential amplifier, 33 is a terminating resistor, and 34 and 35 are grounding resistors. , 37 is a transmitting circuit, 38 and 39 are connectors, 40 is an AND circuit,
41 is a balanced transmission line; 42, 43, and 44 are resistors; 45 is a transmission circuit; and 46 is a differential amplifier. Data is transmitted by circuit 3
7 as a balanced signal from the device A to the device B via the balanced transmission path 31, and received by the differential amplifier 32 that constitutes the receiving circuit of the device B.
【０００３】この送信回路３７を擬似ＥＣＬ回路構成と
すると、送信回路３７の出力端子側にプルダウン抵抗と
して接地抵抗３４，３５が接続され、受信回路の差動増
幅器３２の入力端子間に終端抵抗３３が接続され、前述
のように、＋４Ｖと＋３Ｖとによるハイレベルとローレ
ベルとの平衡信号によるデータが伝送される。この場合
に、送信回路３７の電源断，コネクタ３８，３９の抜け
，平衡伝送路３１の断線等により、差動増幅器３２の入
力断が生じても、誘導ノイズ等による差動信号が入力さ
れる場合があり、それによって、正規なデータではない
誤データが送出される。When this transmitting circuit 37 has a pseudo ECL circuit configuration, grounding resistors 34 and 35 are connected as pull-down resistors to the output terminal side of the transmitting circuit 37, and a terminating resistor 33 is connected between the input terminals of the differential amplifier 32 of the receiving circuit. are connected, and as described above, data is transmitted using a balanced signal of high level and low level of +4V and +3V. In this case, even if the input to the differential amplifier 32 is cut off due to power cut off of the transmitting circuit 37, disconnection of the connectors 38 and 39, breakage of the balanced transmission line 31, etc., a differential signal due to induced noise etc. is input. In some cases, incorrect data that is not legitimate data is sent.
【０００４】そこで、送信回路３７側の電源断，コネク
タ３８，３９抜け，平衡伝送路３１の断線等を検出でき
るように、ＴＴＬ回路構成の送信回路４５と平衡伝送路
４１と差動増幅器４６の構成が設けられ、送信回路４５
の入力を接地してローレベルとし、正常時は、その送信
回路４５の非反転出力端子がローレベルで電流が流れ込
み、反転出力端子がハイレベルで電流が流出するから、
差動増幅器４６の−端子に比較して＋端子のレベルが高
くなり、出力はハイレベルとなる。従って、アンド回路
４０を介して差動増幅器３２による受信データが出力さ
れる。電源断やコネクタ３８，３９抜けの場合、差動増
幅器４６の−端子に比較して＋端子のレベルが低くなる
から、出力はローレベルとなり、アンド回路４０は閉じ
られて差動増幅器３２の不確定出力信号の送出が阻止さ
れる。Therefore, in order to detect power failure on the transmitting circuit 37 side, disconnection of the connectors 38 and 39, disconnection of the balanced transmission line 31, etc., the transmitting circuit 45 of the TTL circuit configuration, the balanced transmission line 41, and the differential amplifier 46 are connected. A configuration is provided, and a transmitting circuit 45
The input of the transmitter circuit 45 is grounded and set to low level, and under normal conditions, the non-inverting output terminal of the transmitting circuit 45 is at low level and current flows in, and the inverting output terminal is at high level and current flows out.
The level of the + terminal of the differential amplifier 46 is higher than that of the - terminal, and the output becomes high level. Therefore, the data received by the differential amplifier 32 is outputted via the AND circuit 40. If the power is cut off or the connectors 38 and 39 are disconnected, the level of the + terminal of the differential amplifier 46 will be lower than that of the - terminal, so the output will be at a low level, and the AND circuit 40 will be closed and the differential amplifier 32 will be disconnected. Sending of a definitive output signal is prevented.
【０００５】図６は前述の擬似ＥＣＬ回路構成の送信回
路の要部を示し、Ｑ１〜Ｑ４はトランジスタ、Ｒ１，Ｒ
２は抵抗、ＩＮは送信データの入力端子、ＯＵＴ１，Ｏ
ＵＴ２は非反転出力端子及び反転出力端子、Ｖｒは基準
電圧を示す。入力端子ＩＮにハイレベルの信号が入力さ
れると、非反転出力端子ＯＵＴ１は約＋４Ｖ、反転出力
端子ＯＵＴ２は約＋３Ｖの出力電圧となる。従って、ハ
イレベルの出力の場合も又ローレベルの出力の場合も平
衡伝送路側に電流が流出することになる。FIG. 6 shows the main parts of the transmitting circuit having the above-mentioned pseudo-ECL circuit configuration, in which Q1 to Q4 are transistors, R1 and R
2 is a resistor, IN is an input terminal for transmission data, OUT1, O
UT2 indicates a non-inverting output terminal and an inverting output terminal, and Vr indicates a reference voltage. When a high level signal is input to the input terminal IN, the non-inverting output terminal OUT1 has an output voltage of about +4V, and the inverting output terminal OUT2 has an output voltage of about +3V. Therefore, both in the case of a high-level output and in the case of a low-level output, current flows to the balanced transmission line side.
【０００６】このような擬似ＥＣＬレベルのデータを受
信する受信回路は、例えば、図７に示すように、トラン
ジスタＱ５，Ｑ６と抵抗Ｒ３〜Ｒ１０と論理回路５１と
を有し、トランジスタＱ５，Ｑ６により差動増幅器３２
が構成されることになり、入力端子ＩＮ１，ＩＮ２と平
衡伝送路３１を介して送信回路の非反転出力端子ＯＵＴ
１と反転出力端子ＯＵＴ２とが接続される。送信側の電
源断やコネクタ３８，３９抜け等が生じると、入力端子
ＩＮ１，ＩＮ２の入力レベル差が零となり、ノイズ成分
による変動分のみとなり、その変動分を入力信号と見做
した出力信号が論理回路５１に加えられることになり、
出力端子ＯＵＴから誤ったデータが出力されることにな
る。このような欠点を防止する為に、図５に示すように
、検出用の構成が設けられている。[0006] For example, as shown in FIG. 7, a receiving circuit for receiving such pseudo-ECL level data has transistors Q5 and Q6, resistors R3 to R10, and a logic circuit 51. Differential amplifier 32
is configured, and the non-inverting output terminal OUT of the transmitting circuit is connected via the input terminals IN1 and IN2 and the balanced transmission line 31.
1 and the inverting output terminal OUT2 are connected. When power is cut off on the transmitting side or the connectors 38 and 39 are disconnected, the input level difference between the input terminals IN1 and IN2 becomes zero, and only the fluctuation due to the noise component remains, and the output signal that considers the fluctuation as the input signal is It will be added to the logic circuit 51,
Incorrect data will be output from the output terminal OUT. In order to prevent such drawbacks, a detection configuration is provided as shown in FIG.
【０００７】又ＴＴＬ回路構成の送信回路は、例えば、
非反転出力端子側は、図８に示すように、トランジスタ
Ｑ７，Ｑ８とダイオードＤ１と抵抗Ｒ１１とを有し、ト
ランジスタＱ７をオン、トランジスタＱ８をオフとする
と、出力端子ＯＵＴＴは抵抗Ｒ１１，トランジスタＱ７
，ダイオードＤ１による電圧降下により約＋３．５Ｖと
なり、電流ＩＨ が実線で示すように平衡伝送路に流出
する。又トランジスタＱ７をオフ、トランジスタＱ８を
オンとすると、出力端子ＯＵＴＴはトランジスタＱ８の
電圧降下分により約０．４Ｖとなり、電流ＩＬが点線で
示すように平衡伝送路から流入する。従って、図５に於
ける抵抗４２，４３，４４と、差動増幅器４６とにより
、送信側の電源断やコネクタ３８，３９抜け等を検出す
ることができる。[0007] Furthermore, the transmitting circuit having a TTL circuit configuration is, for example,
As shown in FIG. 8, the non-inverting output terminal side has transistors Q7 and Q8, a diode D1, and a resistor R11. When the transistor Q7 is turned on and the transistor Q8 is turned off, the output terminal OUTT is connected to the resistor R11 and the transistor Q7.
, the voltage drop due to the diode D1 becomes approximately +3.5V, and the current IH flows out to the balanced transmission line as shown by the solid line. Further, when the transistor Q7 is turned off and the transistor Q8 is turned on, the output terminal OUTT becomes approximately 0.4V due to the voltage drop of the transistor Q8, and the current IL flows from the balanced transmission line as shown by the dotted line. Therefore, by the resistors 42, 43, 44 and the differential amplifier 46 in FIG. 5, it is possible to detect power failure on the transmitting side, disconnection of the connectors 38, 39, etc.
【０００８】[0008]
【発明が解決しようとする課題】前述のように、ＥＣＬ
回路構成は高速動作が可能である利点があるが、ＥＣＬ
レベルで送信する為には、複数電源を必要とする欠点が
あり、従って、単一電源の例えば＋５Ｖ電源で駆動でき
る擬似ＥＣＬ回路構成が採用されている。その場合に、
図５に示すように、送信回路３７側の電源断，コネクタ
３８，３９抜け等を検出できないので、検出用の送信回
路４５，平衡伝送路４１，受信回路としての差動増幅器
４６を設けなければならず、それによって装置規模が大
きくなる欠点があった。本発明は、簡単な構成により擬
似ＥＣＬレベルで平衡伝送する場合の送信側の電源断及
びコネクタ抜けを容易に検出できるようにすることを目
的とする。[Problem to be solved by the invention] As mentioned above, ECL
The circuit configuration has the advantage of being able to operate at high speed, but ECL
In order to transmit the level, there is a drawback that multiple power supplies are required, and therefore, a pseudo ECL circuit configuration that can be driven by a single power supply, for example, +5V power supply is adopted. In that case,
As shown in FIG. 5, it is not possible to detect power failure on the transmitting circuit 37 side, disconnection of the connectors 38, 39, etc., so a transmitting circuit 45 for detection, a balanced transmission line 41, and a differential amplifier 46 as a receiving circuit must be provided. However, this has the drawback of increasing the size of the device. SUMMARY OF THE INVENTION An object of the present invention is to enable easy detection of power outage and connector disconnection on the transmitting side in the case of balanced transmission at a pseudo ECL level using a simple configuration.
【０００９】[0009]
【課題を解決するための手段】本発明のデータ受信回路
は、図１を参照して説明すると、コネクタ８，９を介し
て送信回路７と受信回路を構成する差動増幅器２とを平
衡伝送路１により接続し、この平衡伝送路１により擬似
ＥＣＬレベルで伝送されたデータを受信する受信回路に
於いて、差動増幅器２の入力端子間に終端抵抗３を接続
し、その差動増幅器２の各入力端子と接地との間に接地
抵抗４，５を接続し、平衡伝送路１の少なくとも何れか
一方の線のレベルが擬似ＥＣＬレベルより低いか否かを
検出するレベル検出部６を接続したものである。[Means for Solving the Problems] The data receiving circuit of the present invention will be described with reference to FIG. In a receiving circuit that receives data transmitted at a pseudo ECL level through this balanced transmission line 1, a terminating resistor 3 is connected between the input terminals of a differential amplifier 2, and the differential amplifier 2 Grounding resistors 4 and 5 are connected between each input terminal of the balanced transmission line 1 and the ground, and a level detection unit 6 is connected to detect whether the level of at least one line of the balanced transmission line 1 is lower than the pseudo ECL level. This is what I did.
【００１０】又レベル検出部６は、平衡伝送路１の少な
くとも何れか一方の電位が接地レベルになった時に、送
信側の電源断或いはケーブル抜けとしてアラーム信号を
出力する構成とする。又更に、レベル検出部６に積分回
路を接続した構成とする。The level detecting section 6 is configured to output an alarm signal indicating that the transmitting side power is cut off or the cable is disconnected when the potential of at least one of the balanced transmission lines 1 reaches the ground level. Furthermore, an integration circuit is connected to the level detection section 6.
【００１１】[0011]
【作用】正常時は、送信回路７から平衡伝送路１に擬似
ＥＣＬレベルのデータが送出されるから、差動増幅器２
の入力端子に接地抵抗４，５が接続されていても、擬似
ＥＣＬレベルとなるから、レベル検出部６は正常と判定
することになる。送信回路７側の電源断，ケーブル抜け
の場合、差動増幅器２の入力端子に接地抵抗４，５が接
続されているので、擬似ＥＣＬレベルより低い例えば接
地レベルとなる。このレベル低下をレベル検出部６によ
り検出してアラーム信号を出力することができる。又平
衡伝送路１に大きい同相ノイズが誘導された場合に、平
衡伝送路１の何れか一方の線のレベルが擬似ＥＣＬレベ
ルより低下することがある。この場合のレベル低下は継
続的ではないから、積分回路を設けることにより、アラ
ーム信号が出力されないようにし、継続的にレベル低下
の場合はアラーム信号が出力されることになる。[Operation] Under normal conditions, pseudo-ECL level data is sent from the transmitting circuit 7 to the balanced transmission line 1, so the differential amplifier 2
Even if the grounding resistors 4 and 5 are connected to the input terminals of , the level detecting section 6 will determine that it is normal because the pseudo ECL level will be obtained. In the case of power failure or cable disconnection on the transmitting circuit 7 side, since the grounding resistors 4 and 5 are connected to the input terminals of the differential amplifier 2, the level becomes lower than the pseudo ECL level, for example, at the ground level. This level drop can be detected by the level detection section 6 and an alarm signal can be output. Further, when large common-mode noise is induced in the balanced transmission line 1, the level of either line of the balanced transmission line 1 may fall below the pseudo ECL level. Since the level drop in this case is not continuous, an integrating circuit is provided to prevent the output of an alarm signal, and in the case of a continuous level drop, an alarm signal is output.
【００１２】0012
【実施例】図２は本発明の一実施例の説明図であり、１
１は平衡伝送路、１２は差動増幅器、１３は終端抵抗、
１４，１５は接地抵抗、１６はレベル検出部を構成する
ゲート回路、１７は送信回路、１８，１９はコネクタ、
２０はアンド回路である。受信回路を構成する差動増幅
器１２の＋入力端子と−入力端子との間に終端抵抗１３
を接続し、且つ＋入力端子及び−入力端子接続と接地と
の間にそれぞれ接地抵抗１４，１５を接続し、−入力端
子にゲート回路１６を接続したものである。従って、送
信回路１７の擬似ＥＣＬレベルの出力信号による電流が
、平衡伝送路１１から接地抵抗１４，１５を介して接地
に流れることになる。[Embodiment] FIG. 2 is an explanatory diagram of an embodiment of the present invention.
1 is a balanced transmission line, 12 is a differential amplifier, 13 is a terminating resistor,
14 and 15 are grounding resistors, 16 is a gate circuit that constitutes a level detection section, 17 is a transmitting circuit, 18 and 19 are connectors,
20 is an AND circuit. A terminating resistor 13 is installed between the +input terminal and the -input terminal of the differential amplifier 12 constituting the receiving circuit.
, ground resistors 14 and 15 are connected between the +input terminal and the -input terminal connection and the ground, respectively, and a gate circuit 16 is connected to the -input terminal. Therefore, the current caused by the pseudo ECL level output signal of the transmitting circuit 17 flows from the balanced transmission line 11 to the ground via the grounding resistors 14 and 15.
【００１３】装置Ａの送信回路１７は例えば図６に示す
構成を有し、平衡伝送路１１に擬似ＥＣＬレベルの平衡
信号を送出するものであり、装置Ｂの受信回路を構成す
る差動増幅器１２の＋入力端子と−入力端子とに擬似Ｅ
ＣＬレベルの平衡信号が入力される。ゲート回路１６は
、擬似ＥＣＬレベル以上の入力によりハイレベルの信号
を出力するもので、それによって、差動増幅器１２の出
力がアンド回路２０を介して受信データとして送出され
る。The transmitting circuit 17 of the device A has the configuration shown in FIG. 6, for example, and sends out a balanced signal at a pseudo ECL level to the balanced transmission line 11, and includes a differential amplifier 12 constituting the receiving circuit of the device B. Pseudo E is connected to the + input terminal and - input terminal of
A balanced signal at CL level is input. The gate circuit 16 outputs a high level signal in response to an input equal to or higher than the pseudo ECL level, and thereby the output of the differential amplifier 12 is sent out as received data via the AND circuit 20.
【００１４】又送信回路１７側の電源断，コネクタ１８
，１９の抜け，平衡伝送路１１の断線等の場合、差動増
幅器１２の＋入力端子と−入力端子とは接地抵抗１４，
１５を介して接地レベルとなる。即ち、擬似ＥＣＬレベ
ルより低下することになる。従って、ゲート回路１６の
出力信号はローレベルとなり、アンド回路２０は閉じら
れて差動増幅器１２の出力は阻止され、又ローレベルの
アラーム信号が出力される。[0014] Also, if the power is cut off on the transmitting circuit 17 side, the connector 18
, 19, disconnection of the balanced transmission line 11, etc., the + and - input terminals of the differential amplifier 12 are connected to the ground resistor 14,
15 to the ground level. In other words, it will be lower than the pseudo ECL level. Therefore, the output signal of the gate circuit 16 becomes low level, the AND circuit 20 is closed, the output of the differential amplifier 12 is blocked, and a low level alarm signal is output.
【００１５】図３は本発明の他の実施例の説明図であり
、レベル検出部６として比較器２１を設けた場合を示し
、他の図２と同一符号は同一部分を示す。比較器２１は
、基準電圧２２と平衡伝送路１１の一方の線のレベルと
を比較するもので、この基準電圧２２は擬似ＥＣＬレベ
ルより低い値に選定されている。従って、正常時は、比
較器２１の出力信号はハイレベルとなり、アンド回路２
０は開かれて、差動増幅器１２の出力は受信データとし
て送出される。又送信回路１７側の電源断，コネクタ１
８，１９の抜け，平衡伝送路１１の断線等の場合に、平
衡伝送路１１のレベルが擬似ＥＣＬレベル以下となるか
ら、比較器２１の出力信号はローレベルとなり、アンド
回路２０は閉じられ、且つローレベルのアラーム信号が
送出される。FIG. 3 is an explanatory diagram of another embodiment of the present invention, in which a comparator 21 is provided as the level detection section 6, and the same reference numerals as in FIG. 2 indicate the same parts. The comparator 21 compares a reference voltage 22 with the level of one line of the balanced transmission line 11, and this reference voltage 22 is selected to have a value lower than the pseudo ECL level. Therefore, under normal conditions, the output signal of the comparator 21 is at a high level, and the AND circuit 2
0 is opened and the output of differential amplifier 12 is sent out as received data. Also, power off on the transmitting circuit 17 side, connector 1
8, 19 or a break in the balanced transmission line 11, the level of the balanced transmission line 11 becomes below the pseudo ECL level, so the output signal of the comparator 21 becomes low level, and the AND circuit 20 is closed. Additionally, a low level alarm signal is sent out.
【００１６】図４は本発明の更に他の実施例の説明図で
あり、レベル検出部２３の出力側に積分回路２４を設け
たものであり、他の図２及び図３と同一符号は同一部分
を示す。前述のゲート回路１６や比較器２１等からなる
レベル検出部２３の出力信号は、平衡伝送路１１に大き
な同相ノイズが誘導された時に、平衡伝送路１１のレベ
ルが擬似ＥＣＬレベルよりランダム的に低下することが
ある。このようなランダム的なローレベルの出力信号は
、積分回路２４により継続したハイレベルの信号となる
から、ローレベルのアラーム信号が送出されることなは
く、且つアンド回路２０は継続して開かれることになる
。そして、送信回路１７側の電源断，ケーブル抜け等の
場合は、継続してレベル検出部２３の出力信号はローレ
ベルとなるから、積分回路２４の出力信号も継続してロ
ーレベルとなり、アラーム信号送出となる。FIG. 4 is an explanatory diagram of still another embodiment of the present invention, in which an integrating circuit 24 is provided on the output side of the level detecting section 23, and the same reference numerals as in the other FIGS. 2 and 3 are the same. Show parts. The output signal of the level detection unit 23 consisting of the gate circuit 16, comparator 21, etc. described above is such that when large common-mode noise is induced in the balanced transmission line 11, the level of the balanced transmission line 11 randomly decreases below the pseudo ECL level. There are things to do. Since such a random low-level output signal becomes a continuous high-level signal by the integrating circuit 24, a low-level alarm signal is not sent out, and the AND circuit 20 remains open. It will be. In the case of a power failure on the transmitting circuit 17 side, a cable disconnection, etc., the output signal of the level detection section 23 will continue to be at a low level, so the output signal of the integrating circuit 24 will also continue to be at a low level, and an alarm signal will be signaled. It will be sent out.
【００１７】[0017]
【発明の効果】以上説明したように、本発明は、擬似Ｅ
ＣＬレベルのデータを受信する差動増幅器２の入力端子
間に終端抵抗３を接続し、各入力端子と接地との間に接
地抵抗４，５を接続し、レベル検出部６を設けたもので
あり、送信回路７からの擬似ＥＣＬレベルのデータが送
出されている場合の正常時は、平衡伝送路１のレベルは
擬似ＥＣＬレベルを保つことになるが、送信回路７側の
電源断又はケーブル抜けの場合は、平衡伝送路１のレベ
ルは擬似ＥＣＬレベル以下となり、これをレベル検出部
６で検出してアラーム信号を送出するもので、擬似ＥＣ
Ｌ回路構成を用いて高速動作を可能とし、且つ検出用の
伝送路や送受信回路を設けなくても、送信回路７側の電
源断やケーブル抜けを検出できるから、受信回路の構成
を簡単化できる利点がある。Effects of the Invention As explained above, the present invention provides pseudo E
A terminating resistor 3 is connected between the input terminals of a differential amplifier 2 that receives CL level data, grounding resistors 4 and 5 are connected between each input terminal and the ground, and a level detecting section 6 is provided. Yes, the level of balanced transmission line 1 will maintain the pseudo ECL level during normal operation when pseudo ECL level data is being sent from the transmitting circuit 7, but if the power is cut off on the transmitting circuit 7 side or the cable is disconnected. In this case, the level of the balanced transmission line 1 is below the pseudo ECL level, which is detected by the level detector 6 and an alarm signal is sent out.
High-speed operation is possible using the L circuit configuration, and power failure or cable disconnection on the transmitting circuit 7 side can be detected without providing a detection transmission line or transmitting/receiving circuit, so the configuration of the receiving circuit can be simplified. There are advantages.
【００１８】更に、図４に示すように、レベル検出部に
積分回路を設けたことにより、ノイズ等による誤動作を
防止し、送信回路７側の電源断やケーブル抜けの検出動
作の信頼性を向上することができる利点がある。Furthermore, as shown in FIG. 4, by providing an integrating circuit in the level detection section, malfunctions due to noise etc. are prevented, and the reliability of the detection operation of power failure or cable disconnection on the transmitting circuit 7 side is improved. There are advantages to being able to do so.
【図１】本発明の原理説明図である。FIG. 1 is a diagram explaining the principle of the present invention.
【図２】本発明の一実施例の説明図である。FIG. 2 is an explanatory diagram of one embodiment of the present invention.
【図３】本発明の他の実施例の説明図である。FIG. 3 is an explanatory diagram of another embodiment of the present invention.
【図４】本発明の更に他の実施例の説明図である。FIG. 4 is an explanatory diagram of still another embodiment of the present invention.
【図５】従来例の説明図である。FIG. 5 is an explanatory diagram of a conventional example.
【図６】擬似ＥＣＬ回路構成の送信回路の要部回路図で
ある。FIG. 6 is a circuit diagram of a main part of a transmitting circuit having a pseudo ECL circuit configuration.
【図７】擬似ＥＣＬ回路構成の受信回路の要部回路図で
ある。FIG. 7 is a circuit diagram of a main part of a receiving circuit having a pseudo ECL circuit configuration.
【図８】ＴＴＬ回路構成の送信回路の要部回路図である
。FIG. 8 is a circuit diagram of a main part of a transmitting circuit having a TTL circuit configuration.
１ 平衡伝送路 ２ 差動増幅器 ３ 終端抵抗 ４，５ 接地抵抗 ６ レベル検出部 ７ 送信回路 ８，９ コネクタ 1 Balanced transmission line 2 Differential amplifier 3 Terminating resistor 4,5 Ground resistance 6 Level detection section 7 Transmission circuit 8,9 Connector
Claims (3)
ベルで伝送されたデータを受信する差動増幅器（２）を
含むデータ受信回路に於いて、前記差動増幅器（２）の
入力端子間に接続した終端抵抗（３）と、前記差動増幅
器（２）の各入力端子と接地との間に接続した接地抵抗
（４），（５）と、前記差動増幅器（２）に接続された
前記平衡伝送路（１）の少なくとも何れか一方の線のレ
ベルが前記擬似ＥＣＬレベルより低いレベルか否かを検
出するレベル検出部（６）とを備えたことを特徴とする
データ受信回路。Claim 1: In a data receiving circuit including a differential amplifier (2) that receives data transmitted at a pseudo ECL level through a balanced transmission line (1), a A terminating resistor (3) connected, a grounding resistor (4), (5) connected between each input terminal of the differential amplifier (2) and ground, and a terminal resistor (4), (5) connected to the differential amplifier (2). A data receiving circuit comprising: a level detecting section (6) for detecting whether the level of at least one line of the balanced transmission line (1) is lower than the pseudo ECL level.
伝送路（１）の少なくとも何れか一方の電位がほぼ接地
レベルになった時に、送信側の電源断或いはケーブル抜
けとしてアラーム信号を出力する構成を有することを特
徴とする請求項１のデータ受信回路。2. The level detection unit (6) outputs an alarm signal as a result of a power cut on the transmitting side or a cable disconnection when the potential of at least one of the balanced transmission lines (1) reaches approximately the ground level. 2. The data receiving circuit according to claim 1, wherein the data receiving circuit has a configuration.
接続したことを特徴とする請求項１のデータ受信回路。3. The data receiving circuit according to claim 1, wherein an integrating circuit is connected to the level detecting section (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3029023A JPH04245817A (en) | 1991-01-31 | 1991-01-31 | Data reception circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3029023A JPH04245817A (en) | 1991-01-31 | 1991-01-31 | Data reception circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04245817A true JPH04245817A (en) | 1992-09-02 |
Family
ID=12264822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3029023A Withdrawn JPH04245817A (en) | 1991-01-31 | 1991-01-31 | Data reception circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04245817A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08229014A (en) * | 1995-02-28 | 1996-09-10 | Tochigi Nippon Denki Kk | Electrocardiograph |
| JP2007235622A (en) * | 2006-03-01 | 2007-09-13 | Nec Corp | Differential transmission circuit and signal regeneration method |
| WO2008056719A1 (en) * | 2006-11-07 | 2008-05-15 | Sony Corporation | Electronic apparatus and cable device |
| JP2008277966A (en) * | 2007-04-26 | 2008-11-13 | Nec Electronics Corp | Semiconductor device |
| JP2009207096A (en) * | 2008-02-29 | 2009-09-10 | Thine Electronics Inc | Input buffer circuit |
| JP2011206948A (en) * | 2010-03-29 | 2011-10-20 | Canon Inc | Image forming apparatus |
| KR101449229B1 (en) * | 2010-06-30 | 2014-10-08 | 애플 인크. | Circuitry for active cable |
| US9143637B2 (en) | 2006-11-07 | 2015-09-22 | Sony Corporation | Transmission device, video signal transmission method for transmission device, reception device, and video signal reception method for reception device |
| US9210353B2 (en) | 2006-11-07 | 2015-12-08 | Sony Corporation | Electronic equipment, control information transmission and reception methods having bidirectional communication using predetermined lines |
-
1991
- 1991-01-31 JP JP3029023A patent/JPH04245817A/en not_active Withdrawn
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08229014A (en) * | 1995-02-28 | 1996-09-10 | Tochigi Nippon Denki Kk | Electrocardiograph |
| JP2007235622A (en) * | 2006-03-01 | 2007-09-13 | Nec Corp | Differential transmission circuit and signal regeneration method |
| US9143637B2 (en) | 2006-11-07 | 2015-09-22 | Sony Corporation | Transmission device, video signal transmission method for transmission device, reception device, and video signal reception method for reception device |
| WO2008056719A1 (en) * | 2006-11-07 | 2008-05-15 | Sony Corporation | Electronic apparatus and cable device |
| US9769520B2 (en) | 2006-11-07 | 2017-09-19 | Sony Corporation | Electronic equipment, control information transmission and reception methods having bidirectional communication using predetermined lines |
| US9462211B2 (en) | 2006-11-07 | 2016-10-04 | Sony Corporation | Electronic equipment, control information transmission and reception methods having bidirectional communication using predetermined lines |
| US8456188B2 (en) | 2006-11-07 | 2013-06-04 | Sony Corporation | Electronic apparatus and cable device |
| JP5239867B2 (en) * | 2006-11-07 | 2013-07-17 | ソニー株式会社 | Electronic equipment and cable device |
| KR101432846B1 (en) * | 2006-11-07 | 2014-08-26 | 소니 주식회사 | Electronic apparatus and cable device |
| US9210353B2 (en) | 2006-11-07 | 2015-12-08 | Sony Corporation | Electronic equipment, control information transmission and reception methods having bidirectional communication using predetermined lines |
| US8860887B2 (en) | 2006-11-07 | 2014-10-14 | Sony Corporation | Communication system, transmitter, receiver, communication method, program, and communication cable |
| US9013636B2 (en) | 2006-11-07 | 2015-04-21 | Sony Corporation | Communication system, transmitter, receiver, communication method, program, and communication cable |
| US9210465B2 (en) | 2006-11-07 | 2015-12-08 | Sony Corporation | Communication system, transmitter, receiver, communication method, program, and communication cable |
| JP2008277966A (en) * | 2007-04-26 | 2008-11-13 | Nec Electronics Corp | Semiconductor device |
| JP2009207096A (en) * | 2008-02-29 | 2009-09-10 | Thine Electronics Inc | Input buffer circuit |
| JP2011206948A (en) * | 2010-03-29 | 2011-10-20 | Canon Inc | Image forming apparatus |
| KR101449229B1 (en) * | 2010-06-30 | 2014-10-08 | 애플 인크. | Circuitry for active cable |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |