JPH04241443A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH04241443A JPH04241443A JP323991A JP323991A JPH04241443A JP H04241443 A JPH04241443 A JP H04241443A JP 323991 A JP323991 A JP 323991A JP 323991 A JP323991 A JP 323991A JP H04241443 A JPH04241443 A JP H04241443A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- chip carrier
- substrate
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 abstract description 9
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 abstract description 6
- 241000587161 Gomphocarpus Species 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 16
- 238000007747 plating Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000004744 fabric Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000013464 silicone adhesive Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000004382 potting Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000914 Mn alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910002666 PdCl2 Inorganic materials 0.000 description 1
- 206010070834 Sensitisation Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- ARHWPKZXBHOEEE-UHFFFAOYSA-N alclofenac Chemical compound OC(=O)CC1=CC=C(OCC=C)C(Cl)=C1 ARHWPKZXBHOEEE-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000008313 sensitization Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- ANOBYBYXJXCGBS-UHFFFAOYSA-L stannous fluoride Chemical compound F[Sn]F ANOBYBYXJXCGBS-UHFFFAOYSA-L 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置及びその製造
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】0002
【従来の技術】従来のピングリッドアレイパッケージ型
半導体装置は、パッケージ基板にセラミックを使用し、
該セラミックの表面、詳しくはセラミックグリーンシー
ト上に高融点金属、例えばタングステン、モリブデン−
マンガン系合金等を用いて印刷法などの手段で配線を形
成し、同時焼成後リードピンを口一付けし、ついで所定
の位置に半導体チップを搭載していた。[Prior Art] A conventional pin grid array package type semiconductor device uses ceramic for the package substrate.
A high-melting point metal, such as tungsten or molybdenum, is applied to the surface of the ceramic, specifically the ceramic green sheet.
Wiring was formed using a printing method using a manganese alloy, etc., and after simultaneous firing, lead pins were attached to the ends, and then semiconductor chips were mounted in predetermined positions.
【０００３】0003
【発明が解決しようとする課題】しかしながら従来の半
導体装置は、高温で同時焼成するために製造工程が長く
高価であるという欠点がある。However, conventional semiconductor devices have the disadvantage that the manufacturing process is long and expensive because they are simultaneously fired at high temperatures.
【０００４】この改良として特開昭６１−７８１４４号
公報に示されるように、キャップ側に半導体チップを搭
載し、これとパッケージ基板とを半田バンプなどを用い
てフリップチップ方式で接続する方法がある。ところが
この方法では稼動時の温度変化による金属疲労で接続部
が破断し易いという問題点がある。As an improvement on this, as shown in Japanese Patent Laid-Open No. 61-78144, there is a method in which a semiconductor chip is mounted on the cap side and this is connected to the package substrate using a flip-chip method using solder bumps or the like. . However, this method has a problem in that the connection part is likely to break due to metal fatigue due to temperature changes during operation.
【０００５】本発明は上記のような問題点が生じない半
導体装置及びその製造法を提供することを目的とするも
のである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that do not cause the above-mentioned problems.
【０００６】[0006]
【課題を解決するための手段】本発明は高熱伝導性基板
の下部のほぼ中央部に凹部及び中央部を除いた部分に配
線パターンが形成されたチップキャリヤー用基板、該チ
ップキャリヤー用基板の凹部に接着された半導体チップ
、半導体チップと配線パターンとを接続するワイヤーを
有し、かつ半導体チップ、ワイヤー及び配線パターンの
内側が絶縁材料で封止されたチップキャリヤーと、貫通
孔を有し、貫通孔の周囲に配線パターンが形成され、か
つ貫通孔内にリードピンが挿入、固着されたパッケージ
基板とからなり、該パッケージ基板上面の配線パターン
の内側端部とチップキャリヤー下面の配線パターンの外
側端部とが柔軟性を有する配線材で電気的に接続された
半導体装置並びに高熱伝導性基板の下部のほぼ中央部に
凹部を、また中央部を除いた部分に配線パターンを形成
したチップキャリヤー用基板を作製し、この後高熱伝導
性基板の下部に設けた凹部に半導体チップを接着し、つ
いで半導体チップと配線パターンとをワイヤーで接続し
た後、半導体チップ、ワイヤー及び配線パターンの内側
を絶縁材料で封止してチップキャリヤーを作製し、一方
貫通孔及び貫通孔の周囲に配線パターンを形成し、かつ
貫通孔内にリードピンを挿入して固着したパッケージ基
板を作製し、この後該パッケージ基板の上面の配線パタ
ーンの内側端部とチップキャリヤー下面の配線パターン
の外側端部とを柔軟性を有する配線材で電気的に接続す
る半導体装置の製造法に関する。[Means for Solving the Problems] The present invention provides a substrate for a chip carrier in which a concave portion is formed in the lower part of a highly thermally conductive substrate and a wiring pattern is formed in a portion other than the central portion, and a concave portion of the substrate for a chip carrier. A chip carrier has a semiconductor chip bonded to the semiconductor chip, a wire connecting the semiconductor chip and the wiring pattern, and the inside of the semiconductor chip, the wire, and the wiring pattern are sealed with an insulating material; It consists of a package substrate on which a wiring pattern is formed around a hole and a lead pin is inserted and fixed in the through hole, and the inner end of the wiring pattern on the upper surface of the package substrate and the outer end of the wiring pattern on the lower surface of the chip carrier. A semiconductor device electrically connected with a flexible wiring material, and a chip carrier substrate having a recessed portion approximately in the center of the lower part of the highly thermally conductive substrate and a wiring pattern formed in the area excluding the central portion. After that, the semiconductor chip is bonded to the recess provided at the bottom of the highly thermally conductive substrate, the semiconductor chip and the wiring pattern are connected with wires, and the insides of the semiconductor chip, wires, and wiring pattern are sealed with an insulating material. A chip carrier is prepared by holding the through hole, and a wiring pattern is formed around the through hole, and a package substrate is prepared in which lead pins are inserted and fixed into the through hole, and then the upper surface of the package substrate is The present invention relates to a method of manufacturing a semiconductor device in which an inner end of a wiring pattern and an outer end of a wiring pattern on the lower surface of a chip carrier are electrically connected using a flexible wiring material.
【０００７】本発明において用いられる高熱伝導性基板
としては、炭素ケイ素、窒化アルミニウム等のセラミッ
ク基板が用いられる。この基板上への配線パターンの形
成法としては特に制限はないが、めっき法、厚膜印刷法
、薄膜法等の方法で行うことが好ましい。[0007] As the highly thermally conductive substrate used in the present invention, a ceramic substrate such as carbon silicon or aluminum nitride is used. Although there are no particular limitations on the method of forming the wiring pattern on this substrate, it is preferable to use a plating method, a thick film printing method, a thin film method, or the like.
【０００８】パッケージ基板としては、ガラス布基材エ
ポキシプリント配線板、ガラス布基材ポリイミドプリン
ト配線板、ガラス布基材テフロン配線板、アラミド繊維
基材ポリイミド配線板等の有機系プリント配線板が用い
られる。As the package substrate, organic printed wiring boards such as glass cloth-based epoxy printed wiring boards, glass cloth-based polyimide printed wiring boards, glass cloth-based Teflon wiring boards, and aramid fiber-based polyimide wiring boards are used. It will be done.
【０００９】パッケージ基板に挿入、固定されるピンの
材質は、特に制限はないが、コバール、４２合金、５２
合金等のＮｉ−Ｆｅ合金、銅、銅合金等が用いられる。
ピンと貫通孔の周辺に形成されたランド（配線パターン
の一部）及び貫通孔内に形成された導電部分との固着は
、Ｓｎ／Ｐｂが６３／３７、２０／８０、１０／９０の
半田、錫−アンチモン系の半田等が用いられる。The material of the pins inserted and fixed to the package board is not particularly limited, but Kovar, 42 alloy, 52
Ni--Fe alloys, copper, copper alloys, etc., such as alloys, are used. The fixation between the pin and the land (part of the wiring pattern) formed around the through hole and the conductive part formed inside the through hole is achieved by using solder with Sn/Pb of 63/37, 20/80, or 10/90. Tin-antimony based solder or the like is used.
【００１０】半導体チップと高熱伝導性基板上に形成し
た配線パターンとの接続は、Ａｕワイヤー、Ａｌワイヤ
ー等の線材を用いたワイヤーボンディングが適している
。半導体チップ、接続ワイヤー及び配線パターンの内側
の封止材としては、シリコーンゲル、エポキシ樹脂等の
有機系樹脂を用いることが好ましい。また半導体チップ
のチップキャリヤー用基板の凹部への固定は、窒化アル
ミ粉、炭化ケイ素粉、銀粉、アルミ粉等の熱伝導性材を
含むエポキシ樹脂、ポリイミド樹脂、シリコーン樹脂等
を用いて接着することが好ましい。Wire bonding using wires such as Au wires and Al wires is suitable for connecting the semiconductor chip and the wiring pattern formed on the highly thermally conductive substrate. As the sealing material inside the semiconductor chip, connection wires, and wiring pattern, it is preferable to use organic resin such as silicone gel or epoxy resin. In addition, to fix the semiconductor chip in the recess of the chip carrier substrate, use epoxy resin, polyimide resin, silicone resin, etc. containing a thermally conductive material such as aluminum nitride powder, silicon carbide powder, silver powder, or aluminum powder to adhere the semiconductor chip. is preferred.
【００１１】パッケージ基板上面の配線パターンの内側
端部とチップキャリヤー下面の配線パターンの外側端部
とを電気的に接続する柔軟性を有する配線材としては、
フレキシブル配線板、異方導電性フィルム等が用いられ
る。フレキシブル配線板の材質としては、ポリイミド樹
脂フィルム、ポリエステル樹脂フィルム等が用いられ、
これらのフィルム表面に所望の銅パターンを形成して使
用する。電気的に接続する柔軟性を有する配線板と各配
線パターンの端部との接続は、半田を用いて接続するこ
とが好ましい。半田の組成については特に制限はないが
、Ｓｎ／Ｐｂ＝６３／３７の半田を用いることが好まし
い。The flexible wiring material for electrically connecting the inner end of the wiring pattern on the upper surface of the package substrate and the outer end of the wiring pattern on the lower surface of the chip carrier is as follows:
Flexible wiring boards, anisotropic conductive films, etc. are used. Polyimide resin film, polyester resin film, etc. are used as materials for flexible wiring boards.
A desired copper pattern is formed on the surface of these films and used. It is preferable that solder be used to connect the flexible wiring board for electrical connection and the ends of each wiring pattern. Although there are no particular restrictions on the composition of the solder, it is preferable to use solder with Sn/Pb=63/37.
【００１２】チップキャリヤーとパッケージ基板とは、
エポキシ樹脂、変性エポキシ樹脂、シリコーン樹脂等の
熱硬化性樹脂を用いて固定することが好ましい。[0012] The chip carrier and the package substrate are
It is preferable to fix using a thermosetting resin such as an epoxy resin, a modified epoxy resin, or a silicone resin.
【００１３】本発明になる半導体装置は、必要に応じチ
ップキャリヤーに放熱フィンが接着される。[0013] In the semiconductor device according to the present invention, heat dissipation fins are bonded to the chip carrier as necessary.
【００１４】[0014]
【実施例】以下本発明の実施例を説明する。
実施例１
図２に示すように、寸法が２３×２３ｍｍで厚さが１．
０ｍｍの窒化アルミニウム基板（徳山曹達製、商品名シ
ェイパル）１のほぼ中央部の半導体素子が搭載される部
分に、底面が平坦な凹部を形成し、ついで該窒化アルミ
ニウム基板１をトリクレン溶液（脱脂液）（和光純薬製
、試薬１級）で洗浄し、水洗を行った後、ＳｎＦ２溶液
（５０ｇ／ｌ）中に１５分間浸漬して、粗化及び感受性
化処理を同時に行い、さらに水洗後ＰｄＣｌ２溶液（０
．３ｇ／ｌ）に５分間浸漬して活性化処理を行った。[Examples] Examples of the present invention will be described below. Example 1 As shown in Figure 2, the dimensions are 23 x 23 mm and the thickness is 1.
A recess with a flat bottom surface is formed in the approximately central part of a 0 mm aluminum nitride substrate (manufactured by Tokuyama Soda, trade name Shapal) 1 where a semiconductor element is to be mounted, and then the aluminum nitride substrate 1 is soaked in Triclean solution (degreasing liquid). ) (manufactured by Wako Pure Chemical Industries, reagent grade 1), washed with water, immersed in SnF2 solution (50 g/l) for 15 minutes to perform roughening and sensitization treatment at the same time, and after washing with water, PdCl2 Solution (0
．． 3 g/l) for 5 minutes for activation treatment.
【００１５】この後無電解ニッケルめっきを１０分間行
い、厚さ１．０μｍのニッケル被膜を形成した。なお無
電解ニッケルめっき液は、（日本カニゼン製、商品名シ
ューマーＳ−６８０）を使用した。水洗後、濃度１０重
量％の硫酸溶液に浸漬して酸化被膜を除去後、ソフトエ
ッチング溶液（奥野製薬製、商品名ＯＰＣ−９１、５０
ｍｌ／ｌ）に３０秒間浸漬し、ついで電解銅めっき（硫
酸銅めっき）を１５分間行い、厚さ１０μｍの銅の被膜
を形成した。なお電解銅めっき液は（荏原電産製、商品
名ＰＣ−６３６）を使用した。[0015] After this, electroless nickel plating was performed for 10 minutes to form a 1.0 μm thick nickel film. The electroless nickel plating solution used was (manufactured by Nippon Kanigen, trade name: Schumer S-680). After washing with water, remove the oxide film by immersing it in a sulfuric acid solution with a concentration of 10% by weight.
ml/l) for 30 seconds, and then electrolytic copper plating (copper sulfate plating) was performed for 15 minutes to form a copper film with a thickness of 10 μm. The electrolytic copper plating solution (manufactured by Ebara Densan, trade name: PC-636) was used.
【００１６】次に感光性レジストフィルム（日立化成工
業製、商品名ＰＨＴ−８６２ＡＦ−４０）を前記銅の被
膜上全面に貼付し、さらにその上面に、得られる配線パ
ターンと同形状に透明な部分を形成したネガフィルムを
貼付し、露光してネガフィルムの透明な部分の下面に配
設した感光性レジストフィルムを硬化させた。ついでネ
ガフィルムを取り除き、さらに現像して硬化していない
部分、詳しくは露光していない部分の感光性レジストフ
ィルムを除去し、塩化銅エッチング液でエッチングを行
い配線パターンとして不必要な部分の銅の被膜を除去し
た。Next, a photosensitive resist film (manufactured by Hitachi Chemical Co., Ltd., trade name PHT-862AF-40) is pasted on the entire surface of the copper film, and a transparent part is formed on the top surface in the same shape as the wiring pattern to be obtained. A negative film formed with the above was attached and exposed to light to harden the photosensitive resist film disposed on the lower surface of the transparent portion of the negative film. Next, the negative film is removed, and the photosensitive resist film is removed from the areas that have not been developed and cured, more specifically, the areas that have not been exposed to light, and etched with a copper chloride etching solution to remove the copper from areas that are unnecessary for wiring patterns. The coating was removed.
【００１７】この後、濃度５重量％のＮａＯＨ溶液で硬
化している感光性レジストフィルムを剥離し、配線パタ
ーン２を形成した。Thereafter, the photosensitive resist film cured with a 5% by weight NaOH solution was peeled off to form a wiring pattern 2.
【００１８】次に配線パターン２のランド部となる部分
とその先端部分を除いた部分に耐めっきレジスト（アサ
ヒ化学研究所製、商品名ＣＣＲ５０６）を塗布した後、
ランド部となる部分とその先端部分の銅の被膜上にワッ
ト浴で２〜３μｍの厚さにニッケルめっきを施し、さら
にその上面に１〜１．５μｍの厚さに金めっき〔日本エ
レクトロプレイティングエンジニヤーズ（ＥＥＪＡ）製
、商品名テンペレックス４０１〕を施してランド部（図
示せず）とワイヤーボンディング部（図示せず）とを形
成した。Next, after applying a plating-resistant resist (manufactured by Asahi Chemical Research Institute, trade name: CCR506) to the portion of the wiring pattern 2 excluding the land portion and its tip portion,
Nickel plating is applied to the copper coating on the land portion and its tip to a thickness of 2 to 3 μm in a Watt bath, and then gold plating is applied to the top surface to a thickness of 1 to 1.5 μm [Nippon Electroplating Co., Ltd.] Temperex 401 (manufactured by EEJA)] was applied to form a land portion (not shown) and a wire bonding portion (not shown).
【００１９】この後シリコーンゴム（東レ・ダウコーニ
ング・シリコーン製、商品名ＳＥ４４００）を配線パタ
ーン２上の所定の箇所に塗布し、１５０℃で３０分間熱
硬化させてポッティングダム３を形成したチップキャリ
ヤー用基板４を得た。さらに前記で得たチップキャリヤ
ー用基板４に図３に示すように半導体チップ５をダイボ
ンディングペースト（日立化成工業製、商品名エピナー
ルＥＮ−４１１４）６を用いて接着し、ついでＡｕワイ
ヤー（田中貴金属製、直径３８ｍｍのＡｕ線）７を用い
てワイヤーボンディングを行った後ポッティングダム３
の内部にシリコーンゲル（東レ・ダウコーニング・シリ
コーン製、ＪＣＲ６１１０）８を流し込み、１５０℃で
１時間熱硬化させて半導体チップ５、Ａｕワイヤー７及
び配線パターン２の内部を絶縁材料で封止した。シリコ
ーンゲル８が硬化した後、配線パターン２の外側端部に
柔軟性を有するフレキシブル配線板（日立化成工業製）
９を半田付けして、チップキャリヤー１０を得た。After that, silicone rubber (manufactured by Toray Dow Corning Silicone, trade name SE4400) was applied to a predetermined location on the wiring pattern 2, and the chip carrier was heat-cured at 150° C. for 30 minutes to form a potting dam 3. A substrate 4 for use was obtained. Furthermore, as shown in FIG. 3, a semiconductor chip 5 is bonded to the chip carrier substrate 4 obtained above using a die bonding paste (manufactured by Hitachi Chemical, trade name: Epinal EN-4114) 6, and then Au wire (Tanaka Kikinzoku After wire bonding using a 38mm diameter Au wire) 7, the potting dam 3
A silicone gel (manufactured by Dow Corning Toray Silicone, JCR6110) 8 was poured into the inside of the semiconductor chip 5, the Au wire 7, and the wiring pattern 2 were sealed with an insulating material by heat curing at 150° C. for 1 hour. After the silicone gel 8 has hardened, a flexible wiring board (manufactured by Hitachi Chemical Co., Ltd.) has flexibility at the outer end of the wiring pattern 2.
9 was soldered to obtain a chip carrier 10.
【００２０】一方図４に示すガラス布基材エポキシ配線
板（日立化成工業製、商品名ＭＣＬ−Ｅ−６７）１１の
ほぼ中央部に凹部１４、貫通孔及び貫通孔の周囲に所望
の配線パターン１２を形成し、さらに貫通孔内にすずめ
っきを１０±２μｍの厚さに施した後、貫通孔内に直径
が０．４６ｍｍで一方の端部をくぎの頭状に加工した長
さが７ｍｍの５２合金のネールヘッドピン１３を挿入し
、他の一方の端部（端子）を下面に露出させた後、Ｓｎ
／Ｐｂ＝１０／９０の半田１５を用いて、前記のネール
ヘッドピン１３を固着し、パッケージ基板１６を得た。On the other hand, a glass cloth-based epoxy wiring board (manufactured by Hitachi Chemical Co., Ltd., trade name MCL-E-67) 11 shown in FIG. 12, and then tin-plated the inside of the through hole to a thickness of 10±2 μm, and then inside the through hole, a hole with a diameter of 0.46 mm and one end shaped like a nail head and a length of 7 mm was formed. After inserting the nail head pin 13 made of 52 alloy and exposing the other end (terminal) on the bottom surface,
The nail head pins 13 were fixed using solder 15 of /Pb=10/90 to obtain a package substrate 16.
【００２１】次にパッケージ基板１６の凹部１４にシリ
コーン接着剤（東レ・ダウコーニング・シリコーン製、
商品名ＳＥ４４００）１７を塗布後、前記で得たチップ
キャリヤー１０を図１に示すように該パッケージ基板１
６上の所定の位置に載置し、フレキシブル配線板９の端
部をパッケージ基板１６の端子に半田付け後、１５０℃
で３０分間熱硬化を行い、パッケージ基板１６とチップ
キャリヤー１０とを固着させ半導体装置を得た。この後
チップキャリヤー４の上面にシリコーン接着剤（東レ・
ダウコーニング・シリコーン製、商品名ＳＨ８５０）１
８でアルミニウム製の放熱フィン１９を接着した。Next, silicone adhesive (manufactured by Toray Dow Corning Silicone,
After applying the product (trade name: SE4400) 17, the chip carrier 10 obtained above was attached to the package substrate 1 as shown in FIG.
6, and after soldering the ends of the flexible wiring board 9 to the terminals of the package board 16, heat the flexible wiring board 9 to 150°C.
The package substrate 16 and the chip carrier 10 were fixed together by heat curing for 30 minutes to obtain a semiconductor device. After this, apply silicone adhesive (Toray) to the top surface of the chip carrier 4.
Made by Dow Corning Silicone, product name SH850) 1
In Step 8, heat radiation fins 19 made of aluminum were bonded.
【００２２】実施例２
実施例１で用いたガラス布基材エポキシ配線板に代えて
図５に示すようなガラス布基材ポリイミド配線板（日立
化成工業製、商品名ＭＣＬ−Ｉ−６７）２０を用いて複
数のチップキャリヤー１０を搭載した半導体装置を得た
。なお図５において１９は放熱フィンである。Example 2 In place of the glass cloth-based epoxy wiring board used in Example 1, a glass cloth-based polyimide wiring board (manufactured by Hitachi Chemical Co., Ltd., trade name MCL-I-67) 20 as shown in FIG. 5 was used. A semiconductor device equipped with a plurality of chip carriers 10 was obtained using the method. In addition, in FIG. 5, 19 is a heat radiation fin.
【００２３】[0023]
【発明の効果】本発明になる半導体装置は、半導体チッ
プを高熱伝導性基板に搭載するので熱放散性に優れ、ま
たワイヤーボンディング後封止をしてチップキャリヤー
とするので耐湿信頼性にも優れている。さらに、チップ
キャリヤーとパッケージ基板とを柔軟性を有するフレキ
シブル配線板を用いて接続するので、熱膨張係数の異な
る材料間に生じる応力による接続部の破断を防止する効
果を有する。[Effects of the Invention] The semiconductor device of the present invention has excellent heat dissipation because the semiconductor chip is mounted on a highly thermally conductive substrate, and also has excellent moisture resistance and reliability because it is sealed after wire bonding and used as a chip carrier. ing. Furthermore, since the chip carrier and the package substrate are connected using a flexible wiring board having flexibility, it is possible to prevent the connection portion from breaking due to stress generated between materials having different coefficients of thermal expansion.
【図１】本発明の一実施例になる半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２、図３、図４】本発明の実施例における半導体装
置の製造作業状態を示す断面図である。2, 3, and 4 are cross-sectional views showing the state of manufacturing work of a semiconductor device in an embodiment of the present invention.
【図５】本発明の他の一実施例になる半導体装置の断面
図である。FIG. 5 is a sectional view of a semiconductor device according to another embodiment of the present invention.
１ 窒化アルミニウム基板
２ 配線パターン
３ ポッティングダム
４ チップキャリヤー用基板
５ 半導体チップ
６ ダイボンディングペースト
７ Ａｕワイヤー
８ シリコーンゲル
９ フレキシブル配線板 １
０ チップキャリヤー
１１ ガラス布基材エポキシ配線板 １２
配線パターン
１３ ネールヘッドピン
１４ 凹部１５ 半田
１６ パッケージ基板
１７ シリコーン接着剤
１８ シリコーン接着剤
１９ 放熱フィン
２０ ガラス布基材ポリイミド配線板1 Aluminum nitride substrate
2 Wiring pattern 3 Potting dam
4 Chip carrier substrate 5 Semiconductor chip
6 Die bonding paste 7 Au wire
8 Silicone gel 9 Flexible wiring board 1
0 Chip carrier 11 Glass cloth base epoxy wiring board 12
Wiring pattern 13 Nail head pin
14 recess 15 solder
16 Package board 17 Silicone adhesive
18 Silicone adhesive 19 Heat dissipation fin
20 Glass cloth base polyimide wiring board
Claims (2)
凹部及び中央部を除いた部分に配線パターンが形成され
たチップキャリヤー用基板、該チップキャリヤー用基板
の凹部に接着された半導体チップ、半導体チップと配線
パターンとを接続するワイヤーを有し、かつ半導体チッ
プ、ワイヤー及び配線パターンの内側が絶縁材料で封止
されたチップキャリヤーと、貫通孔を有し貫通孔の周囲
に配線パターンが形成され、かつ貫通孔内にリードピン
が挿入、固着されたパッケージ基板とからなり、該パッ
ケージ基板上面の配線パターンの内側端部とチップキャ
リヤー下面の配線パターンの外側端部とが柔軟性を有す
る配線材で電気的に接続された半導体装置。1. A chip carrier substrate having a concave portion substantially in the center of the lower part of a highly thermally conductive substrate and a wiring pattern formed in a portion excluding the central portion; a semiconductor chip bonded to the concave portion of the chip carrier substrate; A chip carrier having a wire connecting the semiconductor chip and the wiring pattern, and in which the inside of the semiconductor chip, the wire, and the wiring pattern are sealed with an insulating material, and a through hole, and the wiring pattern is formed around the through hole. and a package substrate in which lead pins are inserted and fixed in through holes, and the inner end of the wiring pattern on the upper surface of the package substrate and the outer end of the wiring pattern on the lower surface of the chip carrier are flexible. Semiconductor devices electrically connected.
凹部を、また中央部を除いた部分に配線パターンを形成
したチップキャリヤー用基板を作製し、この後高熱伝導
性基板の下部に設けた凹部に半導体チップを接着し、つ
いで半導体チップと配線パターンとをワイヤーで接続し
た後、半導体チップ、ワイヤー及び配線パターンの内側
を絶縁材料で封止してチップキャリヤーを作製し、一方
貫通孔及び貫通孔の周囲に配線パターンを形成し、かつ
貫通孔内にリードピンを挿入して固着したパッケージ基
板を作製し、この後該パッケージ基板の上面の配線パタ
ーンの内側端部とチップキャリヤー下面の配線パターン
の外側端部とを柔軟性を有する配線材で電気的に接続す
ることを特徴とする半導体装置の製造法。2. A chip carrier substrate is manufactured in which a concave portion is formed approximately in the center of the lower part of a highly thermally conductive substrate, and a wiring pattern is formed in a portion other than the central portion, and then a recess is formed in the lower portion of the highly thermally conductive substrate. After adhering a semiconductor chip to the recessed part, and then connecting the semiconductor chip and the wiring pattern with a wire, the inside of the semiconductor chip, wire, and wiring pattern are sealed with an insulating material to produce a chip carrier. A wiring pattern is formed around the through hole, and a lead pin is inserted into the through hole to create a fixed package board, and then the inner end of the wiring pattern on the top surface of the package board and the wiring pattern on the bottom surface of the chip carrier are formed. 1. A method for manufacturing a semiconductor device, comprising electrically connecting an outer end of the semiconductor device to an outer end of the semiconductor device using a flexible wiring material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP323991A JPH04241443A (en) | 1991-01-16 | 1991-01-16 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP323991A JPH04241443A (en) | 1991-01-16 | 1991-01-16 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04241443A true JPH04241443A (en) | 1992-08-28 |
Family
ID=11551907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP323991A Pending JPH04241443A (en) | 1991-01-16 | 1991-01-16 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04241443A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003518743A (en) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Organic packages with solder for reliable flip-chip connection |
-
1991
- 1991-01-16 JP JP323991A patent/JPH04241443A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003518743A (en) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Organic packages with solder for reliable flip-chip connection |
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