JPH04223716A - Pll synthesizer circuit - Google Patents
Pll synthesizer circuitInfo
- Publication number
- JPH04223716A JPH04223716A JP2406924A JP40692490A JPH04223716A JP H04223716 A JPH04223716 A JP H04223716A JP 2406924 A JP2406924 A JP 2406924A JP 40692490 A JP40692490 A JP 40692490A JP H04223716 A JPH04223716 A JP H04223716A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output signal
- pass filter
- low
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000001105 regulatory effect Effects 0.000 claims description 8
- 230000007423 decrease Effects 0.000 claims description 3
- 238000007599 discharging Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000001360 synchronised effect Effects 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 6
- 230000001276 controlling effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はＰＬＬ（ Ｐｈａｓｅ
Ｌｏｃｋｅｄ Ｌｏｏｐ ） シンセサイザ回路に関す
る。[Industrial Application Field] The present invention relates to PLL (Phase
(Locked Loop) relates to a synthesizer circuit.
【０００２】0002
【従来の技術】従来、ＰＬＬシンセサイザ回路として、
図７に、その回路図を示すようなものが提案されている
。図中、１は水晶発振器、２は基準分周器、３は比較分
周器、４は位相比較器、５はチャージポンプ回路、６は
ローパスフィルタ、７は電圧制御発振器であり、このＰ
ＬＬシンセサイザ回路は、水晶発振器１の出力信号を分
周してなる基準分周器２の出力信号、いわゆる基準信号
Ｓｒと、電圧制御発振器７の出力信号ＳＶＣＯを分周し
てなる比較分周器３の出力信号、いわゆる比較信号Ｓｐ
との位相比較を位相比較器４で行い、基準信号Ｓｒと比
較信号Ｓｐとの位相差がゼロとなるように、チャージポ
ンプ回路５によるローパスフィルタ６の出力電圧ＶＬＰ
Ｆの調整を行って電圧制御発振器７の出力信号ＳＶＣＯ
を目的の周波数にロックし、この電圧制御発振器７の出
力信号ＳＶＣＯをこのＰＬＬシンセサイザ回路の出力信
号とするものである。[Prior Art] Conventionally, as a PLL synthesizer circuit,
A circuit diagram of which is shown in FIG. 7 has been proposed. In the figure, 1 is a crystal oscillator, 2 is a reference frequency divider, 3 is a comparison frequency divider, 4 is a phase comparator, 5 is a charge pump circuit, 6 is a low-pass filter, and 7 is a voltage controlled oscillator.
The LL synthesizer circuit includes an output signal of a reference frequency divider 2 which is obtained by dividing the output signal of a crystal oscillator 1, ie, a reference signal Sr, and a comparison frequency divider which is obtained by dividing an output signal SVCO of a voltage controlled oscillator 7. 3, the so-called comparison signal Sp
The output voltage VLP of the low-pass filter 6 is determined by the charge pump circuit 5 so that the phase difference between the reference signal Sr and the comparison signal Sp becomes zero.
The output signal SVCO of the voltage controlled oscillator 7 is adjusted by adjusting F.
is locked to a target frequency, and the output signal SVCO of this voltage controlled oscillator 7 is used as the output signal of this PLL synthesizer circuit.
【０００３】ここに、位相比較器４は、いわゆる位相弁
別器形の位相比較器であり、基準信号Ｓｒの位相に対す
る比較信号Ｓｐの位相の遅れと、進みとを弁別し、基準
信号Ｓｒの位相に対する比較信号Ｓｐの位相の遅れを表
示する信号φｒと、進みを表示する信号φｐとを別々に
出力するように構成されている。Here, the phase comparator 4 is a so-called phase discriminator type phase comparator, and discriminates between a delay and a lead in the phase of the comparison signal Sp with respect to the phase of the reference signal Sr, and determines the phase of the reference signal Sr. It is configured to separately output a signal φr indicating a phase delay of the comparison signal Sp relative to the phase, and a signal φp indicating a phase advance.
【０００４】また、チャージポンプ回路５及びローパス
フィルタ６は、例えば、図８に示すように構成される。
かかるチャージポンプ回路５及びローパスフィルタ６に
おいては、位相比較信号φｒ及びφｐが共にローレベル
“Ｌ”になると、ＰＮＰトランジスタ５１がＯＮ、ＮＰ
Ｎトランジスタ５２がＯＦＦになり、容量６１、６２に
対するチャージが行われる。また、位相比較信号φｒ及
びφｐが共にハイレベル“Ｈ”になると、ＰＮＰトラン
ジスタ５１がＯＦＦ、ＮＰＮトランジスタ５２がＯＮに
なり、容量６１、６２のディスチャージが行われる。ま
た、位相比較信号φｒ及びφｐが、それぞれハイレベル
“Ｈ”及びローレベル“Ｌ”になると、ＰＮＰトランジ
スタ５１及びＮＰＮトランジスタ５２が共にＯＦＦにな
り、容量６１、６２がフローティング状態にされて容量
６１、６２のチャージ電圧がホールドされ、ローパスフ
ィルタ６の出力電圧ＶＬＰＦが安定する。Further, the charge pump circuit 5 and the low-pass filter 6 are configured as shown in FIG. 8, for example. In the charge pump circuit 5 and the low-pass filter 6, when the phase comparison signals φr and φp both become low level "L", the PNP transistor 51 is turned on and the NP transistor 51 is turned on.
The N transistor 52 is turned off, and the capacitors 61 and 62 are charged. Further, when the phase comparison signals φr and φp both become high level “H”, the PNP transistor 51 is turned off, the NPN transistor 52 is turned on, and the capacitors 61 and 62 are discharged. Furthermore, when the phase comparison signals φr and φp reach a high level "H" and a low level "L", respectively, both the PNP transistor 51 and the NPN transistor 52 are turned off, and the capacitors 61 and 62 are placed in a floating state. , 62 are held, and the output voltage VLPF of the low-pass filter 6 is stabilized.
【０００５】ここに、図９、図１０は、かかる従来のＰ
ＬＬチャージポンプ回路の動作を示すタイムチャートで
あり、特に、図９は、基準信号Ｓｒの周波数をｆｒ、比
較信号Ｓｐの周波数をｆｐとした場合において、電圧制
御発振器７の出力信号ＳＶＣＯが周波数ｆ１にロックさ
れている状態から、比較分周器３の分周比が大きくされ
て、ｆ１より大きい周波数ｆ２にロックされる場合の動
作を示すタイムチャートである。Here, FIGS. 9 and 10 show such conventional P
9 is a time chart showing the operation of the LL charge pump circuit. In particular, FIG. 9 shows that when the frequency of the reference signal Sr is fr and the frequency of the comparison signal Sp is fp, the output signal SVCO of the voltage controlled oscillator 7 has a frequency f1. 3 is a time chart showing an operation when the frequency division ratio of the comparison frequency divider 3 is increased from a state where the frequency is locked to a frequency f2 that is greater than f1.
【０００６】また、図１０は、電圧制御発振器７の出力
信号ＳＶＣＯが周波数ｆ２にロックされている状態から
、比較分周器３の分周比が小さくされて、ｆ１にロック
される場合の動作を示すタイムチャートである。Further, FIG. 10 shows the operation when the output signal SVCO of the voltage controlled oscillator 7 is locked to the frequency f2, and then the frequency division ratio of the comparison frequency divider 3 is decreased and the output signal SVCO is locked to f1. It is a time chart showing.
【０００７】これら図９、図１０から明らかなように、
かかる従来のＰＬＬシンセサイザ回路においては、位相
比較信号φｒは、ロック状態、アンロック状態に関わら
ず、その立ち下がりを基準信号Ｓｒの立ち上がりに同期
され、位相比較信号φｐは、ロック状態、アンロック状
態に関わらず、その立ち上がりを比較信号Ｓｐの立ち上
がりに同期されている。As is clear from these FIGS. 9 and 10,
In such a conventional PLL synthesizer circuit, the falling edge of the phase comparison signal φr is synchronized with the rising edge of the reference signal Sr, regardless of whether the phase comparison signal φr is in the locked or unlocked state, and the phase comparison signal φp is synchronized with the rising edge of the reference signal Sr, regardless of whether the phase comparison signal φr is in the locked or unlocked state. Regardless, its rising edge is synchronized with the rising edge of the comparison signal Sp.
【０００８】ところが、図９に示すように、電圧制御発
振器７の出力信号ＳＶＣＯが周波数ｆ１にロックされて
いる状態から、比較分周器３の分周比が大きくされてｆ
ｒ＞ｆｐなるアンロック状態にされると、位相比較信号
φｒは、その立ち下がりを基準信号Ｓｒの立ち上がりに
同期させたまま、基準信号Ｓｒの位相に対する比較信号
Ｓｐの位相の遅れ分を若干上回る幅だけ、そのローレベ
ル“Ｌ”の部分を拡大させる。なお、この場合、位相比
較信号φｐは、その立ち上がりを比較信号Ｓｐの立ち上
がりに同期されたままであり、ハイレベル“Ｈ”の部分
の幅については、なんら変化しない。However, as shown in FIG. 9, since the output signal SVCO of the voltage controlled oscillator 7 is locked to the frequency f1, the frequency division ratio of the comparison frequency divider 3 is increased to
When the unlocked state is set such that r>fp, the phase comparison signal φr slightly exceeds the phase delay of the comparison signal Sp with respect to the phase of the reference signal Sr, while keeping its falling edge synchronized with the rising edge of the reference signal Sr. The low level "L" portion is expanded by the width. In this case, the rise of the phase comparison signal φp remains synchronized with the rise of the comparison signal Sp, and the width of the high level "H" portion does not change at all.
【０００９】この結果、チャージポンプ回路５は、基準
信号φｒの立ち上がりに同期させて間欠的にそのＰＮＰ
トランジスタ５１をＯＮ状態にし、ローパスフィルタ６
に間欠的にチャージ電圧を供給し、ローパスフィルタ６
の出力電圧ＶＬＰＦを上昇させ、電圧制御発振器７の出
力信号ＳＶＣＯの周波数をｆ２に上昇させる。As a result, the charge pump circuit 5 intermittently pumps its PNP in synchronization with the rise of the reference signal φr.
The transistor 51 is turned on, and the low-pass filter 6 is turned on.
A charge voltage is intermittently supplied to the low-pass filter 6.
, and the frequency of the output signal SVCO of the voltage controlled oscillator 7 is increased to f2.
【００１０】このようにして電圧制御発振器７の出力信
号ＳＶＣＯの周波数がｆ２に上昇すると、基準信号Ｓｒ
の周波数ｆｒと比較信号Ｓｒの周波数ｆｐとはｆｒ＝ｆ
ｐとなるので、位相比較信号φｒは、基準信号Ｓｒ及び
比較信号Ｓｒには位相差がないことを表示する状態に戻
り、ローパスフィルタ６の容量６１、６２がフローティ
ング状態にされて、容量６１、６２のチャージ電圧がホ
ールドされ、ローパスフィルタ６の出力電圧ＶＬＰＦは
電圧制御発振器７の出力信号ＳＶＣＯの周波数がｆ２と
なる電圧に安定し、電圧制御発振器７の出力信号ＳＶＣ
Ｏの周波数はｆ２にロックされる。When the frequency of the output signal SVCO of the voltage controlled oscillator 7 rises to f2 in this way, the reference signal Sr
The frequency fr of the comparison signal Sr and the frequency fp of the comparison signal Sr are fr=f
p, so the phase comparison signal φr returns to a state indicating that there is no phase difference between the reference signal Sr and the comparison signal Sr, and the capacitors 61 and 62 of the low-pass filter 6 are set in a floating state, and the capacitors 61 and 62 are in a floating state. 62 is held, the output voltage VLPF of the low-pass filter 6 becomes stable at a voltage at which the frequency of the output signal SVCO of the voltage controlled oscillator 7 becomes f2, and the output signal SVC of the voltage controlled oscillator 7
The frequency of O is locked to f2.
【００１１】他方、図１０に示すように、電圧制御発振
器７の出力信号ＳＶＣＯが、周波数ｆ２にロックされて
いる状態から、比較分周器３の分周比が小さくされてｆ
ｒ＜ｆｐなるアンロック状態になると、位相比較信号φ
ｐは、その立ち下がりを基準信号Ｓｒの立ち上がりに同
期させたまま、基準信号Ｓｒの位相に対する比較信号Ｓ
ｐの位相の進み分を若干上回る幅だけ、そのハイレベル
“Ｈ”の部分を拡大させる。なお、この場合、位相比較
信号φｒは、その立ち下がりを比較信号Ｓｐの立ち上が
りに同期されたままであり、ローレベル“Ｌ”の部分の
幅については、なんら変化しない。On the other hand, as shown in FIG. 10, the output signal SVCO of the voltage controlled oscillator 7 is locked to the frequency f2, and the frequency division ratio of the comparison frequency divider 3 is reduced to the frequency f2.
When the unlock state becomes r<fp, the phase comparison signal φ
p is a comparison signal S with respect to the phase of the reference signal Sr, with its falling edge synchronized with the rising edge of the reference signal Sr.
The high level "H" portion is expanded by a width slightly exceeding the phase advance of p. In this case, the fall of the phase comparison signal φr remains synchronized with the rise of the comparison signal Sp, and the width of the low level "L" portion does not change at all.
【００１２】この結果、チャージポンプ回路５は、比較
信号Ｓｐの立ち上がりに同期させて間欠的にそのＮＰＮ
トランジスタ５２をＯＮ状態にし、ローパスフィルタ６
の容量６１、６２を間欠的にディスチャージし、ローパ
スフィルタ６の出力電圧ＶＬＰＦを下降させ、電圧制御
発振器７の出力信号ＳＶＣＯの周波数をｆ１に下降させ
る。As a result, the charge pump circuit 5 intermittently pumps the NPN signal in synchronization with the rise of the comparison signal Sp.
The transistor 52 is turned on, and the low-pass filter 6 is turned on.
The capacitors 61 and 62 are intermittently discharged, the output voltage VLPF of the low-pass filter 6 is lowered, and the frequency of the output signal SVCO of the voltage controlled oscillator 7 is lowered to f1.
【００１３】このようにして電圧制御発振器７の出力信
号ＳＶＣＯの周波数がｆ１に下降すると、基準信号Ｓｒ
の周波数ｆｒと比較信号Ｓｒの周波数ｆｐとはｆｒ＝ｆ
ｐとなるので、位相比較信号φｐは基準信号Ｓｒ及び比
較信号Ｓｒには位相差がないことを表示する状態に戻り
、ローパスフィルタ６の容量６１、６２がフローティン
グ状態にされて容量６１、６２のチャージ電圧がホール
ドされ、ローパスフィルタ６の出力電圧ＶＬＰＦは、電
圧制御発振器７の出力信号ＳＶＣＯの周波数がｆ１とな
る電圧に安定し、電圧制御発振器７の出力信号ＳＶＣＯ
の周波数はｆ１にロックされる。When the frequency of the output signal SVCO of the voltage controlled oscillator 7 falls to f1 in this way, the reference signal Sr
The frequency fr of the comparison signal Sr and the frequency fp of the comparison signal Sr are fr=f
p, the phase comparison signal φp returns to the state indicating that there is no phase difference between the reference signal Sr and the comparison signal Sr, and the capacitors 61 and 62 of the low-pass filter 6 are set in a floating state, and the capacitors 61 and 62 The charge voltage is held, and the output voltage VLPF of the low-pass filter 6 becomes stable at a voltage at which the frequency of the output signal SVCO of the voltage controlled oscillator 7 becomes f1, and the output signal SVCO of the voltage controlled oscillator 7
The frequency of is locked to f1.
【００１４】[0014]
【発明が解決しようとする課題】かかる従来のＰＬＬシ
ンセサイザ回路においては、ローパスフィルタ６を構成
する容量６１、６２をチャージする場合、これを基準信
号Ｓｒに同期させて間欠的に行っており、また、ディス
チャージする場合には、これを比較信号Ｓｐに同期させ
て間欠的に行っている。このため、電圧制御発振器７の
出力信号ＳＶＣＯの周波数の切り換えを高速に行うこと
ができないという問題点があった。[Problems to be Solved by the Invention] In such a conventional PLL synthesizer circuit, when charging the capacitors 61 and 62 constituting the low-pass filter 6, this is done intermittently in synchronization with the reference signal Sr. , when discharging is performed intermittently in synchronization with the comparison signal Sp. Therefore, there was a problem in that the frequency of the output signal SVCO of the voltage controlled oscillator 7 could not be switched at high speed.
【００１５】本発明は、かかる点に鑑み、電圧制御発振
器７の出力信号ＳＶＣＯの周波数の切り換えの高速化を
図ることができるようにしたＰＬＬシンセサイザ回路を
提供することを目的とする。SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a PLL synthesizer circuit that can switch the frequency of the output signal SVCO of the voltage controlled oscillator 7 at high speed.
【００１６】[0016]
【課題を解決するための手段】本発明によるＰＬＬシン
セサイザ回路は、図１に、その原理回路図を示すように
、ローパスフィルタ６と、このローパスフィルタ６に設
けられている出力電圧規制用容量のチャージ又はディス
チャージを行い、ローパスフィルタ６の出力電圧ＶＬＰ
Ｆを制御するチャージポンプ回路５と、ローパスフィル
タ６の出力電圧ＶＬＰＦによって、その出力信号ＳＶＣ
Ｏの周波数が制御される電圧制御発振器７と、分周比を
可変とし、電圧制御発振器７の出力信号ＳＶＣＯを分周
する分周器（比較分周器）３と、周波数一定の基準信号
Ｓｒの位相と分周器３の出力信号（比較信号）Ｓｐの位
相を比較し、基準信号Ｓｒの位相に対する分周器３の出
力信号Ｓｐの位相の進み、遅れを別々に表示する位相比
較信号φｒ、φｐを出力する位相弁別器形の位相比較器
４と、チャージポンプ制御回路８とを設けて構成すると
いうものであって、チャージポンプ制御回路８は、分周
器３の分周比を変化させて、電圧制御発振器７の出力信
号ＳＶＣＯの周波数の切り換えを行う場合、目的の周波
数に達するまで、ローパスフィルタ６に設けられている
出力電圧規制用容量をほぼ間断なくチャージ又はディス
チャージしてローパスフィルタ６の出力電圧ＶＬＰＦを
上昇又は下降させるようにチャージポンプ回路５の動作
を制御する信号Ｑｒ、Ｑｐを位相比較信号φｒ、φｐを
加工することにより得、これをチャージポンプ回路５に
供給するように構成される。[Means for Solving the Problems] The PLL synthesizer circuit according to the present invention, as shown in the principle circuit diagram in FIG. Charging or discharging is performed to reduce the output voltage VLP of the low-pass filter 6.
The charge pump circuit 5 that controls F and the output voltage VLPF of the low-pass filter 6 control the output signal SVC.
A voltage controlled oscillator 7 whose frequency is controlled, a frequency divider (comparison frequency divider) 3 whose frequency division ratio is variable and which divides the output signal SVCO of the voltage controlled oscillator 7, and a reference signal Sr whose frequency is constant. A phase comparison signal φr that compares the phase of the output signal (comparison signal) Sp of the frequency divider 3 with the phase of the output signal (comparison signal) Sp of the frequency divider 3 and separately displays the lead or lag of the phase of the output signal Sp of the frequency divider 3 with respect to the phase of the reference signal Sr. , φp, and a charge pump control circuit 8. The charge pump control circuit 8 changes the frequency division ratio of the frequency divider 3. When switching the frequency of the output signal SVCO of the voltage controlled oscillator 7, the output voltage regulation capacitor provided in the low-pass filter 6 is charged or discharged almost continuously until the target frequency is reached. Signals Qr and Qp for controlling the operation of the charge pump circuit 5 to raise or lower the output voltage VLPF of 6 are obtained by processing the phase comparison signals φr and φp, and are supplied to the charge pump circuit 5. configured.
【００１７】[0017]
【作用】本発明においては、ローパスフィルタ６に設け
られている出力電圧規制用容量のチャージ及びディスチ
ャージを行う場合、ほぼ間断なく行われるので、これら
チャージ及びディスチャージを間欠的に行う従来のＰＬ
Ｌシンセサイザ回路に比較して、ローパスフィルタ６の
出力電圧ＶＬＰＦの上昇、下降を高速化することができ
る。したがって、電圧制御発振器７の出力信号ＳＶＣＯ
の周波数の切り換えの高速化を図ることができる。[Operation] In the present invention, charging and discharging of the output voltage regulating capacitor provided in the low-pass filter 6 are performed almost without interruption.
Compared to the L synthesizer circuit, the rise and fall of the output voltage VLPF of the low-pass filter 6 can be made faster. Therefore, the output signal SVCO of the voltage controlled oscillator 7
It is possible to increase the speed of frequency switching.
【００１８】[0018]
【実施例】以下、図２〜図６を参照して、本発明の一実
施例につき説明する。なお、図２において図７に対応す
る部分には同一符号を付し、その重複説明は省略する。
図２は本発明の一実施例を示す回路図であり、本実施例
が図７に示す従来のＰＬＬシンセサイザ回路と異なる点
は、位相比較器４とチャージポンプ回路５との間にチャ
ージポンプ回路５の動作を制御するチャージポンプ制御
回路８を設けた点であり、その他については、図７に示
す従来のＰＬＬシンセサイザ回路と同様に構成されてい
る。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 2 to 6. In FIG. 2, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and redundant explanation thereof will be omitted. FIG. 2 is a circuit diagram showing an embodiment of the present invention. This embodiment differs from the conventional PLL synthesizer circuit shown in FIG. 5 is provided with a charge pump control circuit 8 for controlling the operation of FIG.
【００１９】なお、チャージポンプ制御回路８は、例え
ば、図３に示すように、Ｄフリップフロップ９〜１４、
インバータ１５〜１９、ＡＮＤ回路２０、２１、ＮＡＮ
Ｄ回路２２〜２５を設けて構成される。なお、Ｄフリッ
プフロップ１１、１４において、Ｑ＃は、反転出力を示
している。The charge pump control circuit 8 includes, for example, D flip-flops 9 to 14, as shown in FIG.
Inverters 15-19, AND circuits 20, 21, NAN
It is configured by providing D circuits 22 to 25. Note that in the D flip-flops 11 and 14, Q# indicates an inverted output.
【００２０】ここに、図４、図５は、本実施例の動作を
示すタイムチャートであり、特に、図４は、Ｄフリップ
フロップ１０の出力信号をｒ１、ＡＮＤ回路２０の出力
信号をｒ２、Ｄフリップフロップ１１の出力信号をｒ３
、Ｄフリップフロップ９の出力信号をＴｒ、ＮＡＮＤ回
路２２の出力信号をＧｒ、ＮＡＮＤ回路２３の出力信号
をＱｒ、Ｄフリップフロップ１３の出力信号をｐ１、Ａ
ＮＤ回路２１の出力信号をｐ２、Ｄフリップフロップ１
４の出力信号をｐ３、Ｄフリップフロップ１２の出力信
号をＴｐ、ＮＡＮＤ回路２４の出力信号をＧｐ、インバ
ータ１９の出力信号をＱｐとした場合において、電圧制
御発振器７の出力信号ＳＶＣＯが周波数ｆ１にロックさ
れている状態から、比較分周器３の分周比が大きくされ
て、ｆ１より大きい周波数ｆ２にロックされる場合の動
作を示すタイムチャートである。Here, FIGS. 4 and 5 are time charts showing the operation of this embodiment. In particular, FIG. 4 shows the output signal of the D flip-flop 10 as r1, the output signal of the AND circuit 20 as r2, The output signal of the D flip-flop 11 is r3
, the output signal of the D flip-flop 9 is Tr, the output signal of the NAND circuit 22 is Gr, the output signal of the NAND circuit 23 is Qr, the output signal of the D flip-flop 13 is p1, A
The output signal of the ND circuit 21 is connected to p2, the D flip-flop 1
4, the output signal of the D flip-flop 12 is Tp, the output signal of the NAND circuit 24 is Gp, and the output signal of the inverter 19 is Qp, and the output signal SVCO of the voltage controlled oscillator 7 has a frequency f1. 12 is a time chart showing the operation when the frequency division ratio of the comparison frequency divider 3 is increased from the locked state and the frequency is locked to a frequency f2 larger than f1.
【００２１】また、図５は、電圧制御発振器７の出力信
号ＳＶＣＯが周波数ｆ２にロックされている状態から、
比較分周器３の分周比が小さくされて、ｆ１にロックさ
れる場合の動作を示すタイムチャートである。FIG. 5 also shows that the output signal SVCO of the voltage controlled oscillator 7 changes from a state where it is locked to the frequency f2.
12 is a time chart showing the operation when the frequency division ratio of the comparison frequency divider 3 is decreased and locked to f1.
【００２２】図４から明らかなように、本実施例におい
ては、電圧制御発振器７の出力信号ＳＶＣＯが周波数ｆ
１にロックされている状態から、比較分周器３の分周比
が大きくされて、ｆｒ＞ｆｐなるアンロック状態にされ
ると、チャージポンプ回路５は、アンロックとなった時
点で、基準信号Ｓｒがハイレベル“Ｈ”となっている時
間の間、ローパスフィルタ６にチャージ電圧を供給し、
その後、次の基準信号Ｓｒの立ち上がりの時点から、電
圧制御発振器７の出力信号ＳＶＣＯの周波数が目標の周
波数であるｆ２に高まり、比較信号Ｓｐの位相と基準信
号Ｓｒの位相とが一致するようになるまで、ローパスフ
ィルタ６に設けられている出力電圧規制用容量６１、６
２をほぼ間断なくチャージしてローパスフィルタ６の出
力電圧ＶＬＰＦを上昇させ、電圧制御発振器７の出力信
号ＳＶＣＯの周波数をｆ２に上昇させる。As is clear from FIG. 4, in this embodiment, the output signal SVCO of the voltage controlled oscillator 7 has a frequency f
When the frequency division ratio of the comparison frequency divider 3 is increased from the state where it is locked at 1 to the unlocked state where fr>fp, the charge pump circuit 5 changes to the reference frequency at the time it becomes unlocked. Supplying a charging voltage to the low-pass filter 6 during the time when the signal Sr is at a high level "H",
After that, from the time when the next reference signal Sr rises, the frequency of the output signal SVCO of the voltage controlled oscillator 7 increases to the target frequency f2, so that the phase of the comparison signal Sp and the phase of the reference signal Sr match. until the output voltage regulating capacitors 61, 6 provided in the low-pass filter 6
2 is charged almost continuously to raise the output voltage VLPF of the low-pass filter 6, and raise the frequency of the output signal SVCO of the voltage controlled oscillator 7 to f2.
【００２３】このようにして電圧制御発振器７の出力信
号ＳＶＣＯの周波数がｆ２に上昇すると、基準信号Ｓｒ
の周波数ｆｒと比較信号Ｓｐの周波数ｆｐとは、ｆｒ＝
ｆｐとなるので、位相比較信号φｒは、基準信号Ｓｒ及
び比較信号Ｓｐには位相差がないことを表示する状態に
戻り、ローパスフィルタ６の容量６１、６２がフローテ
ィング状態にされて、容量６１、６２のチャージ電圧が
ホールドされ、ローパスフィルタ６の出力電圧ＶＬＰＦ
は電圧制御発振器７の出力信号ＳＶＣＯの周波数がｆ２
となる電圧に安定し、電圧制御発振器７の出力信号ＳＶ
ＣＯの周波数はｆ２にロックされる。When the frequency of the output signal SVCO of the voltage controlled oscillator 7 rises to f2 in this way, the reference signal Sr
The frequency fr of the comparison signal Sp and the frequency fp of the comparison signal Sp are fr=
fp, the phase comparison signal φr returns to a state indicating that there is no phase difference between the reference signal Sr and the comparison signal Sp, and the capacitors 61 and 62 of the low-pass filter 6 are brought into a floating state, and the capacitors 61 and 62 are set in a floating state. 62 charge voltage is held, and the output voltage VLPF of the low-pass filter 6
The frequency of the output signal SVCO of the voltage controlled oscillator 7 is f2
The output signal SV of the voltage controlled oscillator 7 stabilizes at a voltage of
The frequency of CO is locked to f2.
【００２４】また、図５から明らかなように、電圧制御
発振器７の出力信号ＳＶＣＯが周波数ｆ２にロックされ
ている状態から、比較分周器３の分周比が小さくされて
ｆｒ＜ｆｐなるアンロック状態になると、チャージポン
プ回路５は、アンロックとなった時点で、比較信号Ｓｐ
がハイレベル“Ｈ”となっている時間の間、ローパスフ
ィルタ６に設けられている出力電圧規制用容量６１、６
２をディスチャージし、その後、次に比較信号Ｓｐが立
ち上がる時点から、電圧制御発振器７の出力信号ＳＶＣ
Ｏの周波数が目標の周波数であるｆ１に低まり、比較分
周器３の出力信号Ｓｐの位相と基準信号Ｓｒの位相とが
一致するようになるまで、ローパスフィルタ６に設けら
れている出力電圧規制用容量６１、６２をほぼ間断なく
ディスチャージしてローパスフィルタ６の出力電圧ＶＬ
ＰＦを下降させ、電圧制御発振器７の出力信号ＳＶＣＯ
の周波数をｆ１に下降させる。Further, as is clear from FIG. 5, from the state in which the output signal SVCO of the voltage controlled oscillator 7 is locked to the frequency f2, the frequency division ratio of the comparison frequency divider 3 is reduced to an amplifier where fr<fp. When the lock state is reached, the charge pump circuit 5 transmits the comparison signal Sp at the time the charge pump circuit 5 becomes unlocked.
During the time when is at the high level "H", the output voltage regulating capacitors 61, 6 provided in the low-pass filter 6
2, and then from the next time the comparison signal Sp rises, the output signal SVC of the voltage controlled oscillator 7
The output voltage provided in the low-pass filter 6 is increased until the frequency of O decreases to the target frequency f1 and the phase of the output signal Sp of the comparison frequency divider 3 and the phase of the reference signal Sr match. The output voltage VL of the low-pass filter 6 is maintained by discharging the regulating capacitors 61 and 62 almost continuously.
PF is lowered and the output signal SVCO of the voltage controlled oscillator 7 is
The frequency of is lowered to f1.
【００２５】このようにして電圧制御発振器７の出力信
号ＳＶＣＯの周波数がｆ１に下降すると、基準信号Ｓｒ
の周波数ｆｒと比較信号Ｓｐの周波数ｆｐとはｆｒ＝ｆ
ｐとなるので、位相比較信号φｐは基準信号Ｓｒ及び比
較信号Ｓｐには位相差がないことを表示する状態に戻り
、ローパスフィルタ６の容量６１、６２がフローティン
グ状態にされて容量６１、６２のチャージ電圧がホール
ドされ、ローパスフィルタ６の出力電圧ＶＬＰＦは、電
圧制御発振器７の出力信号ＳＶＣＯの周波数がｆ１とな
る電圧に安定し、電圧制御発振器７の出力信号ＳＶＣＯ
の周波数はｆ１にロックされる。When the frequency of the output signal SVCO of the voltage controlled oscillator 7 falls to f1 in this way, the reference signal Sr
The frequency fr of the comparison signal Sp and the frequency fp of the comparison signal Sp are fr=f
p, the phase comparison signal φp returns to the state indicating that there is no phase difference between the reference signal Sr and the comparison signal Sp, and the capacitors 61 and 62 of the low-pass filter 6 are set in a floating state, and the capacitors 61 and 62 The charge voltage is held, and the output voltage VLPF of the low-pass filter 6 becomes stable at a voltage at which the frequency of the output signal SVCO of the voltage controlled oscillator 7 becomes f1, and the output signal SVCO of the voltage controlled oscillator 7
The frequency of is locked to f1.
【００２６】このように、本実施例においては、チャー
ジポンプ制御回路８を設け、ローパスフィルタ６に設け
られている出力電圧規制用容量６１、６２（図８参照）
のチャージ及びディスチャージを行う場合、これれらを
ほぼ間断なく行うようにしているので、これらチャージ
及びディスチャージを間欠的に行う従来のＰＬＬシンセ
サイザ回路に比較して、ローパスフィルタ６の出力電圧
ＶＬＰＦの上昇、下降を高速化することができる。As described above, in this embodiment, the charge pump control circuit 8 is provided, and the output voltage regulating capacitors 61 and 62 provided in the low-pass filter 6 (see FIG. 8)
When charging and discharging are performed almost continuously, the output voltage VLPF of the low-pass filter 6 increases compared to a conventional PLL synthesizer circuit that performs charging and discharging intermittently. , can speed up the descent.
【００２７】なお、図６は、電圧制御発振器７の出力信
号ＳＶＣＯの周波数がｆ１からｆ２に切り換えられる場
合のローパスフィルタ６の出力電圧ＶＬＰＦの変化を従
来の場合と本実施例の場合とで比較して示したものであ
る。FIG. 6 compares the change in the output voltage VLPF of the low-pass filter 6 when the frequency of the output signal SVCO of the voltage controlled oscillator 7 is switched from f1 to f2 between the conventional case and the case of this embodiment. This is what was shown.
【００２８】[0028]
【発明の効果】本発明によれば、ローパスフィルタ６に
設けられている出力電圧規制用容量のチャージ及びディ
スチャージを行う場合、これらをほぼ間断なく行う構成
としたことにより、これらチャージ及びディスチャージ
を間欠的に行う従来のＰＬＬシンセサイザ回路に比較し
て、ローパスフィルタ６の出力電圧ＶＬＰＦの上昇、下
降を高速化することができるので、電圧制御発振器７の
出力信号ＳＶＣＯの周波数の切り換えの高速化を図るこ
とができる。According to the present invention, when charging and discharging the output voltage regulating capacitor provided in the low-pass filter 6, the charging and discharging are performed almost without interruption, so that the charging and discharging can be performed intermittently. Compared to the conventional PLL synthesizer circuit, which performs a conventional PLL synthesizer circuit, it is possible to increase and decrease the output voltage VLPF of the low-pass filter 6 at a higher speed, so that the frequency of the output signal SVCO of the voltage-controlled oscillator 7 can be switched faster. be able to.
【図１】本発明の原理回路図である。FIG. 1 is a circuit diagram of the principle of the present invention.
【図２】本発明の一実施例を示す回路図である。FIG. 2 is a circuit diagram showing one embodiment of the present invention.
【図３】本発明を構成するチャージポンプ制御回路を示
す回路図である。FIG. 3 is a circuit diagram showing a charge pump control circuit constituting the present invention.
【図４】本発明の一実施例の動作を示すタイムチャート
である。FIG. 4 is a time chart showing the operation of an embodiment of the present invention.
【図５】本発明の一実施例の動作を示すタイムチャート
である。FIG. 5 is a time chart showing the operation of an embodiment of the present invention.
【図６】本発明の一実施例の効果を示すタイムチャート
である。FIG. 6 is a time chart showing the effects of one embodiment of the present invention.
【図７】従来のＰＬＬシンセサイザ回路を示す回路図で
ある。FIG. 7 is a circuit diagram showing a conventional PLL synthesizer circuit.
【図８】図７のＰＬＬシンセサイザ回路を構成するチャ
ージポンプ回路及びローパスフィルタを示す回路図であ
る。8 is a circuit diagram showing a charge pump circuit and a low-pass filter that constitute the PLL synthesizer circuit of FIG. 7. FIG.
【図９】従来のＰＬＬシンセサイザ回路の動作を示すタ
イムチャートである。FIG. 9 is a time chart showing the operation of a conventional PLL synthesizer circuit.
【図１０】従来のＰＬＬシンセサイザ回路の動作を示す
タイムチャートである。FIG. 10 is a time chart showing the operation of a conventional PLL synthesizer circuit.
３ 分周器 ４ 位相比較器 ５ チャージポンプ回路 ６ ローパスフィルタ ７ 電圧制御発振器 ８ チャージポンプ制御回路 3 Frequency divider 4 Phase comparator 5 Charge pump circuit 6 Low pass filter 7 Voltage controlled oscillator 8 Charge pump control circuit
Claims (1)
ィルタ（６）に設けられている出力電圧規制用容量のチ
ャージ又はディスチャージを行い、前記ローパスフィル
タ（６）の出力電圧（ＶＬＰＦ）を制御するチャージポ
ンプ回路（５）と、前記ローパスフィルタ（６）の出力
電圧（ＶＬＰＦ）によって、その出力信号（ＳＶＣＯ）
の周波数が制御される電圧制御発振器（７）と、分周比
を可変とし、前記電圧制御発振器（７）の出力信号（Ｓ
ＶＣＯ）を分周する分周器（３）と、周波数一定の基準
信号（Ｓｒ）の位相と前記分周器（３）の出力信号（Ｓ
ｐ）の位相を比較し、前記基準信号（Ｓｒ）の位相に対
する前記分周器（３）の出力信号（Ｓｐ）の位相の進み
、遅れを別々に表示する位相比較信号（φｒ、φｐ）を
出力する位相弁別器形の位相比較器（４）と、前記分周
器（３）の分周比を変化させて、前記電圧制御発振器（
７）の出力信号（ＳＶＣＯ）の周波数の切り換えを行う
場合、目的の周波数に達するまで、前記ローパスフィル
タ（６）に設けられている出力電圧規制用容量をほぼ間
断なくチャージ又はディスチャージして前記ローパスフ
ィルタ（６）の出力電圧（ＶＬＰＦ）を上昇又は下降さ
せるように前記チャージポンプ回路（５）の動作を制御
する信号（Ｑｒ、Ｑｐ）を前記位相比較信号（φｒ、φ
ｐ）を加工することにより得、これを前記チャージポン
プ回路（５）に供給するチャージポンプ制御回路（８）
とを設けて構成されていることを特徴とするＰＬＬシン
セサイザ回路。1. A low-pass filter (6) and an output voltage regulating capacitor provided in the low-pass filter (6) are charged or discharged to control the output voltage (VLPF) of the low-pass filter (6). The output signal (SVCO) is determined by the charge pump circuit (5) and the output voltage (VLPF) of the low-pass filter (6).
a voltage controlled oscillator (7) whose frequency is controlled; and an output signal (S) of the voltage controlled oscillator (7) whose frequency division ratio is variable;
A frequency divider (3) that divides the frequency of the frequency divider (3), a reference signal (Sr) with a constant frequency, and an output signal (Sr) of the frequency divider (3).
phase comparison signals (φr, φp) that separately display the lead and lag in the phase of the output signal (Sp) of the frequency divider (3) with respect to the phase of the reference signal (Sr). By changing the frequency division ratio of the output phase discriminator type phase comparator (4) and the frequency divider (3), the voltage controlled oscillator (
When switching the frequency of the output signal (SVCO) in step 7), the output voltage regulating capacitor provided in the low-pass filter (6) is almost constantly charged or discharged until the frequency of the output signal (SVCO) reaches the target frequency. The phase comparison signals (φr, φ) are used to control the operation of the charge pump circuit (5) so as to increase or decrease the output voltage (VLPF) of the filter (6).
a charge pump control circuit (8) obtained by processing p) and supplying it to the charge pump circuit (5);
A PLL synthesizer circuit comprising:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2406924A JPH04223716A (en) | 1990-12-26 | 1990-12-26 | Pll synthesizer circuit |
| EP19910403533 EP0493251A3 (en) | 1990-12-26 | 1991-12-24 | Pll synthesizer circuit |
| KR1019910024378A KR960000809B1 (en) | 1990-12-26 | 1991-12-26 | Pll synthesizer circuit |
| US07/812,919 US5166644A (en) | 1990-12-26 | 1991-12-26 | Pll synthesizer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2406924A JPH04223716A (en) | 1990-12-26 | 1990-12-26 | Pll synthesizer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04223716A true JPH04223716A (en) | 1992-08-13 |
Family
ID=18516542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2406924A Withdrawn JPH04223716A (en) | 1990-12-26 | 1990-12-26 | Pll synthesizer circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5166644A (en) |
| EP (1) | EP0493251A3 (en) |
| JP (1) | JPH04223716A (en) |
| KR (1) | KR960000809B1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2854777B2 (en) * | 1992-04-27 | 1999-02-03 | 株式会社東芝 | Phase locked loop circuit and signal extraction method |
| US5359299A (en) * | 1993-01-21 | 1994-10-25 | Gennum Corporation | High speed and low drift charge pump circuit |
| US5384551A (en) * | 1993-02-25 | 1995-01-24 | Delco Electronics Corporation | Fast locking phase locked loop frequency synthesizer |
| JPH07143002A (en) * | 1993-09-20 | 1995-06-02 | Fujitsu Ltd | Pll frequency synthesizer circuit |
| US5483558A (en) * | 1994-08-08 | 1996-01-09 | Motorola Inc. | Method and apparatus for detecting phase or frequency lock |
| US5692023A (en) * | 1994-11-04 | 1997-11-25 | Lsi Logic Corporation | Phase locked loop including distributed phase correction pulses for reducing output ripple |
| JPH09326691A (en) * | 1996-06-06 | 1997-12-16 | Sony Cinema Prod Corp | Phase locked loop circuit |
| US6836192B1 (en) | 2002-01-16 | 2004-12-28 | Microtune (San Diego), Inc. | Methods and apparatuses for tuning voltage controlled oscillators |
| CN102868396A (en) * | 2011-07-04 | 2013-01-09 | 贺林 | Relaxation oscillator of low power consumption and high performance |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58133042A (en) * | 1982-02-03 | 1983-08-08 | Matsushita Electric Ind Co Ltd | Pll circuit |
| JPS621322A (en) * | 1985-06-27 | 1987-01-07 | Nec Corp | Frequency synthesizer |
| US4792705A (en) * | 1986-03-14 | 1988-12-20 | Western Digital Corporation | Fast switching charge pump |
| US4937536A (en) * | 1988-08-19 | 1990-06-26 | Hughes Aircraft Company | Fast settling phase lock loop |
| US4987387A (en) * | 1989-09-08 | 1991-01-22 | Delco Electronics Corporation | Phase locked loop circuit with digital control |
-
1990
- 1990-12-26 JP JP2406924A patent/JPH04223716A/en not_active Withdrawn
-
1991
- 1991-12-24 EP EP19910403533 patent/EP0493251A3/en not_active Withdrawn
- 1991-12-26 US US07/812,919 patent/US5166644A/en not_active Expired - Fee Related
- 1991-12-26 KR KR1019910024378A patent/KR960000809B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US5166644A (en) | 1992-11-24 |
| EP0493251A2 (en) | 1992-07-01 |
| KR920013933A (en) | 1992-07-30 |
| KR960000809B1 (en) | 1996-01-12 |
| EP0493251A3 (en) | 1993-01-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980312 |