JPH04217386A - Manufacture of circuit - Google Patents
Manufacture of circuitInfo
- Publication number
- JPH04217386A JPH04217386A JP41130190A JP41130190A JPH04217386A JP H04217386 A JPH04217386 A JP H04217386A JP 41130190 A JP41130190 A JP 41130190A JP 41130190 A JP41130190 A JP 41130190A JP H04217386 A JPH04217386 A JP H04217386A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conductor
- groove
- etching
- insulation board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004020 conductor Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 33
- 238000007747 plating Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 22
- 229910052802 copper Inorganic materials 0.000 abstract description 20
- 239000010949 copper Substances 0.000 abstract description 20
- 238000009713 electroplating Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 6
- 230000007423 decrease Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は例えばプリント配線板や
ＴＡＢ用フィルムに微細な導体回路を製造する方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing fine conductor circuits on, for example, printed wiring boards or TAB films.
【０００２】0002
【従来の技術】プリント配線板やＴＡＢ用フィルムに導
体回路を作製する方法としては、現在主に次の２つの方
法がとられている。１つは絶縁性基板表面に銅箔を積層
しておいて、その銅箔のうち不必要な部分をエッチング
により除去し、必要な導体パターンだけを残して作製す
る、いわゆるサブトラクティブ法である。もう１つは絶
縁性基板表面に例えば無電解メッキに対する触媒活性層
を所定の回路形状に設けておき、その後で銅メッキを施
して、導体パターン部だけに導電性材料を析出固着させ
ることにより回路を作製する、いわゆるアディティブ法
である。2. Description of the Related Art At present, the following two methods are mainly used to fabricate conductive circuits on printed wiring boards and TAB films. One is the so-called subtractive method, in which copper foil is laminated on the surface of an insulating substrate, and unnecessary portions of the copper foil are removed by etching, leaving only the necessary conductor pattern. The other method is to provide a catalytic active layer for electroless plating on the surface of an insulating substrate in a predetermined circuit shape, and then apply copper plating to deposit and fix a conductive material only on the conductor pattern. This is a so-called additive method.
【０００３】0003
【発明が解決しようとする課題】しかしながら、上記２
つの方法とも多くの問題を有しており、回路の現在以上
の微細化が困難な状況にある。[Problem to be solved by the invention] However, the above 2
Both methods have many problems, making it difficult to miniaturize circuits any further than currently available.
【０００４】その原因として、■どちらの方法もレジス
トを用いるためレジストの解像度により回路の微細化の
限界が決まる、■レジストと基板との密着力、あるいは
レジストの耐薬品性が十分でなく微細なエッチングがで
きない、■ゴミなどの異物がレジストに混入するか、ま
たはレジスト表面に付着した場合には回路に欠点が生ず
る原因となり、回路が微細であればあるほど歩留りが低
下する、などの点があげられる。いずれにせよ、回路の
微細化を阻んでいる根本原因のひとつは回路の製造過程
でレジストを使用している点にある。The reasons for this are: (1) both methods use a resist, so the resolution of the resist determines the limit of circuit miniaturization, (2) the adhesion between the resist and the substrate, or the chemical resistance of the resist is insufficient, resulting in Etching is not possible; ■ If foreign matter such as dust gets into the resist or adheres to the resist surface, it can cause defects in the circuit, and the finer the circuit, the lower the yield. can give. In any case, one of the fundamental causes that is hindering circuit miniaturization is the use of resist in the circuit manufacturing process.
【０００５】また、従来は導体回路の微細化・高密度化
に対応するため、導体回路の銅層を薄くすることがしば
しば行われてきた。例えば、サブトラクティブ法の場合
、導体幅／導体厚の値が１以下となるような場合には、
著しいサイドエッチングが生じてしまうが、導体回路の
銅層を薄くすることでこれを防止できる。また、アディ
ティブ法の場合、回路幅が微細になると積みあげられた
メッキ層から瘤がつき出して回路の配線間が短絡する可
能性があるが、導体回路の銅層が薄ければ瘤はあまり成
長せず、回路間の短絡の危険性を減少させることができ
る。[0005] Conventionally, in order to cope with miniaturization and higher density of conductor circuits, the copper layer of conductor circuits has often been made thinner. For example, in the case of the subtractive method, if the value of conductor width/conductor thickness is less than 1,
Although significant side etching occurs, this can be prevented by thinning the copper layer of the conductor circuit. In addition, in the case of the additive method, when the circuit width becomes finer, bumps may protrude from the accumulated plating layers and cause a short circuit between the circuit wiring, but if the copper layer of the conductive circuit is thin, bumps will be less likely to occur. growth, reducing the risk of short circuits between circuits.
【０００６】しかしながら、導体回路の銅層を薄くする
と回路配線の断面積が減少することになり、このことが
回路配線の高抵抗化・電流容量の低下を招き、逆に微細
化に限界を設ける結果となってしまっていた。However, when the copper layer of the conductor circuit is made thinner, the cross-sectional area of the circuit wiring decreases, which leads to higher resistance and lower current capacity of the circuit wiring, and conversely puts a limit on miniaturization. That was the result.
【０００７】微細化に伴う他の問題点は、導体回路と基
板との接合面積の減少による密着力の絶対値の減少と、
耐薬品性、耐熱性及び耐湿性の低下である。このため後
工程である錫メッキ工程や、ＩＣとのボンディング時に
導体回路が剥がれたり、長期信頼性が低下したりすると
いった問題点があった。Other problems associated with miniaturization include a decrease in the absolute value of adhesion due to a decrease in the bonding area between the conductor circuit and the substrate;
This is a decrease in chemical resistance, heat resistance, and moisture resistance. For this reason, there have been problems such as peeling of the conductor circuit during the subsequent tin plating process or bonding with the IC, and deterioration of long-term reliability.
【０００８】本発明の目的はこのような状況に鑑み、微
細でありながら信頼性・電気特性に優れた導体回路を製
造する方法を提供することにある。SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a method for manufacturing a conductor circuit that is fine but has excellent reliability and electrical characteristics.
【０００９】[0009]
【課題を解決するための手段】本発明では、絶縁基板上
の導体回路となるべき部分に溝を形成し、この溝を含む
前記絶縁基板表面に導電性を付与したのち、前記溝部分
を含む前記絶縁基板上にメッキを行って前記溝部を導体
で埋め、次いで基板表面導体層の不要な部分をエッチン
グにより除去して前記溝部の導体上部を露出させ、しか
る後、前記絶縁基板をエッチングにより少なくとも部分
的に減肉除去して溝部導体を前記絶縁基板表面から所望
の高さだけ露出させて導体回路を形成することにより上
記の課題を達成している。[Means for Solving the Problems] In the present invention, a groove is formed in a portion of an insulating substrate that is to become a conductor circuit, and after imparting conductivity to the surface of the insulating substrate including the groove, the surface of the insulating substrate including the groove portion is The insulating substrate is plated to fill the groove with a conductor, the unnecessary portion of the conductor layer on the surface of the substrate is removed by etching to expose the upper part of the conductor in the groove, and then the insulating substrate is etched to at least The above-mentioned problem is achieved by partially reducing the thickness and exposing the groove conductor by a desired height from the surface of the insulating substrate to form a conductor circuit.
【００１０】本発明を適用した回路の製造方法の一例を
示した図面を参照して詳細な説明を行う。A detailed explanation will be given with reference to the drawings showing an example of a method for manufacturing a circuit to which the present invention is applied.
【００１１】先ず図１（ａ） の如く、作製する回路の
導体パターンに合わせて基板上に溝を形成する。溝はで
きる限り矩形、あるいはそれに準ずる形状の断面を有す
ることが望ましい。溝を形成する手段としてはウォータ
ージェット等による切削、ウェットエッチング、プラズ
マやレーザー等を用いるドライエッチングなどがあるが
、できる限り微細且つ矩形の溝を形成するためには、例
えばエキシマレーザー、ＹＡＧレーザーを用いたレーザ
ーエッチングの手法が最も優れている。First, as shown in FIG. 1(a), grooves are formed on the substrate in accordance with the conductor pattern of the circuit to be fabricated. It is desirable that the groove has a cross section that is as rectangular or rectangular as possible. Methods for forming grooves include cutting with a water jet, wet etching, and dry etching using plasma, laser, etc. However, in order to form grooves as fine and rectangular as possible, for example, excimer laser or YAG laser is used. The laser etching method used is the best.
【００１２】次いで図１（ｂ） の如く、溝を含む基板
表面に導電層を設ける。導電層を設ける手段としては無
電解メッキ、蒸着、スパッタリングなどがあるが十分な
る基板との密着力を得るためにはスパッタリングが好適
である。さらに図１（ｃ） の如く、電解メッキを施し
導電層を厚膜化することにより溝を導体で完全に埋める
。次に図１（ｄ） の如く、基板表面の導体層のみをエ
ッチングにより除去し、溝部の導体は残す。最後に図１
（ｅ） の如く基板表面をエッチングし、所望の厚さだ
け導体層を露出させる。このときの導体層の厚みは特に
限定されるものではない。Next, as shown in FIG. 1(b), a conductive layer is provided on the surface of the substrate including the grooves. Methods for forming the conductive layer include electroless plating, vapor deposition, and sputtering, but sputtering is preferred in order to obtain sufficient adhesion to the substrate. Further, as shown in FIG. 1(c), the grooves are completely filled with conductor by applying electrolytic plating to thicken the conductive layer. Next, as shown in FIG. 1(d), only the conductor layer on the surface of the substrate is removed by etching, leaving the conductor in the groove. Finally, Figure 1
(e) Etch the surface of the substrate to expose the conductor layer to a desired thickness. The thickness of the conductor layer at this time is not particularly limited.
【００１３】[0013]
【作用】本発明によれば導体層をエッチングして回路を
作製する方法と異なり、回路の導体パターンに合わせて
基板上に溝を形成し、該溝を導体で埋め、しかるのち基
板をエッチングして導体を露出させるので、回路導体の
厚さを幅に比べ十分厚くすることができ、さらにその回
路導体が絶縁基板に半埋め込み状態で形成されるため、
回路幅が細くても十分な接合面積が得られる。[Operation] According to the present invention, unlike the method of fabricating a circuit by etching a conductor layer, a groove is formed on the substrate in accordance with the conductor pattern of the circuit, the groove is filled with a conductor, and then the substrate is etched. Since the conductor is exposed through the insulating substrate, the thickness of the circuit conductor can be made sufficiently thicker than the width.Furthermore, since the circuit conductor is formed semi-embedded in the insulating substrate,
Sufficient bonding area can be obtained even if the circuit width is narrow.
【００１４】[0014]
【実施例】以下に本発明の方法をＴＡＢ用フィルムの回
路作製に適用した場合について説明する。EXAMPLES The following describes the case where the method of the present invention is applied to the production of circuits on TAB films.
【００１５】まず、エキシマレーザー（ラムダフィジッ
ク社製、波長：２４８ｎｍ）のビーム（約２ｃｍ×１ｃ
ｍ）を、石英ガラス上にＣｒを蒸着した後、Ｃｒ層を導
体回路状にエッチングして作製したマスクと集光レンズ
等の光学系を介して、約１／２に縮小した回路像をステ
ージ上に固定したポリイミドフィルム（絶縁基板）１（
商品名ＮＯＶＡＸ：三菱化成株式会社製）に照射した。
この時１パルス当りのエネルギー密度はフィルム上にお
いて約１Ｊ／ｃｍ２ であり、エッチングレートは約０
．２μｍ／パルスであった。大面積をエッチングする必
要がある場合にはマスク及びステージを移動させ上記の
エッチングを繰り返して回路の導体パターンの形状に溝
２を形成した（図１（ａ） に示す）。First, a beam of excimer laser (manufactured by Lambda Physics, wavelength: 248 nm) (approximately 2 cm x 1 c
After depositing Cr on quartz glass, a circuit image reduced to about 1/2 is placed on a stage through a mask made by etching the Cr layer into a conductor circuit shape and an optical system such as a condensing lens. Polyimide film (insulating substrate) 1 fixed on top (
(trade name NOVAX: manufactured by Mitsubishi Kasei Corporation) was irradiated. At this time, the energy density per pulse is approximately 1 J/cm2 on the film, and the etching rate is approximately 0.
．． It was 2 μm/pulse. When it was necessary to etch a large area, the mask and stage were moved and the above etching was repeated to form grooves 2 in the shape of the conductor pattern of the circuit (as shown in FIG. 1(a)).
【００１６】なお、本実施例においてはマスクを使用し
ているが、レーザービームを実際の回路線幅に絞り、マ
スクを介さず直接フィルムに照射して導体回路状の溝を
形成することも可能である。この場合、ステージを移動
、あるいはビームを走査しながらエッチングすることに
より、所望のパターンの溝を形成できる。Although a mask is used in this example, it is also possible to narrow the laser beam to the actual circuit line width and irradiate the film directly without using a mask to form conductor circuit-shaped grooves. It is. In this case, grooves with a desired pattern can be formed by etching while moving the stage or scanning the beam.
【００１７】このようにレーザーにより溝を形成する場
合には、導体回路の製造工程中にレジストを使用する必
要がないので、微細な回路を高精度に作製でき、かつ導
体回路の製造工程数を削減できる。When grooves are formed using a laser in this way, it is not necessary to use a resist during the manufacturing process of the conductive circuit, so that fine circuits can be manufactured with high precision and the number of manufacturing processes of the conductive circuit can be reduced. It can be reduced.
【００１８】さて、本実施例における回路形成用の絶縁
基板としては、実施例中で使用したポリイミドフィルム
の他に、フッ素樹脂フィルム（いわゆるテフロンフィル
ム）、シリコン樹脂フィルム、ポリエチレンフィルム、
ポリプロピレンフィルム、ガラスエポキシフィルム等が
好ましく用いられるが、耐熱性、耐薬品性、寸法安定性
等の点からポリイミドフィルムが特に好ましい。Now, in addition to the polyimide film used in the example, the insulating substrate for circuit formation in this example includes a fluororesin film (so-called Teflon film), a silicone resin film, a polyethylene film,
Polypropylene film, glass epoxy film, etc. are preferably used, but polyimide film is particularly preferred from the viewpoint of heat resistance, chemical resistance, dimensional stability, etc.
【００１９】また、基板に溝を形成する方法としては、
ウォータージェット等による切削、ウェットエッチング
、プラズマやレーザー等を用いるドライエッチングなど
があげられるが、できる限り微細且つ矩形の溝を形成す
るためには、例えばエキシマレーザー、ＹＡＧレーザー
などを用いるレーザーエッチングの手法を使用すること
が好ましい。[0019] Furthermore, as a method for forming grooves on a substrate,
Examples include cutting with a water jet, wet etching, and dry etching using plasma or laser. However, in order to form as fine and rectangular grooves as possible, laser etching using excimer laser, YAG laser, etc. is recommended. It is preferable to use
【００２０】本実施例において、基板に設けた溝の最小
線幅は２５μｍ、深さ約５０μｍであった。次にその上
から銅をスパッタしてフィルムと溝との表面に厚さ０．
２μｍの銅層３を形成して導電性を与えた（図１（ｂ）
）。本実施例では、導通を付与するにあたって、銅を
スパッタする方法を用いたが、その他無電解メッキ、蒸
着などの方法も用いることができる。In this example, the minimum line width of the groove provided in the substrate was 25 μm and the depth was approximately 50 μm. Next, copper is sputtered onto the surface of the film and the groove to a thickness of 0.
A 2 μm thick copper layer 3 was formed to provide conductivity (Figure 1(b)
). In this embodiment, a method of sputtering copper was used to provide conductivity, but other methods such as electroless plating and vapor deposition may also be used.
【００２１】次いで、厚さ約２５μｍの電解銅メッキを
行い、溝を完全に銅メッキ（導体）４で埋めた（図１（
ｃ） ）。続いて塩化第２鉄溶液でフィルム表面の銅を
回路の形が現われるまでエッチングした（図１（ｄ）
）。最後に８Ｎの水酸化カリウム溶液でフィルムを回路
側から２５μｍエッチングして、高さ２５μｍだけ回路
をフィルムから露出させた（図１（ｅ） ）。この結果
、幅２５μｍ、厚さ５０μｍ（露出２５μｍ）のほぼ矩
形の断面形状を有する回路が一箇所の欠陥もなく作製で
きた。Next, electrolytic copper plating was applied to a thickness of about 25 μm, and the groove was completely filled with copper plating (conductor) 4 (see FIG. 1).
c) ). Next, the copper on the film surface was etched with a ferric chloride solution until the circuit shape appeared (Figure 1(d)).
). Finally, the film was etched 25 μm from the circuit side using an 8N potassium hydroxide solution to expose the circuit to a height of 25 μm from the film (FIG. 1(e)). As a result, a circuit having a substantially rectangular cross-sectional shape with a width of 25 μm and a thickness of 50 μm (exposure of 25 μm) was fabricated without a single defect.
【００２２】なお、前述の方法で、銅をスパッタする代
りに、銀ペーストなどのペーストを塗布し、無電解メッ
キを行って溝を完全に銅メッキで埋めたあと銅層をエッ
チングし、次にペーストを物理的手段で取り除き、最後
に基板をエッチングすることにより回路をフィルムから
露出させてもよい。Note that in the above method, instead of sputtering copper, a paste such as silver paste is applied, electroless plating is performed to completely fill the groove with copper plating, and then the copper layer is etched. The paste may be removed by physical means and the circuitry may be exposed from the film by finally etching the substrate.
【００２３】（比較例）ポリイミドフィルム上に銅層を
マグネトロンスパッタリングにより形成させて、この銅
層表面に所望のパターン形状のフォトレジストを設けた
。続いて、温度４０℃の銅エッチング液（塩化第２鉄水
溶液）にて銅層をエッチングし、実施例と同様の銅回路
を形成した。次に、アセトンによりフォトレジストを除
去した。(Comparative Example) A copper layer was formed on a polyimide film by magnetron sputtering, and a photoresist having a desired pattern was provided on the surface of the copper layer. Subsequently, the copper layer was etched with a copper etching solution (ferric chloride aqueous solution) at a temperature of 40° C. to form a copper circuit similar to that in the example. Next, the photoresist was removed using acetone.
【００２４】次に、前記実施例及び比較例の導体の剥離
強度を測定した。実施例において作製したＴＡＢ用フィ
ルムにおいては、比較例で作製した従来のＴＡＢ用フィ
ルムに比べ約３倍の剥離強度を示した。また、両者につ
いて回路表面に無電解錫メッキを０．６μｍ施し、剥離
強度を再度測定したが、実施例において作製したＴＡＢ
用フィルムのみ剥離強度の低下が見られなかった。さら
にまた、両者を１５０℃及び８５℃、８５％ＲＨの環境
下に１０００時間放置したところ、比較例のＴＡＢ用フ
ィルムの剥離強度低下はそれぞれ４３％、２７％であっ
たが、実施例のＴＡＢ用フィルムは１４％、５％となり
、大幅な改善が見られた。Next, the peel strengths of the conductors of the above examples and comparative examples were measured. The TAB film produced in the example had a peel strength about three times that of the conventional TAB film produced in the comparative example. In addition, electroless tin plating of 0.6 μm was applied to the circuit surface of both, and the peel strength was measured again.
No decrease in peel strength was observed only in the film for use with the film. Furthermore, when both were left in an environment of 150°C and 85°C and 85% RH for 1000 hours, the peel strength of the TAB film of the comparative example was 43% and 27%, respectively, but the TAB film of the example The percentage of film used for this purpose was 14% and 5%, a significant improvement.
【００２５】なお、上記の実施例では、ＴＡＢ用フィル
ムに用いられる回路の作製方法について説明したが、本
発明の方法は、フレキシブルプリント配線板やリジッド
プリント配線板にも適用可能であることは言うまでもな
く、その場合にはそれぞれの配線板に応じた基板材料を
選択すればよい。[0025] In the above example, a method for manufacturing a circuit used in a TAB film was explained, but it goes without saying that the method of the present invention can also be applied to flexible printed wiring boards and rigid printed wiring boards. In that case, the substrate material may be selected according to each wiring board.
【００２６】[0026]
【発明の効果】以上の説明からわかるように、本発明に
よれば従来法では難しかった微細回路を容易に作製でき
る。As can be seen from the above description, according to the present invention, it is possible to easily fabricate fine circuits that were difficult to produce using conventional methods.
【００２７】また、回路が半埋め込み状の形で形成でき
るので接合面積が増大し、導体回路の機械的強度のみな
らず、従来問題となっていた錫メッキなどの後工程での
耐薬品性、耐熱性及び耐湿性をも向上させることができ
る。さらに、これまでは導体回路の微細化に伴って必然
的に導体回路の断面積が減少してしまっていたが、本発
明においては線幅に比べ導体厚を厚くできるので、これ
によって導体回路断面積を増大させることが可能である
。従って、導体回路断面積の減少による導体の高抵抗化
、電流容量の減少という問題を解決することができる。
以上のように本発明の実用的価値は極めて高いものであ
る。In addition, since the circuit can be formed in a semi-embedded form, the bonding area increases, which not only improves the mechanical strength of the conductor circuit, but also improves chemical resistance in post-processes such as tin plating, which has been a problem in the past. Heat resistance and moisture resistance can also be improved. Furthermore, up until now, the cross-sectional area of conductor circuits has inevitably decreased as the conductor circuits have become finer, but in the present invention, the conductor thickness can be made thicker than the line width. It is possible to increase the area. Therefore, it is possible to solve the problems of increased resistance of the conductor and decreased current capacity due to a reduction in the cross-sectional area of the conductor circuit. As described above, the practical value of the present invention is extremely high.
【図１】（ａ） 〜（ｅ） は、本発明を適用した回路
の製造工程を示す図である。FIGS. 1A to 1E are diagrams showing the manufacturing process of a circuit to which the present invention is applied.
１ 絶縁基板 ２ 溝 ４ 導体 1 Insulating substrate 2 groove 4 Conductor
Claims (1)
に溝を形成し、この溝を含む前記絶縁基板表面に導電性
を付与したのち、前記溝部分を含む前記絶縁基板上にメ
ッキを行って前記溝部を導体で埋め、次いで基板表面導
体層の不要な部分をエッチングにより除去して前記溝部
の導体上部を露出させ、しかる後、前記絶縁基板をエッ
チングにより少なくとも部分的に減肉除去して溝部導体
を前記絶縁基板表面から所望の高さだけ露出させること
を特徴とする回路の製造方法。1. Forming a groove in a portion of an insulating substrate that is to become a conductive circuit, imparting conductivity to the surface of the insulating substrate including the groove, and plating the insulating substrate including the groove portion. filling the groove with a conductor, then removing an unnecessary portion of the substrate surface conductor layer by etching to expose the upper part of the conductor in the groove, and then removing at least a portion of the insulating substrate by etching. A method for manufacturing a circuit, comprising exposing the groove conductor to a desired height from the surface of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41130190A JPH04217386A (en) | 1990-12-18 | 1990-12-18 | Manufacture of circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41130190A JPH04217386A (en) | 1990-12-18 | 1990-12-18 | Manufacture of circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04217386A true JPH04217386A (en) | 1992-08-07 |
Family
ID=18520319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41130190A Pending JPH04217386A (en) | 1990-12-18 | 1990-12-18 | Manufacture of circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04217386A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153522A (en) * | 1997-10-19 | 2000-11-28 | Fujitsu Limited | Semiconductor device manufacturing method |
-
1990
- 1990-12-18 JP JP41130190A patent/JPH04217386A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153522A (en) * | 1997-10-19 | 2000-11-28 | Fujitsu Limited | Semiconductor device manufacturing method |
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