JPH04214619A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04214619A JPH04214619A JP40200890A JP40200890A JPH04214619A JP H04214619 A JPH04214619 A JP H04214619A JP 40200890 A JP40200890 A JP 40200890A JP 40200890 A JP40200890 A JP 40200890A JP H04214619 A JPH04214619 A JP H04214619A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- rta
- substrate
- heat treatment
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000010408 film Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 17
- 238000010438 heat treatment Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052709 silver Inorganic materials 0.000 abstract description 6
- 239000004332 silver Substances 0.000 abstract description 6
- 229910004205 SiNX Inorganic materials 0.000 abstract description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 17
- 239000013078 crystal Substances 0.000 description 12
- 239000000370 acceptor Substances 0.000 description 9
- 230000007423 decrease Effects 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000103 photoluminescence spectrum Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 108091006149 Electron carriers Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体基板の所定の部
分のみをＲＴＡの熱処理を行ない、集積度の高い集積回
路なども特性よく作製できる製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method that performs RTA heat treatment on only a predetermined portion of a semiconductor substrate, thereby making it possible to manufacture highly integrated circuits with good characteristics.
【０００２】0002
【従来の技術】近年、種々のトランジスタ、及び、それ
による集積回路等の半導体デバイスに対して、より高周
波領域での使用を可能にすること、又は、高速の動作を
可能にすることなどの要求が高くなっている。[Background Art] In recent years, there has been a demand for various transistors and semiconductor devices such as integrated circuits made using the transistors to be able to be used in higher frequency ranges or to be able to operate at higher speeds. Is high.
【０００３】以上の要求に対応して、半導体デバイスの
微細化が進められており、すでに最小寸法１μｍ程度の
シリコンＬＳＩは広く実用化されている。このような微
細化の技術は、さらに１μｍ以下のサブミクロンの製造
技術へと発展している。又、一方ではシリコン（Ｓｉ）
以外の半導体材料を用いたデバイスも作製されている。In response to the above requirements, miniaturization of semiconductor devices is progressing, and silicon LSIs with a minimum dimension of about 1 μm have already been widely put into practical use. Such miniaturization technology has further developed into submicron manufacturing technology of 1 μm or less. On the other hand, silicon (Si)
Devices using other semiconductor materials have also been fabricated.
【０００４】高速・高周波のデバイス作製に適した半導
体材料は、電子移動度や飽和ドリフト速度などが大きく
なくてはならない。以上の条件に合う代表的半導体に通
常ガリウムヒ素と呼ばれているヒ化ガリウム（ＧａＡｓ
）がある。Semiconductor materials suitable for manufacturing high-speed, high-frequency devices must have high electron mobility and saturation drift velocity. A typical semiconductor that meets the above conditions is gallium arsenide (GaAs), which is commonly called gallium arsenide.
).
【０００５】ＧａＡｓはＩＩＩ族元素とＶ族元素からな
る化合物半導体で、次に述べるような特徴をもっている
。GaAs is a compound semiconductor consisting of group III elements and group V elements, and has the following characteristics.
【０００６】まず、高純度のＧａＡｓ結晶中の電子の移
動度は、Ｓｉ結晶中のそれより、４倍から５倍程度大き
く、又、ドリフト速度もそのピーク速度がＳｉのそれよ
り約２倍程度大きい。First, the electron mobility in a high-purity GaAs crystal is about 4 to 5 times higher than that in a Si crystal, and the peak drift velocity is about twice that of Si. big.
【０００７】しかも、ＧａＡｓ中では電子の移動度が大
きいため、電子をピーク速度にするための電界の強さは
Ｓｉ中に比べて小さい。これらの諸特性は、いずれも高
速・高周波デバイスの作製に適している。従って、本発
明では、以下、ＧａＡｓを例に用いて、その内容を説明
する。Moreover, since the mobility of electrons is high in GaAs, the strength of the electric field required to bring the electrons to their peak velocity is smaller than that in Si. All of these characteristics are suitable for manufacturing high-speed, high-frequency devices. Therefore, the present invention will be described below using GaAs as an example.
【０００８】ＧａＡｓ結晶での禁制帯幅（バンドギャッ
プ：ＥＧ）は室温で１．４３ｅＶであり、Ｓｉに比べて
大きい。また、ノンドープのＧａＡｓ結晶中でも、結晶
成長中に混入する炭素が浅いアクセプタ（ＮＡ）になる
が、これは深い準位のドナーであるＥＬ２（＝１０１６
ｃｍ−３＝ＮＤ）が補償するため、フェルミレベル（Ｅ
Ｆ）は禁制帯の中央になって、極めて高抵抗の半絶縁性
結晶になっている。以上で説明したＧａＡｓ結晶中の状
態を図示したのが図２であり、この図２で禁制帯（ＥＶ
〜ＥＣ）中のＥＦの位置とキャリア濃度の関係を示して
おり、上記の条件では正孔キャリア濃度のｐ＋ＮＤ＋と
電子キャリア濃度ｎ＋ＮＡ−が同じ大きさになる両曲線
の交点（ＥＦ）に対応して抵抗率が最大のρ１になって
いる。The forbidden band width (band gap: EG) of GaAs crystal is 1.43 eV at room temperature, which is larger than that of Si. Also, even in non-doped GaAs crystals, carbon mixed during crystal growth becomes a shallow acceptor (NA), which is a deep level donor EL2 (=1016
cm-3=ND), the Fermi level (E
F) is the center of the forbidden band and is a semi-insulating crystal with extremely high resistance. FIG. 2 illustrates the state in the GaAs crystal explained above, and in this FIG.
~EC) shows the relationship between the position of EF and the carrier concentration. Under the above conditions, it corresponds to the intersection point (EF) of both curves where the hole carrier concentration p+ND+ and the electron carrier concentration n+NA- are the same size. The resistivity is the maximum value ρ1.
【０００９】以上のようなＧａＡｓの半絶縁性結晶基板
にデバイスを作製すれば、寄生容量を低減でき、素子間
の分離が容易になる。一方、以上のような半絶縁性基板
上にトランジスタや集積回路を作製するときは、基板表
面に能動層を形成することになり、能動層をイオン注入
で形成している。この場合、イオン注入後に注入した不
純物イオンの活性化を図るためアニールを行っている。
このアニールも、赤外線などの短時間ランプアニール（
ＲＴＡ）により迅速に、しかも、均一に行うことが可能
になっている。[0009] If a device is fabricated on the GaAs semi-insulating crystal substrate as described above, parasitic capacitance can be reduced and isolation between elements can be facilitated. On the other hand, when manufacturing a transistor or an integrated circuit on a semi-insulating substrate as described above, an active layer is formed on the surface of the substrate, and the active layer is formed by ion implantation. In this case, annealing is performed after ion implantation to activate the implanted impurity ions. This annealing also includes short-time lamp annealing (such as infrared rays)
RTA) makes it possible to perform the process quickly and uniformly.
【００１０】0010
【発明が解決しようとする課題】前記半絶縁性ＧａＡｓ
基板のフォトルミネッセンススペクトルを示したのが図
３でありこの図３のスペクトル分布における８３００Å
付近のピークは炭素の浅いアクセプタによるものである
。図３の曲線（ｂ）は前記基板のＲＴＡによる熱処理後
の測定であり、この図の（ａ）曲線はその熱処理前の測
定である。[Problem to be solved by the invention] The semi-insulating GaAs
Figure 3 shows the photoluminescence spectrum of the substrate.
The nearby peaks are due to shallow carbon acceptors. The curve (b) in FIG. 3 is the measurement after the substrate was heat-treated by RTA, and the curve (a) in this figure is the measurement before the heat treatment.
【００１１】以上の２例の炭素アクセプタでの発光強度
から、上記の半絶縁性ＧａＡｓ基板では熱処理によりそ
のアクセプタの発光強度が約３０分の１に低下し、基板
中でのアクセプタ濃度が低下したことを示している。基
板中でのアクセプタ濃度が低下するとＥはＦ伝導帯（Ｅ
Ｃ）側にずれ、その結果として、図２に示されているよ
うに基板自体の抵抗率が低下してしまう。例えば、図２
においてアクセプタ濃度（ＮＡ−）が１０分の１になる
と、基板での抵抗率も１０分の１になりρ２になること
を示している。このような基板抵抗の低下はＲＴＡによ
る熱処理のみでなく、電気炉などによる熱処理によって
も生じている。[0011] From the emission intensity of the carbon acceptor in the above two examples, in the semi-insulating GaAs substrate described above, the emission intensity of the acceptor was reduced to about 1/30th by heat treatment, and the acceptor concentration in the substrate was reduced. It is shown that. As the acceptor concentration in the substrate decreases, E shifts to the F conduction band (E
C), and as a result, the resistivity of the substrate itself decreases as shown in FIG. For example, Figure 2
It is shown that when the acceptor concentration (NA-) becomes 1/10 in , the resistivity at the substrate also becomes 1/10 and becomes ρ2. Such a decrease in substrate resistance is caused not only by heat treatment using RTA but also by heat treatment using an electric furnace or the like.
【００１２】以上のような基板抵抗の低下は、その基板
にＩＣやＬＳＩを作製したとき、サイドゲート効果が大
きくなる等の問題を生じることになる。このような問題
は、そのＩＣ等の集積度を上げる微細加工により、素子
間の距離や、素子と配線間の距離が短くなると、より顕
著に現れてくる。[0012] The above-described decrease in substrate resistance causes problems such as increased side gate effects when ICs and LSIs are fabricated on the substrate. Such problems become more noticeable as the distance between elements and the distance between elements and wiring become shorter due to microfabrication that increases the degree of integration of ICs and the like.
【００１３】本発明は、従来のＲＴＡなどの熱処理によ
り基板全体の抵抗率を抵下させてしまうという問題を解
消するもので、基板中の必要な部分のみＲＴＡにより熱
処理する半導体装置の製造方法を提供することを目的と
している。The present invention solves the problem of lowering the resistivity of the entire substrate due to conventional heat treatment such as RTA, and provides a method for manufacturing a semiconductor device in which only necessary portions of the substrate are heat treated by RTA. is intended to provide.
【００１４】[0014]
【課題を解決するための手段】以上で説明した従来のＲ
ＴＡの工程での問題を解消する本発明の方法は、半導体
基板を赤外線ランプ光照射の加熱でアニールするとき、
その半導体基板表面のアニール処理が必要な領域（例え
ばイオン注入を行った領域）以外は、前記アニール用赤
外線ランプの赤外線に対して反射率の高い金属の薄膜を
形成しておくものである。これによって前記の金属薄膜
を形成していない領域のみにＲＴＡ処理を行なうことが
できる。[Means for solving the problem] The conventional R described above
The method of the present invention that solves problems in the TA process is such that when a semiconductor substrate is annealed by heating with infrared lamp light irradiation,
A thin metal film having a high reflectance to the infrared rays of the annealing infrared lamp is formed on the surface of the semiconductor substrate in areas other than those that require annealing (for example, areas where ions have been implanted). As a result, the RTA process can be performed only on the area where the metal thin film is not formed.
【００１５】なお、赤外線反射用の金属薄膜を半導体表
面に形成した透明な絶縁薄膜上に設けることにより、該
金属膜自体やその膜形成工程などでの汚染や、ＲＴＡ中
の熱伝導などでの問題を小さくすることができる。[0015] By providing a metal thin film for infrared reflection on a transparent insulating thin film formed on the semiconductor surface, contamination of the metal film itself or its film formation process, and heat conduction during RTA can be prevented. The problem can be made smaller.
【００１６】[0016]
【作用】以上で説明した本発明の選択的熱処理方法は、
ＲＴＡのとき、半導体基板表面の金属反射膜を設けた部
分は、赤外線が金属によって反射されるので、熱処理さ
れず抵抗率の低下を防ぐものである。[Operation] The selective heat treatment method of the present invention explained above is as follows:
At the time of RTA, infrared rays are reflected by the metal on the portion of the surface of the semiconductor substrate where the metal reflective film is provided, so that the portion is not heat-treated and a decrease in resistivity is prevented.
【００１７】又、金属膜を設けない部分は、赤外線を吸
収して温度が上昇するので、熱処理される（例えば、注
入イオンの活性化等）。すなわち、所定の形状の赤外線
反射用金属膜を設けることで、必要な部分のみ選択的に
ＲＴＡの熱処理を行うことができるものである。[0017] In addition, since the portion where the metal film is not provided absorbs infrared rays and the temperature rises, it is heat-treated (for example, by activating implanted ions). That is, by providing an infrared reflecting metal film having a predetermined shape, it is possible to selectively perform RTA heat treatment on only necessary portions.
【００１８】[0018]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
【００１９】図面は実施例の製造工程を示す断面図であ
る。まず、図１（ａ）に示したように半絶縁性ＧａＡｓ
基板１の表面上にプラズマＣＶＤ法により窒化ケイ素（
ＳｉＮＸ）膜２を０．０２μｍの厚さに堆積しこの上に
フォトレジスト液（商品名ＯＦＰＲ８００）をスピナー
による３０００ｒｐｍで３０秒の回転塗布と、９０℃で
３０分間のベークにより厚さ１μｍのフォトレジスト膜
３を形成した後、フォトリソグラィーによりイオン注入
部をマスクしたパターンに形成している。The drawings are cross-sectional views showing the manufacturing process of the embodiment. First, as shown in Fig. 1(a), semi-insulating GaAs
Silicon nitride (
A SiN After forming the resist film 3, the ion implantation portion is formed into a masked pattern by photolithography.
【００２０】次の図１（ｂ）は、以上のレジスト膜３の
マスクパターン上へ、抵抗加熱蒸発源をもつ真空蒸着装
置より０．６μｍの銀薄膜（波長２０００ｎｍの赤外光
に対する反射率は９９％）を堆積し、続いてリフトオフ
によりイオン注入用のマスクも兼用した銀薄膜のマスク
４を形成している。Next, in FIG. 1(b), a 0.6 μm thin silver film (reflectance for infrared light with a wavelength of 2000 nm is 99%) is deposited, followed by lift-off to form a thin silver film mask 4 which also serves as a mask for ion implantation.
【００２１】続いて図１（ｃ）に示したのは、イオン注
入を行ったもので、シリコン（Ｓｉ）を加速電圧５０ｋ
ｅＶで６×１０１２ｃｍ−２ドーズを前記基板１に注入
した後、前記マスク４を用いたＲＴＡ法により、９５０
℃で４秒のアニールを行いイオン注入した能動層５を形
成している。このＲＴＡのとき基板１上にマスク４を形
成した部分は照射した赤外線が反射されて加熱されない
ため熱処理されず抵抗率が低下することは少なく、マス
ク４が形成されていない部分のみ、つまり、イオン注入
した半導体表面部のみ赤外線が吸収され温度が上がって
注入イオンの活性化熱処理が行なわれている。Next, FIG. 1(c) shows a case in which ion implantation was performed, and silicon (Si) was heated at an accelerating voltage of 50k.
After implanting a dose of 6 x 1012 cm-2 at eV into the substrate 1, a 950 m
The active layer 5 is formed by annealing at .degree. C. for 4 seconds and implanting ions. During this RTA, the part where the mask 4 is formed on the substrate 1 is not heated because the irradiated infrared rays are reflected, so it is not heat treated and the resistivity is unlikely to decrease. Infrared rays are absorbed only at the surface of the implanted semiconductor, the temperature rises, and heat treatment for activating the implanted ions is performed.
【００２２】更に、次の図１（ｄ）では前記マスク４を
５％塩酸に浸漬して除去した上、ＳｉＮｘ膜２を５％の
フッ化水素酸に浸漬して除去している。Furthermore, in FIG. 1(d), the mask 4 is removed by immersing it in 5% hydrochloric acid, and the SiNx film 2 is removed by immersing it in 5% hydrofluoric acid.
【００２３】最後に図１（ｅ）に示したのは、以上でイ
オン注入した基板１の上に、従来のプレーナ半導体製造
プロセスを用いて、トランジスタ等の素子と配線を形成
して集積回路を作製した状態である。図ではショットキ
ーゲートのＦＥＴを作製しており、６が高濃度不純物層
、７は絶縁膜、８はショットキーゲート、９はオーミッ
ク電極、１０は配線を示している。Finally, as shown in FIG. 1(e), elements such as transistors and wiring are formed on the substrate 1 into which ions have been implanted in the above manner using a conventional planar semiconductor manufacturing process to form an integrated circuit. This is the state in which it was created. In the figure, a Schottky gate FET is manufactured, and 6 is a high concentration impurity layer, 7 is an insulating film, 8 is a Schottky gate, 9 is an ohmic electrode, and 10 is a wiring.
【００２４】以上のような本発明の製造方法により、熱
処理が必要なイオン注入部などはＲＴＡによる熱処理を
行い、赤外線反射マスクを設けた素子間領域などの熱処
理されない領域では前記で説明した結晶中のアクセプタ
濃度が低下しないので、その領域の抵抗率は高く保たれ
ておりサイドゲート効果などは起こりにくく、高集積化
による特性の低下を小さくすることができる。以上は、
本発明の半導体装置の製造方法を実施例で説明したが、
本発明は実施例によって限定されるものではなく、例え
ば、実施例で高反射率金属として用いた銀も、銀に限定
されることなく、反射率が高く、又、その他の条件を満
たす金属であればニッケル，クロム，又は、金等を用い
てもよい。更に、実施例の説明ではイオン注入用のマス
クをそのままＲＴＡの赤外線反射マスクに用いる工程に
したが、このマスクはそれぞれ別にして作製してもよい
。なお、異なる条件で複数のイオン注入を行うときは、
当然それぞれの目的のマスクを作製することになる。According to the manufacturing method of the present invention as described above, the ion-implanted parts that require heat treatment are heat-treated by RTA, and the regions that are not heat-treated, such as the inter-element region where the infrared reflective mask is provided, are treated with the crystal in the crystal as described above. Since the acceptor concentration of the semiconductor device does not decrease, the resistivity of the region is kept high and side gate effects are less likely to occur, making it possible to reduce the deterioration of characteristics due to high integration. The above is
Although the method for manufacturing a semiconductor device of the present invention has been explained with examples,
The present invention is not limited by the examples, and for example, silver used as a high reflectance metal in the examples is not limited to silver, but any metal that has high reflectance and satisfies other conditions. If available, nickel, chromium, or gold may be used. Further, in the description of the embodiment, a process is described in which the ion implantation mask is used as it is as an infrared reflection mask for RTA, but these masks may be manufactured separately. Note that when performing multiple ion implantations under different conditions,
Naturally, masks for each purpose will be manufactured.
【００２５】また、本発明において、使用する半導体基
板もＧａＡｓに限定されるものでなく、ＡｌＡｓやＧａ
Ｐとの混晶、又は、ＳｉやＺｎＳなどの半導体を用いる
こともできる。Furthermore, in the present invention, the semiconductor substrate used is not limited to GaAs, but may also be AlAs or Ga.
A mixed crystal with P or a semiconductor such as Si or ZnS can also be used.
【００２６】[0026]
【発明の効果】本発明による選択的赤外線反射マスクを
設けるＲＴＡによれば、熱処理の必要な部分のみを選択
的に熱処理することができる。例えば、本発明をＧａＡ
ｓ集積回路の製造に用いると、能動層以外の部分を半絶
縁性の高抵抗状態に保つことができ、サイドゲート効果
を抑制することができる。According to the RTA provided with the selective infrared reflection mask according to the present invention, only the portions that require heat treatment can be selectively heat treated. For example, the present invention can be applied to GaA
When used in the manufacture of integrated circuits, parts other than the active layer can be kept in a semi-insulating high resistance state, and side gate effects can be suppressed.
【００２７】従って、サイドゲート効果が発生する素子
や配線間の距離を短縮でき、半導体装置の高集積化、又
は、高速・高性能化を図ることができる。Therefore, the distance between elements and interconnections where the side gate effect occurs can be shortened, and it is possible to achieve higher integration, higher speed, and higher performance of the semiconductor device.
【図１】半導体装置の製造方法の工程を示した断面図で
ある。FIG. 1 is a cross-sectional view showing steps of a method for manufacturing a semiconductor device.
【図２】半絶縁性ＧａＡｓ基板のフェルミレベルと抵抗
率の関係を示す図である。FIG. 2 is a diagram showing the relationship between the Fermi level and resistivity of a semi-insulating GaAs substrate.
【図３】半絶縁性ＧａＡｓ結晶中のアクセプタ濃度とフ
ォトルミネッセンススペクトルの発光強度との関連を示
す図である。FIG. 3 is a diagram showing the relationship between the acceptor concentration in a semi-insulating GaAs crystal and the emission intensity of a photoluminescence spectrum.
１ 半絶縁性ＧａＡｓ基板
２ ＳｉＮｘ薄膜
３ レジスト膜
４ イオン注入／赤外線反射マスク５ 能
動層
６ 高濃度キャリア層
７ 絶縁膜
８ ゲート電極（ショットキー）９ オー
ミック電極
１０ 薄膜配線1 Semi-insulating GaAs substrate 2 SiNx thin film 3 Resist film 4 Ion implantation/infrared reflection mask 5 Active layer 6 High concentration carrier layer 7 Insulating film 8 Gate electrode (Schottky) 9 Ohmic electrode 10 Thin film wiring
Claims (2)
外線による急速加熱アニール（ＲＴＡ）処理を行う半導
体装置の製造において、前記ＲＴＡ処理をしない半導体
基板の表面に、該ＲＴＡ処理に用いる赤外線に高い反射
率をもつ金属膜を設けることを特徴とする半導体装置の
製造方法。1. In the manufacture of a semiconductor device in which a selected surface portion of a semiconductor substrate is subjected to rapid thermal annealing (RTA) treatment using infrared rays, the surface of the semiconductor substrate that is not subjected to the RTA treatment has a high reflectance to the infrared rays used for the RTA treatment. 1. A method of manufacturing a semiconductor device, characterized by providing a metal film having a certain ratio.
覆い、かつ、前記赤外線を透過する絶縁薄膜を介して設
けられていることを特徴とする請求項１記載の半導体装
置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film covers the entire surface of the semiconductor and is provided through an insulating thin film that transmits the infrared rays.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40200890A JPH04214619A (en) | 1990-12-13 | 1990-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40200890A JPH04214619A (en) | 1990-12-13 | 1990-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04214619A true JPH04214619A (en) | 1992-08-05 |
Family
ID=18511816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40200890A Pending JPH04214619A (en) | 1990-12-13 | 1990-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04214619A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10229642A1 (en) * | 2002-07-02 | 2004-01-29 | Infineon Technologies Ag | Method for locally heating an area arranged in a semiconductor substrate |
-
1990
- 1990-12-13 JP JP40200890A patent/JPH04214619A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10229642A1 (en) * | 2002-07-02 | 2004-01-29 | Infineon Technologies Ag | Method for locally heating an area arranged in a semiconductor substrate |
| US6900130B2 (en) | 2002-07-02 | 2005-05-31 | Infineon Technologies Ag | Method for locally heating a region in a semiconductor substrate |
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