JPH04207802A - Digital fm signal demodulator - Google Patents

Digital fm signal demodulator

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Publication number
JPH04207802A
JPH04207802A JP34027590A JP34027590A JPH04207802A JP H04207802 A JPH04207802 A JP H04207802A JP 34027590 A JP34027590 A JP 34027590A JP 34027590 A JP34027590 A JP 34027590A JP H04207802 A JPH04207802 A JP H04207802A
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JP
Japan
Prior art keywords
circuit
difference
value
digital
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34027590A
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Japanese (ja)
Inventor
Yasuo Takahashi
泰雄 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP34027590A priority Critical patent/JPH04207802A/en
Publication of JPH04207802A publication Critical patent/JPH04207802A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the threshold characteristic and at the same time to omit the highly complicated circuit adjustment for a digital signal demodulator by operating the difference between the in-phase and orthogonal components for each phase angle in order to obtain the corrected value, i.e., the differential value kept in an allowable range and securing the differential arithmetic result in an in-allowable range mode and the corrected value in an out-allowable range mode respectively. CONSTITUTION:A level deciding circuit 37 transmits a control signal to a selection circuit 37 so that the output of a subtractor circuit 35 is selected at a level lower than the reference value and then the output of a delay circuit 38 is selected at a level higher than the reference value respectively. In other words, the output value of the circuit 35 is sent as it is to a D/A converter 36 in a normal state and then the value preceding by one stage and delayed by the circuit 38 is sent to the converter 36 as the corrected value. Thus it is possible to improve the S/N of a demodulated signal with no adjustment applied to the circuit even though an FM modulated wave superposed with an impulsive noise is inputted.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) この発明はF M変調波をデジタル形式で復調するデジ
タル型F M信号復調装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a digital FM signal demodulation device that demodulates FM modulated waves in a digital format.

(従来の技術) 従来のFM信号復調装置として、第4図に示すような構
成か代表される。この装置に入力されたF M変調波S
INは、IF分配器11て2系統に分配され、それぞれ
中心周波数f、、f2の同調回路12..122に導か
れる。各同調回路121.12□はそれぞれ第2図(a
)に示すような周波数特性を有する。foはF M変調
波Sいの搬送波周波数であ・る。各同調回路12+、’
l’22で得られた周波数信号は検波ダイオード13.
(Prior Art) A typical example of a conventional FM signal demodulator is the configuration shown in FIG. FM modulated wave S input to this device
IN is divided into two systems by the IF distributor 11, and tuned circuits 12 . . . with center frequencies f, f2. .. I am led to 122. Each tuning circuit 121.12□ is shown in Figure 2 (a).
) has the frequency characteristics shown in fo is the carrier frequency of the FM modulated wave S. Each tuned circuit 12+,'
The frequency signal obtained at l'22 is passed through the detection diode 13.
.

132で互いに逆極性を持って検波され、加算器14て
加算される。すなわち、この加算器14は、第5図に示
すような8字復調特性を持つことになる。加算器14の
出力は低域フィルタ15で不要な高周波成分を除去され
、FM復調信号S。U7として出力される。但し、この
方式は回路が簡易な反面、同調回路のバランス、検波器
の非直線性の影響を受けるため、良好な復調特性を得る
ことが困難であるという欠点を有している。
The signals are detected with opposite polarities at 132, and added at adder 14. That is, this adder 14 has a character-8 demodulation characteristic as shown in FIG. The output of the adder 14 is filtered by a low-pass filter 15 to remove unnecessary high frequency components, and is then converted into an FM demodulated signal S. It is output as U7. However, although this method has a simple circuit, it has the disadvantage that it is difficult to obtain good demodulation characteristics because it is affected by the balance of the tuning circuit and the nonlinearity of the detector.

一方、第6図に示すように、−FM変調波SINを矩形
波変換器21て矩形波に変換し、そのエツジで単安定マ
ルチバイブレータ22を動作させ、第7図に示すような
一定幅の粗密パルス列を生成し、低域フィルタ23で直
流成分を取り出す方式が実用化されている。尚、第7図
(a)は変調信号の波形、同図(b)は搬送波信号を(
a)図の変調信号によってF M変調した場合のF M
変調波Sいの波形、同図(c)は矩形波変換器21の出
力波形、同図(d)は単安定マルチバイブレータ22の
8カ波形、同図(e)は低域フィルタ23の出力波形(
SQLIT)を示している。この方式は回路構成が簡単
なものの、入力信号SINの周波数に比べて相当高い周
波数で動作するデジタル集子が必要なこと、矩形波変換
器21、単安定マルチバイブレータ22がアナログ動作
のため、回路調整が必要で、しかも温度変化の影響を受
けやすい等の欠点を有している。
On the other hand, as shown in FIG. 6, the -FM modulated wave SIN is converted into a rectangular wave by the rectangular wave converter 21, and the monostable multivibrator 22 is operated at the edge of the rectangular wave, so that a constant width wave as shown in FIG. A method has been put into practical use in which a coarse pulse train is generated and a DC component is extracted by a low-pass filter 23. In addition, FIG. 7(a) shows the waveform of the modulation signal, and FIG. 7(b) shows the carrier wave signal (
a) FM when FM modulated by the modulation signal shown in the figure
The waveform of the modulated wave S, (c) is the output waveform of the rectangular wave converter 21, (d) is the 8 waveform of the monostable multivibrator 22, and (e) is the output of the low-pass filter 23. Waveform(
SQLIT). Although this method has a simple circuit configuration, it requires a digital collector that operates at a considerably higher frequency than the frequency of the input signal SIN, and the rectangular wave converter 21 and monostable multivibrator 22 operate as analog circuits. It has drawbacks such as requiring adjustment and being susceptible to temperature changes.

ところが、近年、A/D変換器の高速化に伴って、第8
図に示すようなデジタル型F M信号復調装置が提案さ
れている。この装置では、入力F M変調波SINは、
ハイブリッド分配器31に導がれ、ここで同相成分(0
°)と直交成分(90’)に分配された後、それぞれA
/D変換器321゜322でデジタル信号に変換されて
逆正接回路(位相角演算器)33に入力される。この逆
正接回路33は、A/D変換後のデータよりサンプリン
グ時点の同相成分をsinθ、直交成分をCOSθとし
てとらえ、tan−’θを演算することにより位相角θ
(1)を求めるものである。
However, in recent years, as the speed of A/D converters has increased,
A digital FM signal demodulator as shown in the figure has been proposed. In this device, the input FM modulated wave SIN is
The in-phase component (0
°) and orthogonal component (90'), respectively.
The signal is converted into a digital signal by /D converters 321 and 322 and input to an arctangent circuit (phase angle calculator) 33. This arctangent circuit 33 takes the in-phase component at the time of sampling as sin θ and the orthogonal component as COS θ from the data after A/D conversion, and calculates the phase angle θ by calculating tan-'θ.
(1) is sought.

n番目のサンプル値S。と一つ前のサンプル値S n−
1の各位相角θ。、θ。−1を第9図に示す。
nth sample value S. and the previous sample value S n−
Each phase angle θ of 1. , θ. -1 is shown in FIG.

SoとS I+−1との間のf。はnサンプル目の周波
数を表し、 f、−dθ/dt−Δθ/Δt −(θ。−θ。−1)/T である。
f between So and S I+-1. represents the frequency of the n-th sample, f, -dθ/dt-Δθ/Δt-(θ.-θ.-1)/T.

上記逆正接回路33の出力は、1サンプル遅延回路34
、及び減算回路342による微分回路34に送られる。
The output of the arctangent circuit 33 is transmitted to the 1-sample delay circuit 34.
, and to the differentiation circuit 34 by the subtraction circuit 342.

この微分回路34は入力した位相角データθ(T、)を
遅延回路341て1サンプル分遅延しくθ(”rfi−
、) )、減算回路342で遅延前後の値を減算して、
その変化分子(T、)(−θ(T、)−θ(’r、−,
))を求めるものである。この微分回路34の8力は、
減算回路35で搬送波固有の周波数成分を除去された後
、D/A変換器36てアナログ信号に変換され、FM復
調信号S。LITとして出力される。この方式は、前記
の2方式に比べ、全ての信号処理がデジタルであるため
、動作の安定性、復調特性の点で優れている。
This differentiating circuit 34 delays input phase angle data θ(T,) by one sample through a delay circuit 341.
, ) ), the subtraction circuit 342 subtracts the values before and after the delay,
The change molecule (T,)(-θ(T,)-θ('r,-,
)). The 8 forces of this differential circuit 34 are:
After a frequency component unique to the carrier wave is removed by a subtraction circuit 35, the signal is converted into an analog signal by a D/A converter 36, and the FM demodulated signal S is converted into an analog signal. Output as LIT. This method is superior to the above two methods in terms of operational stability and demodulation characteristics because all signal processing is digital.

さらに具体的に説明するに、入力信号Sいを次のように
定義する。
To explain more specifically, the input signal S is defined as follows.

S IN−sin ((JJO+Δω)  t    
−(1)但し、ω。:搬送周波数 Δω:変調信号による周波数変化分 この場合、逆正接回路33の出力は、 (ω0+Δω)t        ・・・(2)と与え
られる。ここで、A/D変換器321゜322のサンプ
リング時刻をTo、T、、  。
S IN-sin ((JJO+Δω) t
-(1) However, ω. : Carrier frequency Δω: Frequency change due to modulation signal In this case, the output of the arctangent circuit 33 is given as (ω0+Δω)t (2). Here, the sampling times of the A/D converters 321 and 322 are To, T, .

Tll、その間隔をΔTとすると、逆正接回路33の出
力は θ(T、)、  θ(T+ )、”’、  θ(T、、
)・・・(3) で与えられる。但し、θ(T)は時刻Tにおける入力信
号の位相角を表す。したがって、微分回路34の出力は
Sa  (T)は次式で与えられる。
Tll, and the interval is ΔT, the outputs of the arctangent circuit 33 are θ(T,), θ(T+), "', θ(T,,
)...(3) is given by. However, θ(T) represents the phase angle of the input signal at time T. Therefore, the output of the differentiating circuit 34, Sa (T), is given by the following equation.

5B(T、)−θ (T、)  −θ +’、T、−,
)−(ω。+Δω)IT、−+ 十ΔT)−(ω0 〒
ΔωIT、。
5B(T,)-θ (T,)-θ +', T,-,
)−(ω.+Δω)IT, −+ 1ΔT)−(ω0 〒
ΔωIT,.

一ω0 ・ ΔT±Δω ・ ΔT      −・ 
(4)り4)式中第1項は、搬送周波数成分による位相
角変化量を示す。ω。、ΔTは一定値であり、定数とな
る。したがって、減算回路35てω。・ΔTを減しるこ
とにより、変調信号に比例した成分Δω・△T(八Tは
定数)を取り出すことができる。
-ω0 ・ΔT±Δω ・ΔT −・
(4) The first term in equation (4) indicates the amount of phase angle change due to the carrier frequency component. ω. , ΔT are constant values and become constants. Therefore, the subtraction circuit 35 has ω. - By reducing ΔT, a component Δω·ΔT (8T is a constant) proportional to the modulation signal can be extracted.

しかしながら、上記FM信号復調装置は、スレッシュホ
ールドレベル(C/Nが106B : Cはキャリア、
Nはノイズ)以下で復調S/Nか急激に低下する問題を
有している。これは、入力FM変調波に搬送波レベルを
越す雑音が乗った場合に、位相角の急激な変化か生じ、
インパルス性雑音となる。第10図(a)にC/Nが大
きい(S/Nが小さい)場合、同図(b)にC、、/ 
Nか小さい(S/Nが大きい)場合を示す。
However, the above FM signal demodulator has a threshold level (C/N of 106B: C is carrier,
There is a problem in that the demodulation S/N rapidly decreases below the threshold (N is noise). This occurs when a noise exceeding the carrier level is added to the input FM modulated wave, causing a sudden change in the phase angle.
It becomes an impulsive noise. When the C/N is large (S/N is small) in Fig. 10(a), the Fig. 10(b) shows C, , /
The case where N is small (S/N is large) is shown.

すなわち、通信回線の雑音は主として熱雑音てあり、そ
の振幅分布はガウス分布に従う。よって、C/N10d
B以下で上記現象、?1顕著と−る。これはF M通信
方式に固をの現象であり、北aa Z’<置のみならす
、第4図、第6図に示すいずれの復調装置でも差はない
That is, the noise in the communication line is mainly thermal noise, and its amplitude distribution follows a Gaussian distribution. Therefore, C/N10d
The above phenomenon occurs below B? 1 is remarkable. This is a phenomenon specific to the FM communication system, and there is no difference between the demodulators shown in FIGS.

ここで、上記問題点を改善下る方式としで、F Mフィ
ードバック(FMFB)方式や位相同期検出(P L 
D : Phase Lock Detec、tor 
)方式等ρ・提案されているが、いずれも局部発振周波
数をF M信号中の変調成分に追随させることにより、
見掛上IF倍信号周波数偏移位置を下げ、帯域フィルタ
を狭帯域化してC/Nを向上させることを特徴としてい
る。しかしなから、この様な方式であっても、復調直線
性か局部発振器として利用する電圧制御発振器(V C
O)の変調直線性に依存すること、変調周波数特性かル
ープの周波数特性に依存するため、特性の調整に多大な
労力か必要となってしまう。
Here, as a method to improve the above problems, FM feedback (FMFB) method and phase synchronization detection (PL
D: Phase Lock Detect, tor
) method etc. have been proposed, but in both cases, by making the local oscillation frequency follow the modulation component in the FM signal,
It is characterized by lowering the apparent IF multiplied signal frequency deviation position and narrowing the bandpass filter to improve the C/N. However, even with this type of system, demodulation linearity or voltage controlled oscillator (V C
Since it depends on the modulation linearity of O), the modulation frequency characteristic, or the frequency characteristic of the loop, a great deal of effort is required to adjust the characteristic.

(発明か解決しようとする課題) 以上述べたように従来のデジタル型FN11工号復調装
置では、スレッシュホールドレベル以下で復調S/Nか
急激に低下するというF M通信方式固有の問題や高度
かつ複雑な回路調整を必要とする問題を有している。
(Problems to be Solved by the Invention) As mentioned above, the conventional digital FN11 code demodulator has problems unique to the FM communication system, such as the demodulation S/N rapidly decreasing below the threshold level, and advanced and It has a problem that requires complicated circuit adjustment.

この発明は上記の問題を解決するためになされたもので
、F M通信方式固有のスレッシュホールド特性の改善
を図りつつ、高度で複雑な回路調整が不要なデジタル型
FM信号復調装置を提供することを目的とする。
This invention was made to solve the above problems, and an object of the present invention is to provide a digital FM signal demodulation device that does not require sophisticated and complicated circuit adjustment while improving the threshold characteristics specific to the FM communication system. With the goal.

[発明の構成] (課題を解決するための手段) 上記目的を達成するためにこの発明に係るデジタル型F
 M信号復調装置は、FM変調波を入力して同相成分と
直交成分に分配するハイブリッド分配器と、サンプリン
グ周期を前記入力F Pv1変調波か無変調であるとき
の周期の整数倍に設定し、当該サンプリング周期で前記
同相成分と直交成分をそれぞれデジタル信号に変換する
アナログ/デジタル変換手段と、この手段によるアナロ
グ/デジタル変換後のデータよりサンプリング時点の入
力信号の位相角を演算する位相角演算手段と、この手段
で得られた前記同相成分と直交成分の各位相角の差分を
演算する差分演算手段と、この手段で得られた差分値か
予め定められた許容範囲を越えたか否かを判別する判別
手段と、前記許容範囲に入る差分値を求める補正手段と
、前記判別手段で許容範囲内と判別されたとき前記差分
演算手段の演算結果を導出し、許容範囲外と判別された
とき前記補正手段で求められた差分値を導圧する切換手
段とを具備して構成される。
[Structure of the invention] (Means for solving the problem) In order to achieve the above object, a digital type F according to this invention is provided.
The M signal demodulator includes a hybrid divider that inputs an FM modulated wave and divides it into an in-phase component and a quadrature component, and sets a sampling period to an integral multiple of the period when the input F Pv1 modulated wave is unmodulated; Analog/digital conversion means for converting the in-phase component and quadrature component into digital signals, respectively, at the sampling period, and phase angle calculation means for calculating the phase angle of the input signal at the time of sampling from the data after analog/digital conversion by this means. and a difference calculating means for calculating the difference between the phase angles of the in-phase component and the orthogonal component obtained by this means, and determining whether or not the difference value obtained by this means exceeds a predetermined tolerance range. a correcting means for determining a difference value that falls within the allowable range; a correcting means for deriving the calculation result of the difference calculating means when it is determined by the determining means that the difference is within the allowable range; and switching means for introducing the difference value determined by the correction means.

(作用) 上記構成によるデジタル型F M信号復調装置ては、同
相成分と直交成分の各位相角の差分を演算し、この差分
値か予め定められた許容1囲を越えたか否かを判別して
、許容範囲に入る差分値なる補正値を求め、許容範囲内
と判別されたとき差分演算結果をそのまま導出し、許容
範囲外と判別されたとき前記補正値を導出する。
(Operation) The digital FM signal demodulator having the above configuration calculates the difference between the phase angles of the in-phase component and the quadrature component, and determines whether or not this difference value exceeds a predetermined allowable range. Then, a correction value, which is a difference value that falls within the permissible range, is determined, and when it is determined that it is within the permissible range, the difference calculation result is directly derived, and when it is determined that it is outside the permissible range, the correction value is derived.

(実施例) 以下、第1図乃至第3図を参照してこの発明の一実施例
を説明する。但し、第1図において、第8図と同一部分
には同一符号を付して示し、二こでは異なる部分を中心
にのべる。  、第1図にこの発明の実施例を示すもの
で、この装置は第8図の減算回路35とD/A変換器3
6との間に補正回路が付加されている。この補正回路は
、減算回路35の出力レベルが基準し・ベルを越えるか
否かを判定するレベル判定回路37と、減算回路35の
8力値を1サンプル分遅延する遅延回路38と、減算回
路35の出力及び遅延回路38の出力をレベル判定回路
37の判定結果に応じて選択的にD/A変換器36に導
出する選択回路39とで構成される。
(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 3. However, in FIG. 1, the same parts as in FIG. 8 are designated by the same reference numerals, and the two parts mainly focus on different parts. , an embodiment of the present invention is shown in FIG.
A correction circuit is added between 6 and 6. This correction circuit includes a level determination circuit 37 that determines whether the output level of the subtraction circuit 35 exceeds the reference level, a delay circuit 38 that delays the output value of the subtraction circuit 35 by one sample, and a subtraction circuit 35 and a selection circuit 39 selectively outputting the output of the delay circuit 38 to the D/A converter 36 according to the determination result of the level determination circuit 37.

上記構成において、以下、第2図を参照しつつその動作
を説明する。
The operation of the above configuration will be described below with reference to FIG. 2.

まず、入力FM変調波SINに雑音が存在しない場合は
、 (1)〜 (4)式で示した通りである。しかし、
実際の受信信号には雑音が存在するため、逆正接回路3
3の出力は、 θs  (t)+θN  (t)      ・・(5
)と表される。尚、θ5は変調信号成分、θ、は位相雑
音成分である。したかって、減算回路35の出力は次の
ように与えられる。
First, when there is no noise in the input FM modulated wave SIN, the equations (1) to (4) are as shown. but,
Since there is noise in the actual received signal, the arctangent circuit 3
The output of 3 is θs (t) + θN (t) ... (5
). Note that θ5 is a modulation signal component, and θ is a phase noise component. Therefore, the output of the subtraction circuit 35 is given as follows.

(θs(T、)+θN(T−)1 −(θ5(T−1)+θN  (T−+ ) !=(ω
0+Δω)ΔT+ fθN(T、)−θN  (T−+
 ) 1 ・・・(6) 上式第2項はF M雑音成分である。
(θs(T,)+θN(T-)1-(θ5(T-1)+θN(T-+)!=(ω
0+Δω)ΔT+ fθN(T,)−θN (T−+
) 1 (6) The second term in the above equation is the FM noise component.

(6)式から明らかなように、C/Nか十分大きい場合
は1θN(T、)−θN  (T−+ )  l < 
<Δω・ΔTとなるが、C/Nが10dB以下となると
、第7図(b)に示したように、雑音によって変調成分
Δω・ΔTを越えるインパルス雑音か発生する。そこで
、レベル判定回路37により、減算回路35の出力S+
N (Sは復調信号、Nは雑音)が基準レベルを越える
か否かの判定を行う。
As is clear from equation (6), if C/N is sufficiently large, 1θN(T,)−θN(T−+) l <
<Δω·ΔT, but when the C/N becomes 10 dB or less, impulse noise exceeding the modulation component Δω·ΔT is generated due to noise, as shown in FIG. 7(b). Therefore, the level determination circuit 37 determines the output S+ of the subtraction circuit 35.
It is determined whether or not N (S is a demodulated signal, N is noise) exceeds a reference level.

すなわち、信号成分によるサンプル値毎の周波数差は、
周波数偏移量をΔF1最高変調周波数をfffiとする
と、ΔF・2πf、・ΔTを越すことはない。したかっ
て、減算回路37の出力か((ΔF・2πf0・ΔT)
+Ml  (Pvfは微小雑音に対するマージン)を越
えた場合、インパルス性雑音が生じていると判断するこ
とができる。レベル判定回路37は、選択回路39に対
し、上記基準レベルを越えない場合は減算回路35の出
力を選択し、基準レベルを越える場合は遅延回路38の
出力を選択するように、制御信号を送る。
In other words, the frequency difference for each sample value due to the signal component is
Assuming that the frequency shift amount is ΔF1 and the highest modulation frequency is fffi, it does not exceed ΔF·2πf,·ΔT. Is it the output of the subtraction circuit 37 ((ΔF・2πf0・ΔT)?
+Ml (Pvf is a margin for minute noise), it can be determined that impulsive noise is occurring. The level determination circuit 37 sends a control signal to the selection circuit 39 to select the output of the subtraction circuit 35 if the reference level is not exceeded, and to select the output of the delay circuit 38 if the reference level is exceeded. .

つまり、通常は減算回路35の出力値をそのまま導出し
、基準レベルを越えたときのみ、遅延回路38で遅延さ
れた1つ前の値を補正値としてD/A変換器36へ導出
する。
That is, normally, the output value of the subtraction circuit 35 is derived as is, and only when it exceeds the reference level, the previous value delayed by the delay circuit 38 is derived as a correction value to the D/A converter 36.

したがって、上記構成によるデジタル型FM信号復調装
置は、第2図(a)に示すインパルス性雑音が重畳され
たFM変調波を入力しても、何ら回路調整を行うことな
く、同図(b)に示すように復調信号のS/Nを改善す
ることができる。
Therefore, even if the digital FM signal demodulator having the above configuration receives the FM modulated wave on which impulsive noise is superimposed as shown in FIG. 2(a), the digital FM signal demodulator shown in FIG. The S/N of the demodulated signal can be improved as shown in FIG.

第3図はこの発明に係る他の実施例を示すものである。FIG. 3 shows another embodiment of the invention.

但し、第3図において、第1図と同一部分には同一符号
を付して、その説明を省略する。
However, in FIG. 3, the same parts as in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

この実施例では、補正回路として、前記レベル判定回路
37の他、第1乃至第3の遅延回路40゜41.42、
加算器43.1/2演算器44て構成される。すなわち
、この装置では、前記レベル判定回路37で減算回路3
5の出力レベル5(T9)が基準レベルを越えないと判
定したとき、第1の遅延回路40で1サンプル分遅延さ
れた値S (T、−1)を導出し、基準レベルを越えた
と判定したとき、第2、第3の遅延回路41.42で2
サンプル分遅延された値S (Tfi−2>と現在の値
S(T、)とを加算器43で加算し、1/2演算器44
で1/2とすることにより平均値(S (T、−2) 
十S (T、 ) ) / 2を求め、補正値として導
出する。この場合、第8図の実施例と比較して、データ
の置換によって生じる誤差をより少なくすることができ
る。
In this embodiment, in addition to the level determination circuit 37, first to third delay circuits 40°41.42,
It is composed of an adder 43 and a 1/2 arithmetic unit 44. That is, in this device, the level determination circuit 37
When it is determined that the output level 5 (T9) of 5 does not exceed the reference level, the first delay circuit 40 derives the value S (T, -1) delayed by one sample, and determines that the output level 5 (T9) has exceeded the reference level. 2 at the second and third delay circuits 41 and 42.
The value S(Tfi-2> delayed by the sample and the current value S(T,) are added by the adder 43, and the 1/2 arithmetic unit 44
The average value (S (T, -2)
10S (T, ))/2 is determined and derived as a correction value. In this case, compared to the embodiment shown in FIG. 8, errors caused by data replacement can be further reduced.

[発明の効果コ 以上のようにこの発明によれば、F M通信方式固有の
スレッシュホールド特性の改善を図りつつ、高度で複雑
な回路調整が不要なデジタル型F M信号復調装置を提
供することかできる。
[Effects of the Invention] As described above, according to the present invention, it is possible to provide a digital FM signal demodulation device that does not require advanced and complicated circuit adjustment while improving the threshold characteristics specific to the FM communication system. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明に係るデジタル型F M信号復調装置
の一実施例を示すブロック回路図、第2図は同実施例の
動作を説明するための波形図、第3図はこの発明に係る
他の実施例を示すブロック回路図、第4図は従来のF 
M信号復調装置の構成を示すブロック回路図、第5図は
第4図の装置の動作を説明するための特性図、第6図は
従来装置の他の構成を示すブロック回路図、第7図は第
6図の装置の動作を説明するたぬの波形図、第8図は従
来のデジタル型F M信号復調装置の構成を示すブロッ
ク回路図、第9図は第8図の装置の動作を説明するため
のベクトル図、第10図は第8図の装置の問題点となる
インパルス性雑音を説明するためのベクトル図である。 SIN・入力F M変調波、31・・・ハイブリッド分
配器、321.32゜・・・A/D変換器、33・・・
逆正接回路(位相角演算器)、34.・・1サンプル遅
延回路、342・・減算回路、34・・・微分回路、3
5 ・=減算回路、36− D / A変換器、so、
−復調信号、37・・・レベル判定回路、38 遅延回
路、3つ・・・選択回路、40,41.42  遅延回
路、43・・加算器、44・ ユ/2演算器。 出願人代理人 弁理士 鈴 江 武 彦拮4 図 ゛(b) 第6 図 第9図
FIG. 1 is a block circuit diagram showing an embodiment of a digital FM signal demodulator according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment, and FIG. A block circuit diagram showing another embodiment, FIG. 4 is a conventional F
FIG. 5 is a characteristic diagram for explaining the operation of the device in FIG. 4; FIG. 6 is a block circuit diagram showing another configuration of the conventional device; FIG. 6 is a waveform diagram illustrating the operation of the device shown in FIG. 6, FIG. 8 is a block circuit diagram showing the configuration of a conventional digital FM signal demodulation device, and FIG. 9 is a diagram illustrating the operation of the device shown in FIG. Vector Diagram for Explanation FIG. 10 is a vector diagram for explaining impulsive noise, which is a problem with the apparatus shown in FIG. SIN/input FM modulated wave, 31...Hybrid distributor, 321.32°...A/D converter, 33...
Arctangent circuit (phase angle calculator), 34. ...1 sample delay circuit, 342...Subtraction circuit, 34...Differentiation circuit, 3
5 ・= subtraction circuit, 36- D/A converter, so,
- Demodulated signal, 37... Level judgment circuit, 38 Delay circuit, 3... Selection circuit, 40, 41.42 Delay circuit, 43... Adder, 44. U/2 arithmetic unit. Applicant's agent Patent attorney Takehiko Suzue 4 Figure ゛(b) Figure 6 Figure 9

Claims (3)

【特許請求の範囲】[Claims] (1)FM変調波を入力して同相成分と直交成分に分配
するハイブリッド分配器と、サンプリング周期を前記入
力FM変調波が無変調であるときの周期の整数倍に設定
し、当該サンプリング周期で前記同相成分と直交成分を
それぞれデジタル信号に変換するアナログ/デジタル変
換手段と、この手段によるアナログ/デジタル変換後の
データよりサンプリング時点の入力信号の位相角を演算
する位相角演算手段と、この手段で得られた前記同相成
分と直交成分の各位相角の差分を演算する差分演算手段
と、この手段で得られた差分値が予め定められた許容範
囲を越えたか否かを判別する判別手段と、前記許容範囲
に入る差分値を求める補正手段と、前記判別手段で許容
範囲内と判別されたとき前記差分演算手段の演算結果を
導出し、許容範囲外と判別されたとき前記補正手段で求
められた差分値を導出する切換手段とを具備するデジタ
ル型FM信号復調装置。
(1) A hybrid distributor that inputs an FM modulated wave and divides it into an in-phase component and a quadrature component, and a sampling period that is set to an integral multiple of the period when the input FM modulated wave is unmodulated; Analog/digital conversion means for converting the in-phase component and quadrature component into digital signals, phase angle calculation means for calculating the phase angle of the input signal at the time of sampling from data after analog/digital conversion by this means, and this means a difference calculation means for calculating the difference between the phase angles of the in-phase component and the orthogonal component obtained by the step; and a determination means for determining whether the difference value obtained by this means exceeds a predetermined tolerance range. , a correction means for determining a difference value that falls within the tolerance range; a calculation result of the difference calculation means is derived when the discrimination means determines that the difference value is within the tolerance range; and a calculation result is derived by the difference calculation means when it is determined that the difference value is outside the tolerance range; 1. A digital FM signal demodulator, comprising: switching means for deriving a difference value.
(2)前記補正手段は、前記差分演算手段で得られた一
つ前の差分値を出力することを特徴とする請求項1記載
のデジタル型FM信号復調装置。
(2) The digital FM signal demodulation device according to claim 1, wherein the correction means outputs the previous difference value obtained by the difference calculation means.
(3)前記補正手段は、前記差分演算手段で得られた前
後の差分値の平均値を出力することを特徴とする請求項
1記載のデジタル型FM信号復調装置。
(3) The digital FM signal demodulation device according to claim 1, wherein the correction means outputs an average value of the difference values before and after the difference values obtained by the difference calculation means.
JP34027590A 1990-11-30 1990-11-30 Digital fm signal demodulator Pending JPH04207802A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34027590A JPH04207802A (en) 1990-11-30 1990-11-30 Digital fm signal demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34027590A JPH04207802A (en) 1990-11-30 1990-11-30 Digital fm signal demodulator

Publications (1)

Publication Number Publication Date
JPH04207802A true JPH04207802A (en) 1992-07-29

Family

ID=18335383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34027590A Pending JPH04207802A (en) 1990-11-30 1990-11-30 Digital fm signal demodulator

Country Status (1)

Country Link
JP (1) JPH04207802A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007049552A1 (en) * 2005-10-25 2007-05-03 Matsushita Electric Industrial Co., Ltd. Audio signal demodulation device
JP2009206536A (en) * 2008-01-30 2009-09-10 Daihen Corp High frequency detector
JP2014199737A (en) * 2013-03-29 2014-10-23 株式会社ダイヘン High frequency power supply device
JP2014199736A (en) * 2013-03-29 2014-10-23 株式会社ダイヘン High frequency power supply
WO2023248765A1 (en) * 2022-06-24 2023-12-28 株式会社ヨコオ Signal processing device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007049552A1 (en) * 2005-10-25 2007-05-03 Matsushita Electric Industrial Co., Ltd. Audio signal demodulation device
JP2009206536A (en) * 2008-01-30 2009-09-10 Daihen Corp High frequency detector
JP2014199737A (en) * 2013-03-29 2014-10-23 株式会社ダイヘン High frequency power supply device
JP2014199736A (en) * 2013-03-29 2014-10-23 株式会社ダイヘン High frequency power supply
WO2023248765A1 (en) * 2022-06-24 2023-12-28 株式会社ヨコオ Signal processing device

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