JPH0420123A - Pll frequency synthesizer oscillator - Google Patents
Pll frequency synthesizer oscillatorInfo
- Publication number
- JPH0420123A JPH0420123A JP2124996A JP12499690A JPH0420123A JP H0420123 A JPH0420123 A JP H0420123A JP 2124996 A JP2124996 A JP 2124996A JP 12499690 A JP12499690 A JP 12499690A JP H0420123 A JPH0420123 A JP H0420123A
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- pll
- oscillator
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Abstract
Description
【発明の詳細な説明】
〔概要〕
制御電圧Vcで発振周波数を制御する電圧制御発振器V
COと、其の出力foの一部を、より低い周波数に変換
するミキサと、該ミキサの出力の周波数を1/Nに分周
する可変分周器と、基準信号源からの信号frを1/H
に分周する分周器と、該分周器の出力fcを基準人力と
し前記可変分周器の出力を位相比較する位相比較器から
なり該位相比較器の出力を制御電圧Vcとして前記電圧
制御発振器を制御するPLLと、前記ミキサに周波数変
換のための局発信号fLを供給する局部発振器とを有す
るミキシングダウン方式のPLL周波数シンセサイザ発
振器に関し、
出力のキャリアのスペクトラム特性や安定性を損なうこ
となく、このキャリア近傍のスプリアス出力の与える悪
影響を軽減させたPLL周波数シンセサイザ発振器の提
供を目的とし、
前記PLLのミキサに供給する局部発振器の出力の局発
周波数fLが、該PLLの位相比較器の入力の基準周波
数fcの整数倍に選定されるように構成する。[Detailed Description of the Invention] [Summary] Voltage controlled oscillator V that controls oscillation frequency with control voltage Vc
CO, a mixer that converts a part of its output fo to a lower frequency, a variable frequency divider that divides the frequency of the output of the mixer to 1/N, and a signal fr from the reference signal source to 1/N. /H
and a phase comparator that uses the output fc of the frequency divider as a reference power and compares the phases of the output of the variable frequency divider. A mixing down type PLL frequency synthesizer oscillator having a PLL that controls an oscillator and a local oscillator that supplies a local oscillator signal fL for frequency conversion to the mixer, without impairing the spectral characteristics and stability of the output carrier. , the purpose is to provide a PLL frequency synthesizer oscillator that reduces the adverse effects of spurious output near the carrier, and the local oscillator frequency fL of the output of the local oscillator supplied to the mixer of the PLL is the input of the phase comparator of the PLL. The reference frequency fc is selected to be an integral multiple of the reference frequency fc.
〔産業上の利用分野]
本発明は、移動無線、衛星通信の送受信機、衛星放送の
チューナ、ラジオ等の装置に用いられるPLL周波数シ
ンセサイザ発振器に関する。[Industrial Application Field] The present invention relates to a PLL frequency synthesizer oscillator used in devices such as mobile radios, satellite communication transceivers, satellite broadcast tuners, and radios.
上記のような装置の高性能化に伴い、PLL周波数シン
セサイザ発振器も出力のスペクトラムの純度を高く、ス
プリアスのレベルを低く保ちつつ広い帯域で、細かい周
波数ステップ(出力可能な周波数の間隔)を実現すると
いう互いに相反する性能が要求されている。As the performance of the above devices increases, PLL frequency synthesizer oscillators also achieve fine frequency steps (intervals of frequencies that can be output) over a wide band while maintaining high output spectrum purity and low spurious levels. These contradictory performances are required.
従来のPLL周波数シンセサイザ発振器として。 As a conventional PLL frequency synthesizer oscillator.
第5図の(A)に示す如き、所謂ミキシングダウン方式
がある。この方式のPLL周波数シンセサイザ発振器は
、電圧制御発振器(以下VCOと呼ぶ)11の出力fo
の一部を、ミキサ12において局部発振器2の出力f、
と混合して、より低い周波数f。There is a so-called mixing down method as shown in FIG. 5(A). This type of PLL frequency synthesizer oscillator uses the output fo of a voltage controlled oscillator (hereinafter referred to as VCO) 11.
In the mixer 12, a part of the output f of the local oscillator 2,
mixed with the lower frequency f.
fLに周波数変換したのち、可変分周器13で周波数を
l/Nに分周して位相比較器15に入力する。−方、基
準信号源3からの周波数frの基準信号は。After converting the frequency to fL, the variable frequency divider 13 divides the frequency into l/N and inputs it to the phase comparator 15. - On the other hand, the reference signal of frequency fr from the reference signal source 3 is.
分周器14で1/Hに分周され基準周波数fcとして8
前記の位相比較器15に入力されて、可変分周器13か
らの信号と位相比較される。位相比較器15の出力は、
制御信号Vcとして前記のVCO11に供給され。The frequency is divided into 1/H by the frequency divider 14 and the reference frequency fc is 8.
The signal is input to the phase comparator 15 and compared in phase with the signal from the variable frequency divider 13. The output of the phase comparator 15 is
It is supplied to the VCO 11 as the control signal Vc.
其の発振周波数を制御する。この構成では、 VCOl
lの出力周波数foは、
fo = fc x N + f L −・−■とな
り1分周数Nを1づつ増減させる事によって。Control its oscillation frequency. In this configuration, VCOl
The output frequency fo of l is as follows: fo = fc x N + f L -・-■ By increasing/decreasing the frequency division number N by 1.
出力キャリアの周波数ステップfcが得られる。The frequency step fc of the output carrier is obtained.
この方式では1局部発振器2の出力の局発周波数fLを
、 VCO11の出力の出力周波数foに近い値に設計
することにより1分周数Nの値を小さくする事ができる
。In this method, by designing the local frequency fL of the output of one local oscillator 2 to a value close to the output frequency fo of the output of the VCO 11, it is possible to reduce the value of the frequency division number N.
PLL周波数シンセサイザ発振器の出力のキャリアのス
ペクトラムの純度を定量づける位相雑音は1位相比較器
15の内部雑音の20 Log N dB増になるから
、可変分周器13の分周数Nの値を成る可く小さくする
事により、該位相雑音を小さくシ。Since the phase noise that quantifies the purity of the carrier spectrum of the output of the PLL frequency synthesizer oscillator is 20 Log N dB higher than the internal noise of the 1-phase comparator 15, it becomes the value of the frequency division number N of the variable frequency divider 13. By making it as small as possible, the phase noise can be reduced.
出力のキャリアのスペクトラムの純度を上げることが出
来る。The purity of the output carrier spectrum can be increased.
然し、この様なミキシングダウン方式には、該方式に特
有のスプリアス出力が、所望の周波数(以後、キャリア
周波数と呼ぶ)foの近傍に発生することがある。これ
は9位相比較器15の入力の基準の周波数fcの整数倍
とキャリア周波数foが接近した時に顕著なレベルで現
れるもので、出力のスペクトラムfoの両側に1周波数
Δfsだけ離れて現れる。ここで Δfs = fo
−n x fc −■である。However, in such a mixing down method, a spurious output peculiar to the method may occur in the vicinity of a desired frequency (hereinafter referred to as a carrier frequency) fo. This appears at a remarkable level when an integer multiple of the input reference frequency fc of the nine-phase comparator 15 approaches the carrier frequency fo, and appears on both sides of the output spectrum fo, separated by one frequency Δfs. Here Δfs = fo
−n x fc −■.
スプリアス出力のレベルは、此のΔfsに大キく依存し
1例えば700 MHz帯の周波数シンセサイザの、所
謂D/U比は、第5図の(B)「スプリアスの位置とレ
ベルの例」のようになっている。The spurious output level largely depends on this Δfs.1 For example, the so-called D/U ratio of a 700 MHz band frequency synthesizer is as shown in Figure 5 (B) "Example of spurious position and level". It has become.
この様な所望のキャリアの近傍のスプリアス出力に対し
、所謂フィルタの挿入によって対処することは不可能で
ある。何となれば、この様なスプリアス出力に効果が有
るような狭帯域のフィルタをPLLループ内に挿入する
と、PLL出力のキャリアのスペクトラム特性や安定性
に悪い影響を与え、所期の性能が得られないからである
。 本発明の課題は、出力のキャリアのスペクトラム特
性や安定性を損なうことなく、キャリア近傍のスプリア
スの与える悪影響を軽減したPLL周波数シンセサイザ
発振器の従倶にある。It is impossible to deal with such spurious output near the desired carrier by inserting a so-called filter. The reason is that if a narrowband filter that is effective against such spurious output is inserted into the PLL loop, it will have a negative effect on the spectrum characteristics and stability of the carrier of the PLL output, making it impossible to obtain the desired performance. That's because there isn't. An object of the present invention is to provide a PLL frequency synthesizer oscillator that reduces the adverse effects of spurious signals near the carrier without impairing the spectral characteristics or stability of the output carrier.
〔課題を解決するための手段〕
この課題は、第1図の原理図の如く、電圧制御発振器V
CO11の出力foの一部をミキサ12で混合し周波数
を1/Nに分周するミキシングダウンの為の局部発振器
2の出力の局発周波数f、を1位相比較器I5の入力の
基準の周波数fcの整数倍に選ぶように構成した本発明
のPLL周波数シンセサイザ発振器によって達成される
。[Means for solving the problem] This problem is solved by using a voltage controlled oscillator V as shown in the principle diagram in Fig.
The local oscillator frequency f of the output of the local oscillator 2 for mixing down, which mixes a part of the output fo of the CO 11 with the mixer 12 and divides the frequency into 1/N, is the reference frequency of the input of the phase comparator I5. This is achieved by the PLL frequency synthesizer oscillator of the present invention configured to select an integer multiple of fc.
本発明のPLL周波数シンセサイザ発振器の動作を、第
2図の(a)、 (b)の各スペクトラムの周波数関係
図によって説明する。The operation of the PLL frequency synthesizer oscillator of the present invention will be explained with reference to the frequency relationship diagrams of the spectra shown in FIGS. 2(a) and 2(b).
第2図の(a)は4局部発振器2の出力の局発周波数f
Lを1位相比較器15の入力の基準周波数fcの整数倍
に選んだ場合のVCO11の出力周波数foと位相比較
器15の入力の基準周波数fcの高調波の周波数関係を
示す。 前記の式■に示したように。(a) in Figure 2 shows the local oscillation frequency f of the output of the four local oscillators 2.
The frequency relationship between the output frequency fo of the VCO 11 and the harmonics of the reference frequency fc of the input of the phase comparator 15 when L is selected to be an integral multiple of the reference frequency fc of the input of the phase comparator 15 is shown. As shown in equation (■) above.
VCO11の出力周波数foは、
fo = fc x N + f t −■(再出)
で表される。局発周波数fLを位相比較器の入力の基準
周波数fcの整数倍、すなわち
fL=fcxn −■
となる様に選ぶと、 VCO11の出力周波数foも。The output frequency fo of the VCO 11 is fo = fc x N + f t - ■ (reappearance)
It is expressed as If the local frequency fL is selected to be an integer multiple of the reference frequency fc of the input of the phase comparator, that is, fL=fcxn - ■, the output frequency fo of the VCO 11 will also be.
fo = fc x N + fc x n = fc
(N+n) =fc x N、■となって9位相比較器
15の入力の基準周波数fcの整数倍に一致する。fo = fc x N + fc x n = fc
(N+n) = fc x N, (■), which corresponds to an integral multiple of the reference frequency fc of the input of the nine phase comparator 15.
したがって、出力周波数fOと最も近い位相比較器の入
力の基準周波数の高調波は、 VCO11の出力周波数
foから周波数fcだけ離れる。すなわちΔfs =
fc −・・ ■である。これは、可変分周
器13の分周数Nを変えることによって、 VCO11
の出力周波数fOを切り替えた時にも成立する。Therefore, the harmonic of the reference frequency at the input of the phase comparator closest to the output frequency fO is separated from the output frequency fo of the VCO 11 by the frequency fc. That is, Δfs =
fc -...■. This can be done by changing the frequency division number N of the variable frequency divider 13.
This also holds true when the output frequency fO of is switched.
一方、第2図の(b)は9局部発振器2の出力の局発周
波数f、を8位相比較器15の入力の基準周波数fcの
整数倍でないように選んだ場合の、 VCO11の出力
周波数foと位相比較器15の入力の基準周波。On the other hand, (b) in FIG. 2 shows the output frequency fo of the VCO 11 when the local frequency f of the output of the nine local oscillators 2 is selected not to be an integral multiple of the reference frequency fc of the input of the eight phase comparator 15. and the reference frequency of the input of the phase comparator 15.
数fcの高調波の周波数関係を示す。この場合。The frequency relationship of several fc harmonics is shown. in this case.
f L= fc x n + f ’ 、 (f
’ < fc) ■という事であり、 VCO11の
出力周波数foは。f L= fc x n + f', (f
'< fc) ■The output frequency fo of VCO11 is.
fo = fc x N + fc x n + f’
= fc(N+n) + f ’= fc x N、
+ f’ 、 (f ’ < fc) ■である
。fo = fc x N + fc x n + f'
= fc(N+n) + f'= fc x N,
+ f', (f'< fc) ■.
第2図の(b)から判るように、Δfs = f’であ
り。As can be seen from FIG. 2(b), Δfs = f'.
スプリアス出力は、第2図の(a)に比べ、 VCO1
1の出力周波数foに近い周波数に現れる。前記第5図
の(A)の従来例で示したように、Δfs が大きく
なるにつれて1位相同期ループPLLの効果により、ス
プリアス出力のレベルは小さくなるから。Compared to (a) in Figure 2, the spurious output is VCO1
It appears at a frequency close to the output frequency fo of 1. As shown in the conventional example in FIG. 5A, as Δfs increases, the level of the spurious output decreases due to the effect of the one-phase locked loop PLL.
ミキシングダウンのための局発周波数fLを1位相比較
器15の入力の基準周波数fcの整数倍に選ぶことによ
り、該位相比較器の入力の基準周波数fcの高調波に起
因するスプリアスの出力レベルを最小に抑えることが出
来て課題は達成される。By selecting the local frequency fL for mixing down to be an integral multiple of the reference frequency fc at the input of the phase comparator 15, the output level of spurious signals due to harmonics of the reference frequency fc at the input of the phase comparator 15 can be reduced. The task can be achieved by minimizing it.
第3図は本発明の実施例のPLL周波数シンセサイザ発
振器の構成を示すブロック図であり、第4図は本発明の
別の実施例の構成を示すブロック図である。図中、第1
図で示したものと同一のものは、同一の記号で示してい
る。FIG. 3 is a block diagram showing the configuration of a PLL frequency synthesizer oscillator according to an embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, the first
Components that are the same as those shown in the figures are indicated by the same symbols.
第3図の実施例では、ミキシングダウンのための局部発
振器2として、 VCO21と、該νC021の出力f
Lを1/N*に分周する1/NZ分周器23と、基準信
号源3の出力周波数frを17M!に分周する1/M!
分周器24と、該1/’t’Vz分周器24の出力周波
数fczを基準入力として前記1/N*分周器23の出
力の位相比較を行う位相比較器25で構成される位相同
期ループを使用している。この場合1局部発振器2の出
力の局発周波数fLは。In the embodiment shown in FIG. 3, the local oscillator 2 for mixing down includes the VCO 21 and the output f of the νC021.
The 1/NZ frequency divider 23 that divides L into 1/N* and the output frequency fr of the reference signal source 3 are 17M! The frequency is divided into 1/M!
A phase comparator 25 comprising a frequency divider 24 and a phase comparator 25 that compares the phase of the output of the 1/N* frequency divider 23 using the output frequency fcz of the 1/'t'Vz frequency divider 24 as a reference input. Using a synchronous loop. In this case, the local oscillator frequency fL of the output of local oscillator 2 is as follows.
f L = fcz x Nz = fr/M2x N
、。f L = fcz x Nz = fr/M2x N
,.
であり9位相比較器15の入力の基準周波数fc、はf
c、・fr/M+であるので1局部発振器2の出力は2
f L−Ml/M2 fc+ x Nz。The reference frequency fc of the input of the phase comparator 15 is f
c, ・fr/M+, so the output of 1 local oscillator 2 is 2
f L-Ml/M2 fc+ x Nz.
となり9分同数の比h+/Mzを整数となるように選定
することによって実現可能できる。This can be realized by selecting the ratio h+/Mz of the same number of 9 minutes to be an integer.
第4図の本発明の別の実施例では、ミキシングダウンの
ための局部発振器2として、基準信号源3の出力周波数
frをし倍して、出力周波数fLを送出する逓倍器26
を使用している。この場合1局部発振器2の出力の局発
周波数f、は。In another embodiment of the present invention shown in FIG. 4, a multiplier 26 is used as a local oscillator 2 for mixing down, which multiplies the output frequency fr of the reference signal source 3 and sends out an output frequency fL.
are using. In this case, the local oscillator frequency f of the output of local oscillator 2 is:
f L = fc+ x L x L+となるので、こ
の局発周波数「、は1位相比較器15の入力の基準周波
数fc、の整数倍となり、前記の第3図の実施例と同じ
効果が得られる。Since f L = fc+ x L x L+, this local oscillation frequency "," is an integral multiple of the reference frequency fc of the input of the 1-phase comparator 15, and the same effect as the embodiment shown in FIG. 3 described above can be obtained. .
以上説明した様に1本発明によれば、出力のキャリアの
スペクトラム特性や安定性に悪影響を与えることなく1
位相比較の入力の基準周波数の高調波に起因するスプリ
アス出力のレベルを最小に抑えることが出来るため9種
々の送受信機等に用いられるPLL周波数シンセサイザ
発振器の性能を向上する効果が得られる。As explained above, according to the present invention, 1
Since the level of spurious output caused by harmonics of the reference frequency of the phase comparison input can be minimized, the performance of PLL frequency synthesizer oscillators used in various types of transmitters and receivers can be improved.
第1図は本発明のPLL周波数シンセサイザ発振器の基
本構成を示す原理図、
第2図は本発明のPLL周波数シンセサイザ発振器の動
作を説明するための各スペクトラムの周波数関係図、
第3図は本発明の実施例のPLL周波数シンセサイザ発
振器の構成を示すブロック図、第4図は本発明の別の実
施例のPLL周波数シンセサイザ発振器の構成を示すブ
ロック図、第5図は従来のPLL周波数シンセサイザ発
振器の構成と、スプリアスの位置とレベル例を示す。
図において、1はPLL、2は局部発振器、3は基準信
号源、11は電圧制御発振器VC0,12はミキサ、1
3は1/N可変分周器、14は1/M分周器15は位相
比較器、21は電圧制御発振器VC0,23は17N2
分周器、24は17M2分周器、25は位相比較器。
26は逓倍器である。
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口Fig. 1 is a principle diagram showing the basic configuration of the PLL frequency synthesizer oscillator of the present invention, Fig. 2 is a frequency relationship diagram of each spectrum to explain the operation of the PLL frequency synthesizer oscillator of the present invention, and Fig. 3 is a diagram of the frequency relationship of each spectrum. FIG. 4 is a block diagram showing the configuration of a PLL frequency synthesizer oscillator according to another embodiment of the present invention, and FIG. 5 is a block diagram showing the configuration of a conventional PLL frequency synthesizer oscillator. and examples of spurious positions and levels. In the figure, 1 is a PLL, 2 is a local oscillator, 3 is a reference signal source, 11 is a voltage controlled oscillator VC0, 12 is a mixer, 1
3 is a 1/N variable frequency divider, 14 is a 1/M frequency divider, 15 is a phase comparator, 21 is a voltage controlled oscillator VC0, 23 is 17N2
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Tsuki Tomiko mouth
Claims (1)
器(11)と、其の出力(fo)の一部をより低い周波
数に変換するミキサ(12)と、該ミキサの出力の周波
数を1/Nに分周する可変分周器(13)と、基準信号
源(3)からの信号(fr)を1/Mに分周する分周器
(14)と、該分周器の出力(fc)を基準入力とし前
記可変分周器の出力を位相比較する位相比較器(15)
からなり該位相比較器の出力を制御電圧(Vc)として
前記電圧制御発振器(11)を制御するPLL(1)と
、前記ミキサ(12)に周波数変換のための局発信号(
f_L)を供給する局部発振器(2)を有するPLL周
波数シンセサイザ発振器において、該局部発振器(2)
の出力の局発周波数(f_L)が該PLL(1)の位相
比較器(15)の入力の基準の周波数(fc)の整数倍
に選定されることを特徴としたPLL周波数シンセサイ
ザ発振器。A voltage controlled oscillator (11) that controls the oscillation frequency with a control voltage (Vc), a mixer (12) that converts a part of its output (fo) to a lower frequency, and a mixer that converts the frequency of the output of the mixer to 1/1. A variable frequency divider (13) that divides the frequency by N, a frequency divider (14) that divides the signal (fr) from the reference signal source (3) by 1/M, and an output (fc) of the frequency divider. ) as a reference input and a phase comparator (15) that compares the phase of the output of the variable frequency divider.
A PLL (1) that controls the voltage controlled oscillator (11) using the output of the phase comparator as a control voltage (Vc), and a local oscillator (1) for frequency conversion to the mixer (12).
f_L), wherein the PLL frequency synthesizer oscillator has a local oscillator (2) supplying the local oscillator (2)
A PLL frequency synthesizer oscillator characterized in that the local oscillator frequency (f_L) of the output of the PLL (1) is selected to be an integral multiple of the reference frequency (fc) of the input of the phase comparator (15) of the PLL (1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2124996A JPH0420123A (en) | 1990-05-15 | 1990-05-15 | Pll frequency synthesizer oscillator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2124996A JPH0420123A (en) | 1990-05-15 | 1990-05-15 | Pll frequency synthesizer oscillator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0420123A true JPH0420123A (en) | 1992-01-23 |
Family
ID=14899310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2124996A Pending JPH0420123A (en) | 1990-05-15 | 1990-05-15 | Pll frequency synthesizer oscillator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0420123A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007134833A (en) * | 2005-11-08 | 2007-05-31 | Nippon Hoso Kyokai <Nhk> | Pll frequency synthesizer |
JP2015035676A (en) * | 2013-08-08 | 2015-02-19 | 三菱電機株式会社 | Phase-locked loop |
-
1990
- 1990-05-15 JP JP2124996A patent/JPH0420123A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007134833A (en) * | 2005-11-08 | 2007-05-31 | Nippon Hoso Kyokai <Nhk> | Pll frequency synthesizer |
JP2015035676A (en) * | 2013-08-08 | 2015-02-19 | 三菱電機株式会社 | Phase-locked loop |
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