JPH04196420A - Structure of semiconductor device and method of manufacturing the same - Google Patents
Structure of semiconductor device and method of manufacturing the sameInfo
- Publication number
- JPH04196420A JPH04196420A JP32706790A JP32706790A JPH04196420A JP H04196420 A JPH04196420 A JP H04196420A JP 32706790 A JP32706790 A JP 32706790A JP 32706790 A JP32706790 A JP 32706790A JP H04196420 A JPH04196420 A JP H04196420A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- barrier metal
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000002844 melting Methods 0.000 abstract description 9
- 230000008018 melting Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018459 Al—Ge Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 244000292411 Excoecaria agallocha Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の構造及びその製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device and its manufacturing method.
高アスペクト比のコンタクトホールは、従来性われてい
るＡｆのスパッタではコンタクトホールの埋め込みが不
可能である。従って、キャリア濃度の高いポリシリコン
をコンタクトホールに埋め込むか、または、高融点金属
の選択埋め込みを行うことにより、コンタクトホールの
埋め込み及びコンタクト抵抗の低減化をはかってきた。Contact holes with a high aspect ratio cannot be filled with conventional Af sputtering. Therefore, attempts have been made to fill the contact hole and reduce the contact resistance by filling the contact hole with polysilicon having a high carrier concentration or by selectively filling the contact hole with a high melting point metal.
ポリシリコンをコンタクトホールに埋め込む”方法は、
不純物濃度に固溶限界があるため、アスペクト比の高い
コンタクトホールではコンタクト抵抗が高くなる。また
、高融点金属をコンタクトホールに選択的に埋め込む方
法は、コンタクト抵抗低減には有効であるが、高融点金
属をコンタクトホール内に選択的に成長させると、Ｓｔ
との界面でＳｉと高融点金属が反応し、コンタクトホー
ルの周辺からさらに外側ヘシリサイド化した金属が拡が
って、リークの原因となっていた。このリークを防ぐな
め、バリアメタル膜を形成後に高融点金属を成長させる
方法もあるが、バリアメタルとＳｉの接触抵抗が高いた
め、コンタクト抵抗が高くなる問題があった。The method of burying polysilicon into contact holes is
Since the impurity concentration has a solid solubility limit, contact holes with high aspect ratios have high contact resistance. In addition, the method of selectively burying a high melting point metal in a contact hole is effective for reducing contact resistance, but if a high melting point metal is selectively grown in a contact hole, St.
The Si reacts with the high-melting-point metal at the interface, and the hesilicided metal spreads further outward from the periphery of the contact hole, causing leakage. In order to prevent this leakage, there is a method of growing a high melting point metal after forming a barrier metal film, but there is a problem in that the contact resistance becomes high because the contact resistance between the barrier metal and Si is high.
本発明の目的は、このような問題点を解決した半導体装
置の構造及びその製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a structure of a semiconductor device and a method of manufacturing the same that solves these problems.
本発明の半導体装置の構造は、
Ｓｉ半導体装置のコンタクトホール上にＧｅ膜またはＧ
ｅの不純物を高濃度に含有する層を有し、前記Ｇｅ膜ま
なはＧｅの不純物を高濃度に含有する層上にバリアメタ
ルを有し、前記バリアメタル上に金属配線を有すること
を特徴とする。The structure of the semiconductor device of the present invention includes a Ge film or a G film on the contact hole of the Si semiconductor device.
a layer containing a high concentration of Ge impurities, a barrier metal on the Ge film or the layer containing a high concentration of Ge impurities, and a metal wiring on the barrier metal. do.
本発明の半導体装置の製造方法は、
コンタクトホール形成後、Ｇｅ膜を形成する工程と、前
記Ｇｅ膜上にバリアメタルの膜を形成する工程と、前記
バリアメタル上に金属膜を溶融状態で形成して配線を行
うことを特徴とする。The method for manufacturing a semiconductor device of the present invention includes, after forming a contact hole, forming a Ge film, forming a barrier metal film on the Ge film, and forming a metal film in a molten state on the barrier metal. The feature is that wiring is performed by
また本発明の半導体装置の製造方法は、コンタクトホー
ルを形成後、バリアメタルの膜を形成する工程と、前記
バリアメタルを通してＧｅをイオン注入する工程と、こ
れを高温短時間アニールを行う工程と、前記バリアメタ
ル上に金属膜を溶融状態で形成して配線を行うことを特
徴とする。Further, the method for manufacturing a semiconductor device of the present invention includes the following steps: after forming a contact hole, forming a barrier metal film, implanting Ge ions through the barrier metal, and annealing this for a short time at a high temperature. The method is characterized in that a metal film is formed in a molten state on the barrier metal to perform wiring.
Ｇｅのバンドギャップ０．６６ｅＶは、Ｓｉのバンドギ
ャップ１．１２ｅＶに比べ非常に小さいため、比抵抗も
Ｓｔに比べ約４桁低く、従来のようにコンタクトホール
に多結晶Ｓｉを埋め込んでいた場合に比べ、金属とＧｅ
１ｉｌまたはＧｅを高濃度に含有した５ｉＷＡとのコン
タクト抵抗は下がる。また、高融点金属の埋め込みのよ
うに、金属が直接に拡散層などのデバイス部分に接して
いないため、合金化を起こしてリークの原因となること
も防げる作用がある。Ｇｅ膜またはＧｅ含有層上のバリ
アメタルは、さらにその上の配線材料となる金属膜を形
成する際の、Ｇｅ膜またはＧｅ含有層と金属の反応を防
ぎ、リークを阻止する作用がある。上層の配線金属は、
低融点金属を基板温度を上げて堆積することにより、コ
ンタクトホールの埋め込みと平坦化を行う作用がある。Ge's band gap of 0.66 eV is much smaller than Si's band gap of 1.12 eV, so its resistivity is about four orders of magnitude lower than that of St. In comparison, metal and Ge
The contact resistance with 1il or 5iWA containing a high concentration of Ge is reduced. Furthermore, since the metal is not in direct contact with the device parts such as the diffusion layer, as in the case of embedding a high-melting point metal, it is possible to prevent alloying from occurring and causing leakage. The barrier metal on the Ge film or the Ge-containing layer has the effect of preventing a reaction between the Ge film or the Ge-containing layer and the metal and preventing leakage when forming a metal film that is a wiring material thereon. The upper layer wiring metal is
Depositing a low melting point metal while raising the substrate temperature has the effect of filling and flattening the contact hole.
本発明の実施例について図を参照して説明する。 Embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の半導体装置の一実施例の断面図であ
る。FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention.
ｐ形Ｓｉ基板１上に形成されたｎチャネルのＭＯＳＦＥ
Ｔのソース２．ドレイン３．ゲート４のコンタクトホー
ルに、膜厚５００人のＧｅＷＡまたはＧｅを高濃度に含
んだＳｉ層５を設けている。このＧｅｐＩＡまたはＧｅ
含有層上に、厚さ２００人のバリアメタルであるＴｉＮ
膜６がある。ＴｉＮ膜上に、ＡＪ−Ｓｉより低融点であ
るＡｊＩ−５％Ｇｅ膜７を埋め込み配線として設けであ
る。N-channel MOSFE formed on p-type Si substrate 1
T's sauce 2. Drain 3. In the contact hole of the gate 4, a GeWA layer 5 having a film thickness of 500 nm or a Si layer 5 containing a high concentration of Ge is provided. This GepIA or Ge
On the containing layer, a barrier metal of TiN with a thickness of 200 mm is applied.
There is a membrane 6. An AjI-5%Ge film 7 having a lower melting point than AJ-Si is provided as a buried wiring on the TiN film.
第２図は、本発明の半導体装置のコンタクト部の一製造
方法を示す断面図である。FIG. 2 is a cross-sectional view showing one method of manufacturing the contact portion of the semiconductor device of the present invention.
ドライエツチングであけた開口部０．８Ｘ０．８μｍ２
．高さ０．７μｍのコンタクトホールにリンを固溶限界
まで拡散させたＧｅ膜を、超高真空のガスソース分子線
エピタキシー（ガスソースＭＢＥ）法によりコンタクト
ホール底部に選択的に５００人成長させる（第２図（ａ
））、ガスは水素希釈ゲルマンを用い、ＥＣＲによるク
ラッキングを行った。基板温度は６００℃、ガス圧は５
Ｘ １Ｏ−５Ｔｏｒｒである。Opening 0.8x0.8μm2 by dry etching
．． A Ge film with phosphorus diffused to the solid solution limit in a contact hole with a height of 0.7 μm is selectively grown at the bottom of the contact hole using ultra-high vacuum gas source molecular beam epitaxy (gas source MBE) ( Figure 2 (a
)), hydrogen-diluted germane gas was used, and cracking was performed by ECR. Substrate temperature is 600℃, gas pressure is 5
X 1O-5Torr.
次に、スパッタによりＴｉＮ膜を１０００人堆積したく
第２図（ｂ））、このとき、ホールの側壁及び底部には
ＴｉＮが入り込みにくいため、その膜厚は約２００人で
ある。その後、Ｇｅを５％含むＡＪ；１−Ｇｅ合金７を
１μｍスパッタしたく第２図（ｃ ） ） ’＋１ Ａ
ｊ’−Ｇｅ合金は共晶温度がＡｆ−Ｓｔに比べ低いため
、基板温度３００℃でリフロースパッタが行えた。その
後、配線パターンを形成した。Next, a TiN film of 1,000 layers is deposited by sputtering (FIG. 2(b)); at this time, the film thickness is about 200 layers because TiN is difficult to penetrate into the side walls and bottoms of the holes. After that, AJ; 1-Ge alloy 7 containing 5% Ge was sputtered to a thickness of 1 μm.
Since the j'-Ge alloy has a lower eutectic temperature than Af-St, reflow sputtering could be performed at a substrate temperature of 300°C. After that, a wiring pattern was formed.
゛第３図は、本発明の半導体装置のコンタクト部の別の
一製造方法を示す断面図である。3 is a sectional view showing another method of manufacturing the contact portion of the semiconductor device of the present invention.
ドライエツチングであけた開口部０．８Ｘ Ｏ，８μｍ
２．高さ０．７μｍのコンタクトホールにＴｉＮ６を１
０００人スパッタする（第３図（ａ））、このときホー
ルの側壁及び底部にはＴｉＮは約２００人ついている。Dry etched opening 0.8X O, 8μm
2. 1 layer of TiN6 in a contact hole with a height of 0.7 μm
At this time, about 200 TiN particles are attached to the side walls and bottom of the hole (FIG. 3(a)).
次にＧｅをＴｉＮ膜６を通してイオン注入する（第３図
（ｂ））、このとき加速エネルギーは６０ｋｅＶ、ドー
ス量は２．５Ｘ １０１６／ ｃｍ２である。イオン注
入によるＳｉ中の欠陥を減少し、ＳｉサイトにＧｅ原子
を置換させるために６００℃で３時間窒素処理をする。Next, Ge ions are implanted through the TiN film 6 (FIG. 3(b)), at which time the acceleration energy is 60 keV and the dose is 2.5×10 16 /cm 2 . Nitrogen treatment is performed at 600° C. for 3 hours to reduce defects in Si due to ion implantation and to substitute Ge atoms at Si sites.
その後さらにＴｉＮを緻密にし、メタルのバリア効果を
向上させるために、１０００℃で１０秒ランプアニール
を行った。その後のＡｌ−５％Ｇｅ７による配線工程は
、前記製造方法と同様である。Thereafter, lamp annealing was performed at 1000° C. for 10 seconds in order to further make the TiN dense and improve the barrier effect of the metal. The subsequent wiring process using Al-5%Ge7 is the same as the manufacturing method described above.
以上の構造及び製造方法によれば、高融点材料の埋め込
みで問題になっている、Ｐチャネルのコンタクト抵抗も
低減することができる。また本発明はＭＯＳＦＥＴに限
らずバイポーラトランジスタ等にも適用可能である。According to the above structure and manufacturing method, it is also possible to reduce the contact resistance of the P channel, which is a problem when embedding a high melting point material. Furthermore, the present invention is applicable not only to MOSFETs but also to bipolar transistors and the like.
本発明を用いれば、高アスペクト比のコンタクトホール
を埋め込むことができる上、材料自身の抵抗も低く、ま
た、金属とのオーミックコンタクトもとりやすいので、
コンタクト抵抗の低減化をはかることができる。また、
金属とソース・トレインが直接接していないため、Ｓｔ
基板への金属の食い込みによるリークや、金属スパイク
による接合の破壊も起こらない。よって、将来の微細デ
バイスにおいて大きな問題となるとされている、コンタ
クト抵抗増大によるデバイスの劣化を改善することがで
きる効果がある。Using the present invention, it is possible to fill contact holes with high aspect ratios, the resistance of the material itself is low, and it is easy to make ohmic contact with metal.
Contact resistance can be reduced. Also,
Since the metal and source train are not in direct contact, St
There is no leakage due to metal digging into the board, and no damage to the bond due to metal spikes. Therefore, it is possible to improve device deterioration due to increased contact resistance, which is considered to be a major problem in future fine devices.
第１図は本発明の半導体装置の一実施例の構造を示す断
面図、
第２図はその一製造方法を示す図、
第３図は別の一製造方法を示す図である。
１・・・ｐ形Ｓｉ基板
２・・・ソース
３・・・ドレイン
４・・・ゲート
５・・・Ｇｅ１ｌまたは高濃度Ｇｅ含有Ｓｉ層６・・・
ＴｉＮ膜
７・・・ＡＪ−５％Ｇｅ配線
代理人 弁理士 岩 佐 義 幸
第 １ 図
（ａ）
（ｂ）
（Ｃ）
第２図
（Ｃ）
第３図FIG. 1 is a cross-sectional view showing the structure of an embodiment of the semiconductor device of the present invention, FIG. 2 is a view showing one manufacturing method thereof, and FIG. 3 is a view showing another manufacturing method. 1... P-type Si substrate 2... Source 3... Drain 4... Gate 5... Ge11 or high concentration Ge-containing Si layer 6...
TiN film 7...AJ-5%Ge wiring agent Patent attorney Yoshiyuki Iwasa Figure 1 (a) (b) (C) Figure 2 (C) Figure 3
Claims (3)
たはＧｅの不純物を高濃度に含有する層を有し、前記Ｇ
ｅ膜またはＧｅの不純物を高濃度に含有する層上にバリ
アメタルを有し、前記バリアメタル上に金属配線を有す
ることを特徴とする半導体装置。(1) A Ge film or a layer containing a high concentration of Ge impurities is provided on the contact hole of the Si semiconductor device, and the
A semiconductor device comprising a barrier metal on an e-film or a layer containing a high concentration of Ge impurities, and a metal wiring on the barrier metal.
と、前記Ｇｅ膜上にバリアメタルの膜を形成する工程と
、前記バリアメタル上に金属膜を溶融状態で形成して配
線を行うことを特徴とする半導体装置の製造方法。(2) After forming the contact hole, a step of forming a Ge film, a step of forming a barrier metal film on the Ge film, and a step of forming a metal film in a molten state on the barrier metal to perform wiring. A method for manufacturing a featured semiconductor device.
形成する工程と、前記バリアメタルを通してＧｅをイオ
ン注入する工程と、これを高温短時間アニールを行う工
程と、前記バリアメタル上に金属膜を溶融状態で形成し
て配線を行うことを特徴とする半導体装置の製造方法。(3) After forming the contact hole, a step of forming a barrier metal film, a step of implanting Ge ions through the barrier metal, a step of annealing this for a short time at high temperature, and a step of forming a metal film on the barrier metal. A method of manufacturing a semiconductor device characterized by forming the semiconductor device in a molten state and performing wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32706790A JPH04196420A (en) | 1990-11-28 | 1990-11-28 | Structure of semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32706790A JPH04196420A (en) | 1990-11-28 | 1990-11-28 | Structure of semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04196420A true JPH04196420A (en) | 1992-07-16 |
Family
ID=18194927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32706790A Pending JPH04196420A (en) | 1990-11-28 | 1990-11-28 | Structure of semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04196420A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691571A (en) * | 1994-12-28 | 1997-11-25 | Nec Corporation | Semiconductor device having fine contact hole with high aspect ratio |
| DE4406861B4 (en) * | 1993-03-02 | 2005-01-20 | Samsung Electronics Co., Ltd., Suwon | Ohmic contact structure for a highly integrated semiconductor device and manufacturing method |
| US6891244B2 (en) * | 2002-07-12 | 2005-05-10 | Winbond Electronics Corporation | Plug structure having low contact resistance and method of manufacturing |
| US7564062B2 (en) | 2002-10-29 | 2009-07-21 | Toyoda Gosei, Co., Ltd. | Electrode for p-type SiC |
| US7750476B2 (en) | 1995-12-20 | 2010-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a reliable contact |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192562A (en) * | 1990-11-27 | 1992-07-10 | Fujitsu Ltd | Semiconductor device and its manufacture |
-
1990
- 1990-11-28 JP JP32706790A patent/JPH04196420A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192562A (en) * | 1990-11-27 | 1992-07-10 | Fujitsu Ltd | Semiconductor device and its manufacture |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4406861B4 (en) * | 1993-03-02 | 2005-01-20 | Samsung Electronics Co., Ltd., Suwon | Ohmic contact structure for a highly integrated semiconductor device and manufacturing method |
| US5691571A (en) * | 1994-12-28 | 1997-11-25 | Nec Corporation | Semiconductor device having fine contact hole with high aspect ratio |
| CN1088912C (en) * | 1994-12-28 | 2002-08-07 | 日本电气株式会社 | Semiconductor device and method of manufacturing the same |
| US7750476B2 (en) | 1995-12-20 | 2010-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a reliable contact |
| US6891244B2 (en) * | 2002-07-12 | 2005-05-10 | Winbond Electronics Corporation | Plug structure having low contact resistance and method of manufacturing |
| US7564062B2 (en) | 2002-10-29 | 2009-07-21 | Toyoda Gosei, Co., Ltd. | Electrode for p-type SiC |
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