JPH04196418A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04196418A JPH04196418A JP32749190A JP32749190A JPH04196418A JP H04196418 A JPH04196418 A JP H04196418A JP 32749190 A JP32749190 A JP 32749190A JP 32749190 A JP32749190 A JP 32749190A JP H04196418 A JPH04196418 A JP H04196418A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- metal
- wiring
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 5
- 150000002902 organometallic compounds Chemical class 0.000 claims abstract description 5
- 229910001507 metal halide Inorganic materials 0.000 claims abstract description 4
- 150000005309 metal halides Chemical class 0.000 claims abstract description 3
- 239000007789 gas Substances 0.000 claims description 18
- 150000004820 halides Chemical class 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 150000004678 hydrides Chemical class 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 53
- 238000001179 sorption measurement Methods 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 15
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 238000006722 reduction reaction Methods 0.000 abstract description 4
- 239000003638 chemical reducing agent Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- -1 metal halide compound Chemical class 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 230000002159 abnormal effect Effects 0.000 description 9
- 230000003628 erosive effect Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
化学気相成長（ＣＶＤ）法を用いた配線の形成方法に関
し。[Detailed Description of the Invention] [Summary] This invention relates to a method for forming wiring using chemical vapor deposition (CVD).
ＣＶＤ法により剥離や浸食や異常成長等のない安定した
コンタクトホールの埋込と配線膜の形成を目的とし。The purpose is to stably fill contact holes and form wiring films using the CVD method without peeling, erosion, or abnormal growth.
１）被成長基板上に金属のノ１０ゲン化物あるいは金属
の有機化合物を吸着させる工程と、該吸着物を熱、光ま
たはＲＦ電力を加えて還元雰囲気中で反応させて該基板
上に金属膜を形成する工程と、波金属膜上に導電膜を成
膜する工程とを有するよ）に構成する。1) A step of adsorbing a metal genide or a metal organic compound onto a substrate to be grown, and reacting the adsorbed substance in a reducing atmosphere by applying heat, light or RF power to form a metal film on the substrate. and a step of forming a conductive film on the wave metal film.
２）前記金属がＷ、 Ｔｉ、 Ｍｏ、 Ｔａ、 Ｈｆ、
Ｚｒ、 Ｃｕ、 Ａｌ。2) The metal is W, Ti, Mo, Ta, Hf,
Zr, Cu, Al.
Ａｕであるように構成する。It is configured to be made of Au.
３）還元ガスを被成長基板上に吸着させた後、前記の３
工程を行うように構成する。3) After adsorbing the reducing gas onto the growth substrate, proceed as described in 3.
Configure to perform the process.
４）前記還元ガスは水素、 ｍ、 ｒｖ、 ｖ族元素を
含む水素化物またはハロゲン化物であるように構成する
。4) The reducing gas is configured to be hydrogen, a hydride or a halide containing an element of group M, RV, or V.
本発明は半導体装置の製造方法に係り、特にＣＶＤ法を
用いた配線の形成方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming wiring using a CVD method.
超し］デバイスでは微細配線、上下配線間の高アスペク
トコンタクトの接続が必要となる。Devices require fine wiring and high aspect contact connections between upper and lower wiring.
さらにこれらの配線膜を複雑な表面形状の半導体チップ
上に被覆しなければならない。Furthermore, these wiring films must be coated on semiconductor chips with complex surface shapes.
また、配線を直接シリコン（Ｓｉ）に接触させる場合は
配線物質とＳｉとの反応を防止することが必要である。Furthermore, when the wiring is brought into direct contact with silicon (Si), it is necessary to prevent a reaction between the wiring material and the Si.
計このために、 ＣＶＤ法
を利用した成膜や選択成長等の埋込技術を用いる必要が
ある。For this reason, it is necessary to use a embedding technique such as film formation using the CVD method or selective growth.
本発明は以上の要求に対応したＣＶＤ法として利用でき
る。The present invention can be used as a CVD method that meets the above requirements.
〔従来の技術〕
従来、配線の形成はスパッタ法かあるいはＣＶＤ法によ
る選択成長が用いられていた。[Prior Art] Conventionally, wiring has been formed by selective growth by sputtering or CVD.
特に、コンタクトホールの埋込にはタングステン（Ｗ）
等の選択ＣＶＤ法が検討されている。In particular, tungsten (W) is used to fill contact holes.
Selective CVD methods such as the following are being considered.
ところが、 ＣＶＤ法による成膜では剥離や浸食や異常
成長等が発生し、リーク電流やコンタクト抵抗の増加を
生じていた。However, when forming a film using the CVD method, peeling, erosion, abnormal growth, etc. occur, resulting in an increase in leakage current and contact resistance.
Ｗの異常成長は基板の結晶配列に配向したために起こる
β−Ｗの成長がある。通常成膜されたＷはα−前である
が、β−Ｗは密度が小さく粗な膜質のため見掛けの成長
速度がα−前の数倍となり、このため、コンタクトホー
ルから溢れ出してしまうことになる。Abnormal growth of W includes growth of β-W caused by orientation to the crystalline alignment of the substrate. Normally, the deposited W is before α-, but β-W has a low density and rough film quality, so the apparent growth rate is several times that of before α-, which causes it to overflow from the contact hole. become.
したがって、従来のＣＶＤ法による場合、デバイス特性
を損なうことなく微細配線を形成することは困難であっ
た。Therefore, when using the conventional CVD method, it is difficult to form fine wiring without impairing device characteristics.
本発明はＣＶＤ法により剥離や浸食や異常成長等のない
安定したコンタクトホールの埋込と配線膜の形成を目的
とする。The object of the present invention is to stably fill contact holes and form interconnection films without peeling, erosion, abnormal growth, etc. by the CVD method.
上記課題の解決は。 What is the solution to the above problem?
１）被成長基板上に金属のハロゲン化物あるいは金属の
有機化合物を吸着させる工程と、該吸着物を熱、光また
はＲＦ電力を加えて還元雰囲気中で反応させて該基板上
に金属膜を形成する工程と、該金属膜上に導電膜を成膜
する工程とを有する半導体装置の製造方法、あるいは
２）前記金属がＷ、 Ｔｉ、 Ｍｏ、 Ｔａ、 Ｉｆ、
Ｚｒ、 Ｃｕ、 ＡＩ。1) A step of adsorbing a metal halide or a metal organic compound onto a growth substrate, and forming a metal film on the substrate by reacting the adsorbed substance in a reducing atmosphere by applying heat, light, or RF power. and forming a conductive film on the metal film, or 2) the metal is W, Ti, Mo, Ta, If,
Zr, Cu, AI.
Ａｕであることを特徴とする前記ｌ）記載の半導体装置
の製造方法、あるいは
３）還元ガスを被成長基板上に吸着させた後、前記の３
工程を行うことを特徴とする前記１）記載の半導体装置
の製造方法、あるいは
４）前記還元ガスは水素、 Ｉ、 ＩＶ、 Ｖ族元素を
含む水素化物またはハロゲン化物であることを特徴とす
る前記３）請求項３記載の半導体装置の製造方法により
達成される。The method for manufacturing a semiconductor device according to l) above, characterized in that Au is used, or 3) after adsorbing the reducing gas onto the growth substrate, the method described in 3 above.
1), or 4) the method for manufacturing a semiconductor device, characterized in that the reducing gas is hydrogen, a hydride or a halide containing a group I, IV, or V element; 3) Achieved by the method for manufacturing a semiconductor device according to claim 3.
本発明は前処理を行った基板上にソースガスの数原子ま
たは数分子程度の吸着層を形成し、化学的な還元作用を
利用して薄く安定な金属薄膜を形成してこれを成長表面
とし、この上に成膜を行うことにより、成長皮膜の剥離
や異常成長を防止するようにしたものである。In the present invention, an adsorption layer of a few atoms or molecules of a source gas is formed on a pretreated substrate, and a thin and stable metal thin film is formed using chemical reduction, and this is used as a growth surface. By forming a film thereon, peeling and abnormal growth of the grown film are prevented.
この場合９例えば、基板をＳｉや金属とした場合。In this case 9, for example, when the substrate is made of Si or metal.
表面に酸化膜があると吸着量が少なく、また吸着状態が
弱いことから、ソースガスの圧力、基板温度を適宜に設
定することによりＳｉや金属面にのみ吸着させることが
できる。If there is an oxide film on the surface, the adsorption amount is small and the adsorption state is weak, so by appropriately setting the pressure of the source gas and the substrate temperature, it is possible to make it adsorb only on Si or metal surfaces.
第１図（Ａ）〜（Ｃ）は本発明の一実施例を説明する断
面図である。FIGS. 1A to 1C are cross-sectional views illustrating an embodiment of the present invention.
図において、ｌはＳｉ基板、２は絶縁膜で二酸化シリコ
ン（ＳｉＣｈ）膜、３はコンタクトホール１４は吸着層
、 ４Ａは金属膜、５は埋込層、６は第２の吸着膜、
６Ａは第２の金属膜、７は配線膜である。In the figure, l is a Si substrate, 2 is an insulating film and is a silicon dioxide (SiCh) film, 3 is a contact hole 14 is an adsorption layer, 4A is a metal film, 5 is a buried layer, 6 is a second adsorption film,
6A is a second metal film, and 7 is a wiring film.
つぎに実施例を工程順に説明する。Next, examples will be explained in order of steps.
〔第１図（Ａ）参照〕
（１）前処理
例えば、バターニング工程での残留物を除去した後に、
つぎの（Ａ）、（Ｂ） ２段階のプラズマ処理を行う。[See Figure 1 (A)] (1) Pretreatment For example, after removing the residue from the buttering process,
The following two steps (A) and (B) are performed.
（Ａ）反応ガス： ＮＦＩ／Ｈ２，５／１００ ＳＣ
ＣＭ反応圧カニ ２０ ｍＴｏｒｒ
ＲＦ主電力：３０〜６０ Ｗ／ｃｍ２
処理時間：２０秒
ここで、 ＮＦ、の代わりにＦ２を用いることもできる
。(A) Reaction gas: NFI/H2, 5/100 SC
CM reaction pressure 20 mTorr RF main power: 30-60 W/cm2 Processing time: 20 seconds Here, F2 can also be used instead of NF.
（Ｂ）反応ガス：Ｆ７
反応圧カニ ５０ ｍＴｏｒｒ
ＲＦ主電力：１００〜２００ Ｗ／ｃｍ’処理時間：３
０秒
（２）吸着層４の形成
反応ガス： Ａｌ（ｉＣ，）１６）、、 ５３ＣＣ
Ｍガス圧カニ １０−７〜１０−’ Ｔｏｒｒ基板温
度ニー４０〜４０°Ｃ
処理時間： ０．１−１０秒
〔第１図（Ｂ）参照〕
（３）加熱（金属膜４Ａの形成）
基板温度＝２４０℃
この加熱は吸着層に還元反応を起こさせるために還元雰
囲気中で行う。(B) Reaction gas: F7 Reaction pressure 50 mTorr RF main power: 100-200 W/cm' Processing time: 3
0 seconds (2) Formation of adsorption layer 4 Reactive gas: Al(iC,)16),, 53CC
M gas pressure crab 10-7~10-' Torr Substrate temperature knee 40~40°C Processing time: 0.1-10 seconds [See Figure 1 (B)] (3) Heating (formation of metal film 4A) Substrate Temperature = 240° C. This heating is performed in a reducing atmosphere in order to cause a reduction reaction in the adsorption layer.
また９反応促進のための加熱の代わりに光の照射、 Ｒ
Ｆ主電力印加等を行ってもよい。9Instead of heating to promote the reaction, light irradiation, R
F main power may also be applied.
（４）コンタクトホールの埋込（埋込層５の形成）選択
成長の条件
反応ガス： ＷＦｓ／ＳｉＨ４，５／３ＳＣＣＭガス
圧カニ ３０ ｍＴｏｒｒ
基板温度＝２４０℃
（５）吸着層６の形成
反応ガス： ＴｉＣ！＜、 ５３ＣＣＭガス圧カニ
１０−” Ｔｏｒｒ
基板温度：１０〜１００℃
〔第１図（Ｃ）参照〕
（６）加熱（金属膜６Ａの形成）
基板温度＝２００°に
の加熱も吸着層に還元反応を起こさせるために還元雰囲
気中で行う。(4) Contact hole filling (formation of buried layer 5) Selective growth conditions Reactive gas: WFs/SiH4,5/3SCCM gas pressure crab 30 mTorr Substrate temperature = 240°C (5) Formation of adsorption layer 6 Reactive gas : TiC! <, 53CCM gas pressure crab 10-” Torr Substrate temperature: 10 to 100°C [See Figure 1 (C)] (6) Heating (Formation of metal film 6A) Heating to substrate temperature = 200° also reduces the adsorption layer. It is carried out in a reducing atmosphere to allow the reaction to occur.
また１反応促進のための加熱の代わりに光の照射、 Ｒ
Ｆ主電力印加等を行ってもよい。Also, instead of heating to promote 1 reaction, light irradiation, R
F main power may also be applied.
この金属膜６Ａ膜はつぎのＴｉＮ成膜のための成長核と
なる。均一なＴｉ膜ができると、 ＴｉＮの成膜特性（
膜厚分布１表面状態）が改善される。This metal film 6A becomes a growth nucleus for the next TiN film formation. Once a uniform Ti film is formed, the film formation characteristics of TiN (
The film thickness distribution (1) surface condition) is improved.
（７） ＴｉＮの成長（図では省略）
反応ガス： ＴｉＣｌ４．１０ ＳＣ０ＭＮ２Ｈ４，
１００ＳＣＣＭ
ガス圧カニ ０．１３〜１０ Ｔｏｒｒ基板温度：
５００〜６００℃
ここで９本発明とは直接関係がないので図示を省略した
が、このＴｉＮの成長は密着性向上と、この膜の上下の
層の反応防止用のバリア層として成長するものである。(7) Growth of TiN (omitted in the figure) Reaction gas: TiCl4.10 SC0MN2H4,
100SCCM gas pressure crab 0.13~10 Torr substrate temperature:
500 to 600°CHere 9 Although not shown in the figure as it has no direct relation to the present invention, this TiN growth is intended to improve adhesion and to form a barrier layer for preventing reactions between the layers above and below this film. be.
（８） Ａｌの成膜（配線膜７の形成）ＣＶＤ条件
反応ガス： Ａｌ（ｉＣＪｓ）ｓ、 ２０３ＣＣＭガ
ス圧カニ ０．５〜１００ Ｔｏｒｒ基板温度：２
４０℃
または、スパッタ条件
スパッタガス：Ａｒ
ガス圧カニ １０−’ Ｔｏｒｒ
ＲＦ電力 ：８００Ｗ
以上により配線膜の形成が終わり、この膜をパターニン
グして配線を形成する。(8) Al film formation (formation of wiring film 7) CVD conditions Reactive gas: Al(iCJs)s, 203CCM gas pressure crab 0.5-100 Torr Substrate temperature: 2
40[deg.] C. or sputtering conditions Sputtering gas: Ar Gas pressure 10-' Torr RF power: 800 W The formation of the wiring film is completed, and this film is patterned to form wiring.
上記の工程は（１）の前処理から各工程ごとの反応室間
をロードロック室で連結して（８）のＡＩの成膜まで基
板は大気中に取り出されることなく処理されるようにす
る。In the above steps, the reaction chambers for each step are connected by a load lock chamber from the pretreatment in (1) to the AI film formation in (8), so that the substrate is processed without being taken out into the atmosphere. .
上記の実施例の（２）、（８）の吸着層の形成において
１反応ガスの代表例としてＡＩ（ｉｃ４）１１）、 Ｔ
ｉＣｌ４を用いたが、 Ｗ、 Ｔｉ、 Ｍｏ、 Ｔａ
、 Ｈｆ、 Ｚｒ、 Ｃｕ、 ＡＩ、 Ａｕのハロゲン
化物かあるいは有機化合物を用いても同等の効果が得ら
れる。In the formation of the adsorption layer in (2) and (8) of the above examples, representative examples of one reaction gas are AI(ic4)11), T
iCl4 was used, but W, Ti, Mo, Ta
, Hf, Zr, Cu, AI, Au halides or organic compounds may be used to obtain the same effect.
また、適当な温度を設定することにより、これらの金属
のシリサイド層を形成し、実施例の金属層の代わりにこ
れを用いても同等の効果がある。Further, by setting an appropriate temperature, a silicide layer of these metals can be formed and the same effect can be obtained by using this instead of the metal layer of the embodiment.
例えば、コンタクトホール内のＳｉ基板上にＴｉＣ１，
の薄層を吸着し、４００℃に加熱してＴｉ５ｉｔを形成
する。For example, TiC1,
A thin layer of Ti5it is adsorbed and heated to 400°C to form Ti5it.
また、これらの金属は直接埋込層としても用いることが
できる。Furthermore, these metals can also be used as a directly buried layer.
また、配線膜にもこれらの材料を用いることができる。Further, these materials can also be used for the wiring film.
さらに、配線膜形成に際しＣＶＤ、 ＰＶＤ法の選択も
可能となる。Furthermore, it is also possible to select between CVD and PVD methods when forming wiring films.
第２図（Ａ）、 （Ｂ）は従来例と対比して実施例の効
果を示すデータの説明図である。。FIGS. 2A and 2B are explanatory diagrams of data showing the effects of the embodiment in comparison with the conventional example. .
第２図（Ａ）はＷ／５ｉ（ｎ＋）およびＷ／５ｉ（ｐ”
）のコンタクト抵抗Ｒ６を示す。Figure 2 (A) shows W/5i(n+) and W/5i(p”
) shows the contact resistance R6.
ここで、コンタクト抵抗は多数のコンタクトを直列にし
て測定した相対値で示される。Here, the contact resistance is expressed as a relative value measured by connecting a large number of contacts in series.
この場合は、 Ａｌの吸着を利用している。In this case, adsorption of Al is utilized.
第２図（Ｂ）はＳｉの浸食をλ単位で示す。FIG. 2(B) shows the Si erosion in units of λ.
図より、実施例の浸食は従来例に比し半減していること
が分かる。From the figure, it can be seen that the erosion in the example is reduced by half compared to the conventional example.
この場合は、 ＷＦ、の吸着を利用している。In this case, adsorption of WF is utilized.
つぎに、被膜の剥離と異常成長の改善された具体例を従
来例に対比して説明する。Next, a specific example in which film peeling and abnormal growth are improved will be explained in comparison with a conventional example.
剥離は９例えばＷのＣＶＤでは、従来例で２２０℃以下
では顕著であったが、実施例では１００８Ｃでも起きな
かった。For example, in CVD of W, peeling was noticeable at 220° C. or lower in the conventional example, but it did not occur even at 1008° C. in the example.
異常成長は前記のような形状変化をともなうため目視で
確認できる。その結果、従来例で認められた。異常成長
は、実施例では全く認められなかった。Abnormal growth is accompanied by the above-mentioned shape change and can be visually confirmed. As a result, this was observed in the conventional example. Abnormal growth was not observed at all in the examples.
以上説明したように本発明によれば、剥離や浸食や異常
成長等のない安定したＣＶＤ法によるコンタクトホール
の埋込と配線膜の形成が可能となった。As explained above, according to the present invention, it is possible to fill contact holes and form a wiring film by stable CVD method without peeling, erosion, abnormal growth, etc.
第１図（Ａ）〜（Ｃ）は本発明の一実施例を説明する断
面図。
第２図（Ａ）、（Ｂ）は従来例と対比して実施例の効果
を示すデータの説明図である。。
図において。
１はＳｉ基板。
２は絶縁膜で５ｉ０２膜。
３はコンタクトホール。
４は吸着層。
４Ａは金属膜。
５は埋込層。
６は第２の吸着膜。
６Ａは第２の金属膜。
７は配線膜
（Ａ）、 （Ｂ） （Ｃ）
（Ａ） （１３）寅枡伊１のｆ
ｊ１果／）説明図
罫 ２ ロFIGS. 1A to 1C are cross-sectional views illustrating an embodiment of the present invention. FIGS. 2A and 2B are explanatory diagrams of data showing the effects of the embodiment in comparison with the conventional example. . In fig. 1 is a Si substrate. 2 is an insulating film and is a 5i02 film. 3 is the contact hole. 4 is an adsorption layer. 4A is a metal film. 5 is the embedded layer. 6 is the second adsorption film. 6A is the second metal film. 7 is wiring film (A), (B) (C)
(A) (13) Toramasui 1 f
j1 result /) explanatory diagram border 2 b
Claims (1)
有機化合物を吸着させる工程と、該吸着物を熱、光また
はＲＦ電力を加えて還元雰囲気中で反応させて該基板上
に金属膜を形成する工程と、 該金属膜上に導電膜を成膜する工程とを有することを特
徴とする半導体装置の製造方法。２）前記金属がＷ、Ｔ
ｉ、Ｍｏ、Ｔａ、Ｈｆ、Ｚｒ、Ｃｕ、Ａｌ、Ａｕである
ことを特徴とする請求項１記載の半導体装置の製造方法
。 ３）還元ガスを被成長基板上に吸着させた後、前記の３
工程を行うことを特徴とする請求項１記載の半導体装置
の製造方法。 ４）前記還元ガスは水素、III、IV、Ｖ族元素を含む水
素化物またはハロゲン化物であることを特徴とする請求
項３記載の半導体装置の製造方法。[Claims] 1) A step of adsorbing a metal halide or a metal organic compound onto a growth substrate, and reacting the adsorbed substance in a reducing atmosphere by applying heat, light or RF power to the substrate. A method for manufacturing a semiconductor device, comprising the steps of: forming a metal film thereon; and forming a conductive film on the metal film. 2) The metal is W, T
2. The method for manufacturing a semiconductor device according to claim 1, wherein the material is i, Mo, Ta, Hf, Zr, Cu, Al, or Au. 3) After adsorbing the reducing gas onto the growth substrate, proceed as described in 3.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: 4) The method for manufacturing a semiconductor device according to claim 3, wherein the reducing gas is hydrogen, a hydride or a halide containing a group III, IV, or V element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32749190A JPH04196418A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32749190A JPH04196418A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04196418A true JPH04196418A (en) | 1992-07-16 |
Family
ID=18199750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32749190A Pending JPH04196418A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04196418A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355545B1 (en) | 1999-06-03 | 2002-03-12 | Semiconductor Leading Edge Technologies, Inc. | Method and apparatus for wiring, wire, and integrated circuit |
| WO2008053625A1 (en) * | 2006-10-30 | 2008-05-08 | Tokyo Electron Limited | Method of film deposition and apparatus for treating substrate |
-
1990
- 1990-11-28 JP JP32749190A patent/JPH04196418A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355545B1 (en) | 1999-06-03 | 2002-03-12 | Semiconductor Leading Edge Technologies, Inc. | Method and apparatus for wiring, wire, and integrated circuit |
| WO2008053625A1 (en) * | 2006-10-30 | 2008-05-08 | Tokyo Electron Limited | Method of film deposition and apparatus for treating substrate |
| JP2008112803A (en) * | 2006-10-30 | 2008-05-15 | Tokyo Electron Ltd | Film forming method, and substrate processing apparatus |
| US7981794B2 (en) | 2006-10-30 | 2011-07-19 | Tokyo Electron Limited | Film forming method and substrate processing apparatus |
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