JPH04188812A - Composite ceramic capacitor and manufactuer thereof - Google Patents
Composite ceramic capacitor and manufactuer thereofInfo
- Publication number
- JPH04188812A JPH04188812A JP2319335A JP31933590A JPH04188812A JP H04188812 A JPH04188812 A JP H04188812A JP 2319335 A JP2319335 A JP 2319335A JP 31933590 A JP31933590 A JP 31933590A JP H04188812 A JPH04188812 A JP H04188812A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- composite ceramic
- ceramic capacitor
- plating layer
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 37
- 239000002131 composite material Substances 0.000 title claims description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 229910052718 tin Inorganic materials 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 12
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 23
- 239000000919 ceramic Substances 0.000 claims description 12
- 238000010304 firing Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 230000000379 polymerizing effect Effects 0.000 claims description 3
- 239000002003 electrode paste Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 17
- 239000002184 metal Substances 0.000 abstract description 17
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000002648 laminated material Substances 0.000 abstract 1
- 238000009736 wetting Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 239000007767 bonding agent Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910000510 noble metal Inorganic materials 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はベアチップの積重ね体の端部に端子電極として
焼付は電極層を設けた複合セラミックコンデンサ及びそ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite ceramic capacitor in which an electrode layer is baked as a terminal electrode on the end of a stack of bare chips, and a method for manufacturing the same.
［従来の技術］
積層セラミックコンデンサは、内部電極として電極材料
を印刷したセラミック誘電体を積層した後、これを焼成
してベアチップを形成し、このべアチップの外面に内部
電極に導通する端子電極を形成して作製される。[Prior Art] Multilayer ceramic capacitors are manufactured by laminating ceramic dielectrics printed with electrode materials as internal electrodes, then firing them to form a bare chip, and forming terminal electrodes on the outer surface of this bare chip that are conductive to the internal electrodes. Created by forming.
この積層セラミックコンデンサを高容量化するための手
段として、構成するセラミ・ンク誘電体を大型にしかつ
多層化する方法、或いは構成するセラミック誘電体を高
誘電率化する方法が試みられている。しかし、前者の方
法は多層化が技術的に困難で歩留りの低下が大きく、後
者の方法は量産に適した高誘電率のセラミック誘電体が
開発されていないため、ともに工業上現実的でない。As a means for increasing the capacitance of this multilayer ceramic capacitor, attempts have been made to increase the size and multilayer of the ceramic dielectric that constitutes the capacitor, or to increase the dielectric constant of the ceramic dielectric that constitutes the capacitor. However, the former method is technically difficult to multilayer, resulting in a large drop in yield, and the latter method is industrially impractical because a ceramic dielectric with a high dielectric constant suitable for mass production has not been developed.
このため、従来より複数個の積層セラミ・ンクコンデン
サをチップコンデンサの形態で接着剤を介して重合した
複合セラミックコンデンサが高容量化したコンデンサと
して量産されている。For this reason, composite ceramic capacitors in which multiple laminated ceramic capacitors are polymerized via an adhesive in the form of a chip capacitor have been mass-produced as high-capacity capacitors.
この複合セラミックコンデンサの製法は、第６図に示す
ように、ベアチップを作製する工程Ａと、このベアチッ
プの端部にペースト状電極材料を塗布して端子電極を付
する工程Ｂと、この電極を焼付けて焼付は電極層を形成
する工程Ｃと、このチップコンデンサを接着剤を介して
重合して積重ね体を形成する工程りと、この積重ね体の
端部に金属板を配置する工程Ｅと、この金属板を高温は
んだ又は熱硬化型導電性樹脂の導電性接合剤により接着
して積重ね体端部に現れる複数の端子電極同士を電気的
に接続する工程Ｆと、更にはんだ付けの場合にはフラッ
クスの洗浄工程Ｇをこの順に含む。上記工程Ｆは第７図
に示され、ここで、１は積重ね体、２は金属板、３は導
電性接合剤、４は焼付は電極層である。As shown in Fig. 6, the manufacturing method for this composite ceramic capacitor includes a step A of manufacturing a bare chip, a step B of applying a paste electrode material to the end of the bare chip and attaching a terminal electrode, and a step B of manufacturing the bare chip. Baking is a step C of forming an electrode layer, a step of polymerizing this chip capacitor via an adhesive to form a stacked body, and a step E of arranging a metal plate at the end of this stacked body. A process F in which the metal plates are bonded using high-temperature solder or a conductive bonding agent made of thermosetting conductive resin to electrically connect a plurality of terminal electrodes appearing at the ends of the stack; A flux cleaning step G is included in this order. The above process F is shown in FIG. 7, where 1 is a stacked body, 2 is a metal plate, 3 is a conductive bonding agent, and 4 is a baked electrode layer.
［発明が解決しようとする課題］
しかし、従来の複合セラミックコンデンサの製法はＡ−
Ｇの多くの工程を要し、しかも工程Ｃ及び工程Ｆではベ
アチップの端部に繰返し熱衝撃を与える。このため、端
子電極内側のベアチップにクラックが生じ易く、コンデ
ンサの絶縁抵抗が劣化し易い。[Problem to be solved by the invention] However, the conventional method for manufacturing composite ceramic capacitors is A-
It requires many steps G, and in addition, in steps C and F, thermal shock is repeatedly applied to the end of the bare chip. For this reason, cracks are likely to occur in the bare chip inside the terminal electrode, and the insulation resistance of the capacitor is likely to deteriorate.
また導電性接合剤として熱硬化型導電性樹脂を用いた場
合には、積重ね体の端部に金属板を接着する際に導電性
樹脂か金属板の外側に容易にはみ出るため、第一に積重
ね体の端部を汚して複合セラミックコンデンサの見栄え
を悪くし、第二に金属板を基板にはんだ付けするときに
導電性樹脂にはんだか乗らず、はんだ乗り不良を起こす
問題点かあった。In addition, when thermosetting conductive resin is used as a conductive bonding agent, the conductive resin easily protrudes to the outside of the metal plates when bonding the metal plates to the ends of the stack. The ends of the capacitor were contaminated, making the composite ceramic capacitor look bad.Secondly, when the metal plate was soldered to the board, the solder did not adhere to the conductive resin, resulting in poor soldering.
更にいずれの導電性接合剤を用いた場合にも、積重ね体
端部において金属板の煩雑な接着作業を行わなければな
らない不具合もあった。Furthermore, no matter which conductive bonding agent is used, there is also the problem that a complicated work of bonding the metal plates must be performed at the ends of the stack.
本発明の目的は、高容量で高耐電圧の性能を有し、コン
デンサとして要求される各種特性に優れた複合セラミッ
クコンデンサを提供することにある。An object of the present invention is to provide a composite ceramic capacitor that has high capacity, high withstand voltage performance, and is excellent in various characteristics required for a capacitor.
また本発明の別の目的は、少ない工程で安価にかつ容易
にしかも見栄えよく製造し得る複合セラミックコンデン
サの製造方法を提供することにある。Another object of the present invention is to provide a method for manufacturing a composite ceramic capacitor that can be manufactured easily and at low cost through a small number of steps and with good appearance.
［課題を解決するための手段］
本発明者らは、金属板を用いることなく積重ね体の端部
に直接焼付は電極層からなる端子電極を形成することに
より、本発明に到達した。[Means for Solving the Problems] The present inventors have arrived at the present invention by forming terminal electrodes made of electrode layers directly baked on the ends of stacked bodies without using metal plates.
第１図に示すように、本発明の複合セラミックコンデン
サ１０は、内部電極１５ａ（第１図拡大図）を有するベ
アチップ１１，１２，１３．１４゜１５を複数個重合し
て形成された積重ね体１７の端部に、全ての内部電極１
５ａ（他の４つの内部電極は図示せず、以下同じ。）を
電気的に並列接続しかつこの積重ね体１７の端部全体を
被包する焼付は電極層１８が形成されたものである。As shown in FIG. 1, a composite ceramic capacitor 10 of the present invention is a stacked body formed by polymerizing a plurality of bare chips 11, 12, 13.14° 15 having internal electrodes 15a (enlarged view in FIG. 1). At the end of 17, all internal electrodes 1
5a (the other four internal electrodes are not shown, the same applies hereinafter) are electrically connected in parallel and the entire end of this stacked body 17 is covered by baking to form an electrode layer 18.
以下、本発明を詳述する。The present invention will be explained in detail below.
本発明の複合セラミックコンデンサ１０を構成するベア
チップ１１〜１５は、内部電極１５ａを有するセラミッ
ク誘電体１１ｂ〜１５ｂが複数個積層焼成されて形成さ
れる。本明細書で、ベアチップとは公知の積層セラミッ
クチップコンデンサの外部電極が付いていない構造のも
のをいう。セラミック誘電体には、鉛系、チタン酸バリ
ウム系の誘電体が用いられ、内部電極にはＰｄ、Ｐｔ。The bare chips 11 to 15 constituting the composite ceramic capacitor 10 of the present invention are formed by laminating and firing a plurality of ceramic dielectrics 11b to 15b having internal electrodes 15a. In this specification, a bare chip refers to a known multilayer ceramic chip capacitor with no external electrodes. A lead-based or barium titanate-based dielectric is used for the ceramic dielectric, and Pd or Pt is used for the internal electrodes.
Ａ ｇ ／ Ｐ ｄ等の貴金属、或いはＮｉ、Ｆｅ、Ｃ
。Noble metals such as A g / P d, or Ni, Fe, C
.
等の卑金属が用いられる。Base metals such as
本発明の複合セラミックコンデンサ１０は、上記ベアチ
ップ１１〜１５を複数個それぞれチップ端部を揃えて重
合して積重ね体１７が形成される。In the composite ceramic capacitor 10 of the present invention, a stacked body 17 is formed by stacking a plurality of bare chips 11 to 15 with their respective chip ends aligned.
ベアチップの重合数は、第１図〜第４図では５個の例を
示すが、本発明はこれに限らない。この重合数は２個以
上であって、要求される静電容量、ベアチップの厚み等
に応じて決められる。Although the number of polymerized bare chips is five in FIGS. 1 to 4, the present invention is not limited thereto. The number of polymerizations is two or more and is determined depending on the required capacitance, the thickness of the bare chip, etc.
積重ね体１７の端部には厚さ６０〜７０μｍの焼付は電
極層１８が形成される。この焼付は電極層を下地電極と
してこの表面にＮｉ、Ｓｎ又はＳｎ ／ Ｐ ｂのうち
少なくとも１種で形成されためつき層１９ａ又は１９ｂ
を有することが好ましい。An electrode layer 18 having a thickness of 60 to 70 μm is formed at the end of the stacked body 17. This baking is performed by using the electrode layer as a base electrode and forming a glazing layer 19a or 19b formed of at least one of Ni, Sn, and Sn/Pb on the surface.
It is preferable to have.
焼付は電極層１８の表面に厚みが１〜２μｍのＮｉめっ
き層１９ａを形成した後、このＮｉめつき層１９ａの上
に厚みが４〜５μｍのＳｎ又はＳｎ ／ Ｐ ｂめっき
層１９ｂを形成することがより好ましい。Ｎｉ層を内層
にしてＳｎ又はＳ ｎ ／ Ｐ ｂ層を外層にし、各め
っき層の厚みを上記範囲にするのは、焼付は電極層を耐
熱性のあるＮｉでより確実に保護し、かつＳｎ又はＳ
ｎ ／ Ｐ ｂ層で端子電極のはんだ濡れ性を高め、Ｎ
ｉの酸化を防止するためである。Baking is performed by forming a Ni plating layer 19a with a thickness of 1 to 2 μm on the surface of the electrode layer 18, and then forming a Sn or Sn/Pb plating layer 19b with a thickness of 4 to 5 μm on this Ni plating layer 19a. It is more preferable. The reason why the Ni layer is the inner layer and the Sn or Sn/Pb layer is the outer layer, and the thickness of each plating layer is within the above range, is that the baking protects the electrode layer more reliably with heat-resistant Ni, and the Sn or Sn/Pb layer is the outer layer. or S
The N/P b layer improves the solder wettability of the terminal electrode, and the N
This is to prevent oxidation of i.
これらのめっき層１９ａ、１９ｂは、無電解及び電解め
っき等をバレルめっきで行うことにより形成される。め
っき浴はＮｉ、Ｓｎ又はＳｎ／Ｐｂともそれぞれ公知の
ものを使用する。These plating layers 19a and 19b are formed by barrel plating, such as electroless plating and electrolytic plating. As the plating bath, a known plating bath is used for Ni, Sn, or Sn/Pb.
本発明の複合セラミックコンデンサを製造するには、先
ず複数個のベアチップを作製する（第５図Ａ）。このベ
アチップは、内部電極として電極材料を印刷したセラミ
ック誘電体を積層した後、これを焼成して形成される。To manufacture the composite ceramic capacitor of the present invention, first, a plurality of bare chips are manufactured (FIG. 5A). This bare chip is formed by laminating ceramic dielectrics printed with electrode materials as internal electrodes and then firing them.
次いで第２図及び第３図に示すように、本発明の複合セ
ラミックコンデンサ１０は、複数個のヘアチップ１１，
１２，１３，１４．１５がそれぞれチップ端部を揃えて
重合され積重ね体１７に形成される（第５図Ｂ）。これ
らのベアチップ間に接着剤を配して重合状態のベアチッ
プを仮止めしてもよいが、接着剤を用いずに積重ね体の
一方の端部に接着力の弱い接着テープを貼付して仮止め
してもよい。接着剤を用いる場合には、接着剤としては
焼成時に分解するポリビニルアルコール系、エチルセル
ロース系の樹脂接着剤が使用される。Next, as shown in FIGS. 2 and 3, the composite ceramic capacitor 10 of the present invention includes a plurality of hair chips 11,
12, 13, 14, and 15 are stacked with their respective chip ends aligned to form a stacked body 17 (FIG. 5B). It is possible to temporarily fix the polymerized bare chips by placing an adhesive between these bare chips, but it is also possible to temporarily fix the bare chips in a polymerized state by pasting an adhesive tape with weak adhesive strength to one end of the stack without using adhesive. You may. When an adhesive is used, a polyvinyl alcohol-based or ethyl cellulose-based resin adhesive that decomposes during firing is used.
次いで重合状態のベアチ・ツブを仮止めしたまま、積重
ね体の端部全体ににＡｇ、Ａｇ／Ｐｄ等の貴金属粉末に
ガラスフリットを加えたペーストを塗布して端子電極を
付す（第５図Ｃ）。接着テープで仮止めした場合には、
テープを貼付していない端部から塗布し、ペーストが乾
燥した後、そのペーストの上から積重ね体の端部を仮止
めし、今まで貼付してあったテープを剥いでからそこに
ペーストを塗布する。Next, while the polymerized Beachi tubes are temporarily fixed, a paste of noble metal powder such as Ag or Ag/Pd with glass frit is applied to the entire end of the stack to attach terminal electrodes (Fig. 5C). ). If temporarily fixed with adhesive tape,
Apply the paste from the edge that is not pasted, and after the paste has dried, temporarily secure the end of the stack over the paste, peel off the tape that was pasted, and then apply the paste there. do.
次に端部のペーストを乾燥した後、積重ね体を７００〜
８００℃の温度で処理し、ペーストを焼付けて端子電極
となる焼付は電極層１８を形成する（第５図Ｄ）。Next, after drying the paste on the edges, the stacked body is
The paste is processed at a temperature of 800° C. and the paste is baked to form a terminal electrode, forming an electrode layer 18 (FIG. 5D).
更にこの焼付は電極層１８の表面にＮｉめつき層１９ａ
に形成し、Ｎｉめっき層１９ａの表面にＳｎ又はＳ ｎ
／ Ｐ ｂめっき層１９ｂを形成すると、第１図に示
す複合セラミックコンデンサ１０が得られる。なお、導
電性樹脂層１８の表面にＳｎ又はＳ ｎ ／ Ｐ ｂめ
っき層１９ｂだけ形成してもよい。Furthermore, this baking creates a Ni plating layer 19a on the surface of the electrode layer 18.
Sn or Sn is formed on the surface of the Ni plating layer 19a.
/Pb When the plating layer 19b is formed, the composite ceramic capacitor 10 shown in FIG. 1 is obtained. Note that only the Sn or Sn/Pb plating layer 19b may be formed on the surface of the conductive resin layer 18.
［作 用］
本発明の複合セラミックコンデンサでは、従来の金属板
の機能及び重合したベアチップの接着機能を端部に設け
た焼付は電極層か果す。この焼付は電極層の表面にめっ
き層を設ければ、焼付は電極層の耐熱性、はんだ濡れ性
が高まる。[Function] In the composite ceramic capacitor of the present invention, the electrode layer performs the function of a conventional metal plate and the adhesion function of a polymerized bare chip at the end. If a plating layer is provided on the surface of the electrode layer, the heat resistance and solder wettability of the electrode layer will be improved.
［発明の効果］
以上述べたように、本発明によれば、従来と比べて工程
数が少なく、しかもヘアチップの端部が受ける熱衝撃回
数が少ないため、端子電極に熱的損傷を生じない。これ
により、高容量で高耐電圧の性能を有し、コンデンサと
して要求される各種特性を備え、信頼性に優れた複合セ
ラミックコンデンサが得られる。[Effects of the Invention] As described above, according to the present invention, the number of steps is smaller than that of the conventional method, and the number of thermal shocks that the end portion of the hair tip receives is small, so that no thermal damage occurs to the terminal electrode. As a result, a composite ceramic capacitor with high capacity, high withstand voltage performance, various characteristics required for a capacitor, and excellent reliability can be obtained.
また本発明によれば、金属板を用いないため、複合セラ
ミックコンデンサの端子電極の構成か単純化し、煩雑な
金属板の接合作業が不要となり、安価にかつ容易にしか
も見栄えよく製造することができる。Further, according to the present invention, since no metal plate is used, the structure of the terminal electrode of the composite ceramic capacitor is simplified, and the complicated work of joining metal plates is not required, making it possible to manufacture the capacitor at low cost, easily, and with good appearance. .
また焼付は電極層をめっき層で被覆することにより、焼
付は電極層の耐熱性、はんだ濡れ性を向上させることが
できる。Furthermore, baking can improve the heat resistance and solder wettability of the electrode layer by covering the electrode layer with a plating layer.
［実施例コ 次に本発明の実施例を比較例とともに詳しく説明する。[Example code] Next, examples of the present invention will be described in detail together with comparative examples.
〈実施例１〉
定格電圧２５Ｖで静電容量４７μＦの特性を有する長さ
５．７ｍｍＸ幅５．０ｍｍｘ高さ１１ｍｍのベアチップ
（ＥＩＡコード２２２０タイプ、三菱鉱業セメント側型
）を５個用意した。上記ベアチップは、鉛ペロブスカイ
ト系のセラミック誘電体にＰｄの内部電極を有する。５
個のベアチップを各チップ端部を揃えて重合して長さ５
．７ｍｍＸ幅５．０ｍｍＸ高さ５．０ｍｍの積重ね体を
形成した。<Example 1> Five bare chips (EIA code 2220 type, Mitsubishi Mining Cement side type) with a length of 5.7 mm, width of 5.0 mm, and height of 11 mm having characteristics of a rated voltage of 25 V and a capacitance of 47 μF were prepared. The bare chip has a Pd internal electrode on a lead perovskite ceramic dielectric. 5
A total of 5 bare chips are stacked together with the ends of each chip aligned to form a length of 5.
．． A stack of 7 mm x width 5.0 mm x height 5.0 mm was formed.
接着力の弱いテープで重合したベアチップを仮止めしな
がら、積重ね体の両端部にＡｇ／Ｐｄの貴金属粉末にガ
ラスフリットを加えたペーストを塗布して端子電極を付
した。この塗布したペーストが乾燥した後、積重ね体を
７００〜８００℃の温度で処理し、ペーストを焼付けて
端子電極となる焼付は電極層を形成し、複合セラミック
コンデンサを得た。While temporarily fixing the polymerized bare chips with a tape with weak adhesive strength, a paste of Ag/Pd noble metal powder and glass frit was applied to both ends of the stack to attach terminal electrodes. After the applied paste had dried, the stack was treated at a temperature of 700 to 800° C., and the paste was baked to form an electrode layer to form a terminal electrode, thereby obtaining a composite ceramic capacitor.
く比較例１〉
実施例１と同一のベアチップの端部にガラスフリットを
含んだＡｇペーストの焼付は電極層を外部電極として形
成した積層セラミックチップコンデンサを５個用意し、
これらのチップコンデンサをエポキシ系樹脂接着剤（ウ
ルトラダイン＃５１１．ＩＷ−５、四国化成工業側型）
を介して重合した後、１２０℃の温度で自重により接着
して積重ね体を得た。Comparative Example 1> Baking of Ag paste containing glass frit on the end of the same bare chip as in Example 1 was carried out by preparing five multilayer ceramic chip capacitors with electrode layers formed as external electrodes.
These chip capacitors are glued with epoxy resin adhesive (Ultradyne #511.IW-5, Shikoku Kasei Kogyo type)
After polymerization, the mixture was adhered by its own weight at a temperature of 120° C. to obtain a stack.
この積重ね体の端部に、端子電極として、融点２９０℃
の高温クリームはんだを均一に塗布し、このはんだの上
から表面をＳ ｎ／Ｐ ｂ （９： １）のめっき処理
した、板厚が０．１ ｍｍの銅製の金属板を配してリフ
ロー炉で外部電極同士を金属板により電気的に接続して
複合セラミックコンデンサを得た。A terminal electrode with a melting point of 290°C is placed at the end of this stack.
A 0.1 mm thick copper metal plate whose surface was plated with Sn/P b (9:1) was placed over the solder and placed in a reflow oven. A composite ceramic capacitor was obtained by electrically connecting the external electrodes with each other using a metal plate.
上記実施例１及び比較例１で作製した複合セラミックコ
ンデンサに対して、諸特性を次の方法により調べた。Various characteristics of the composite ceramic capacitors manufactured in Example 1 and Comparative Example 1 were investigated using the following methods.
（ａ）静電容量（μＦ）及び誘電正接（％）１ｋＨｚ、
ＩＶｒｍｓで測定した。(a) Capacitance (μF) and dielectric loss tangent (%) 1kHz,
Measured by IVrms.
（ｂ）絶縁抵抗（Ω）
２５Ｖの直流電圧を印加した後１．３０秒経過後の抵抗
を測定した。(b) Insulation resistance (Ω) The resistance was measured 1.30 seconds after applying a DC voltage of 25V.
（ｃ）直流破壊電圧（Ｖ）
昇圧速度７０Ｖ／秒で直流電圧を印加し、絶縁破壊を生
じたときの電圧を測定した。(c) DC breakdown voltage (V) A DC voltage was applied at a boost rate of 70 V/sec, and the voltage at which dielectric breakdown occurred was measured.
（ｄ）初期不良
定格の２．５倍の電圧を印加したときに破壊したか否か
調べ、破壊した試料数を数えた。(d) It was investigated whether or not the sample broke when a voltage 2.5 times the initial failure rating was applied, and the number of samples that broke was counted.
実施例１及び比較例１の複合セラミックコンデンサを上
記（ａ）〜（Ｃ）についてはそれぞれ３０個ずつ試験し
、上記（ｄ）については１００個確認した。Thirty composite ceramic capacitors of Example 1 and Comparative Example 1 were tested for each of the above (a) to (C), and 100 were tested for the above (d).
その結果を第１表に示す。表において、Ｍａｘは最大値
、Ｍｉｎは最小値、σ７−２は標準偏差をそれぞれ示す
。The results are shown in Table 1. In the table, Max indicates the maximum value, Min indicates the minimum value, and σ7-2 indicates the standard deviation.
第 １ 表
第１表より、比較例１のコンデンサに初期不良が見られ
たのに対して実施例１のコンデンサには初期不良のもの
はなく、実施例１のコンデンサが比較例１のコンデンサ
より優れていることが明らかとなった。Table 1 From Table 1, initial failures were observed in the capacitor of Comparative Example 1, whereas there were no initial failures in the capacitors of Example 1, and the capacitor of Example 1 was found to be more defective than the capacitor of Comparative Example 1. It turned out to be excellent.
また実施例１のコンデンサは比較例１と同等の高容量で
高耐電圧のコンデンサ特性を具備していた。Further, the capacitor of Example 1 had capacitor characteristics of high capacity and high voltage resistance equivalent to those of Comparative Example 1.
第１図は本発明の複合セラミックコンデンサの断面図。
第２図、第３図及び第４図はその複合セラミックコンデ
ンサを製造する過程を示す断面図。
第５図はその複合セラミックコンデンサの製造工程図。
第６図は従来例の複合セラミックコンデンサの製造工程
図。
第７図は従来例の金属板を接着する状況を示す斜視図。
１ｏ二複合セラミックコンデンサ、
１１〜１５：ベアチップ、
１５ａ：内部電極、
１１３〜１５ａ：セラミック誘電体、
１７：積重ね体、
１８二焼付は電極層、
１９ａ、１９ｂ：めっき層。
マ二 −−
Ｎ−一゛
、” ／ ｙ ＼１１
第２図
第３図
第４図
第６図FIG. 1 is a sectional view of the composite ceramic capacitor of the present invention. FIGS. 2, 3, and 4 are cross-sectional views showing the process of manufacturing the composite ceramic capacitor. Figure 5 is a diagram of the manufacturing process of the composite ceramic capacitor. FIG. 6 is a manufacturing process diagram of a conventional composite ceramic capacitor. FIG. 7 is a perspective view showing a state in which metal plates are bonded in a conventional example. 1o2 composite ceramic capacitor, 11-15: bare chip, 15a: internal electrode, 113-15a: ceramic dielectric, 17: stacked body, 182 baked electrode layer, 19a, 19b: plating layer. Manny -- N-1゛," / y \11 Figure 2 Figure 3 Figure 4 Figure 6
Claims (1)
５）を複数個重合して形成された積重ね体（１７）の端
部に、全ての前記内部電極（１５ａ）を電気的に並列接
続しかつ前記積重ね体（１７）の端部全体を被包する焼
付け電極層（１８）が形成された複合セラミックコンデ
ンサ。 ２）焼付け電極層（１８）の表面にめっき層（１９ａ，
１９ｂ）が被覆された請求項１記載の複合セラミックコ
ンデンサ。 ３）めっき層がＮｉ，Ｓｎ又はＳｎ／Ｐｂの少なくとも
１種のめっき層により構成された請求項２記載の複合セ
ラミックコンデンサ。 ４）めっき層がＮｉめっき層（１９ａ）とこのＮｉめっ
き層（１９ａ）の上に形成されたＳｎ又はＳｎ／Ｐｂめ
っき層（１９ｂ）により構成された請求項３記載の複合
セラミックコンデンサ。 ５）内部電極（１５ａ）を有するセラミック誘電体（１
１ｂ〜１５ｂ）を積層焼成したベアチップ（１１〜１５
）を複数個各チップ端部を揃えて積重ね、 この積重ねて形成された積重ね体（１７）の端部に全て
の前記内部電極（１５ａ）を電気的に並列接続し、かつ
前記積重ね体（１７）の端部全体を被包するように端子
電極用ペーストを塗布し、 このペーストを焼付けて焼付け電極層（１８）を形成す
る複合セラミックコンデンサの製造方法。 ６）焼付け電極層（１８）の表面にめっき層（１９ａ，
１９ｂ）を形成する複合セラミックコンデンサの製造方
法。[Claims] 1) Bare chips (11 to 1) having internal electrodes (15a)
All the internal electrodes (15a) are electrically connected in parallel to the end of a stack (17) formed by polymerizing a plurality of 5), and the entire end of the stack (17) is covered. A composite ceramic capacitor on which a baked electrode layer (18) is formed. 2) Plating layer (19a,
19. The composite ceramic capacitor according to claim 1, coated with 19b). 3) The composite ceramic capacitor according to claim 2, wherein the plating layer is composed of at least one type of plating layer of Ni, Sn, or Sn/Pb. 4) The composite ceramic capacitor according to claim 3, wherein the plating layer is composed of a Ni plating layer (19a) and a Sn or Sn/Pb plating layer (19b) formed on the Ni plating layer (19a). 5) Ceramic dielectric (1) with internal electrodes (15a)
Bare chips (11 to 15) obtained by laminating and firing 1b to 15b)
) are stacked with their chip ends aligned, all the internal electrodes (15a) are electrically connected in parallel to the ends of the stacked body (17) formed by stacking, and the stacked body (17 ) A method for manufacturing a composite ceramic capacitor in which a terminal electrode paste is applied to cover the entire end of the capacitor, and the paste is baked to form a baked electrode layer (18). 6) Plating layer (19a,
19b) A method for manufacturing a composite ceramic capacitor forming a composite ceramic capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319335A JPH04188812A (en) | 1990-11-22 | 1990-11-22 | Composite ceramic capacitor and manufactuer thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319335A JPH04188812A (en) | 1990-11-22 | 1990-11-22 | Composite ceramic capacitor and manufactuer thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04188812A true JPH04188812A (en) | 1992-07-07 |
Family
ID=18109030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2319335A Pending JPH04188812A (en) | 1990-11-22 | 1990-11-22 | Composite ceramic capacitor and manufactuer thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04188812A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835338A (en) * | 1995-10-03 | 1998-11-10 | Tdk Corporation | Multilayer ceramic capacitor |
| US11195659B2 (en) | 2002-04-15 | 2021-12-07 | Avx Corporation | Plated terminations |
-
1990
- 1990-11-22 JP JP2319335A patent/JPH04188812A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835338A (en) * | 1995-10-03 | 1998-11-10 | Tdk Corporation | Multilayer ceramic capacitor |
| US11195659B2 (en) | 2002-04-15 | 2021-12-07 | Avx Corporation | Plated terminations |
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