JPH04186774A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04186774A JPH04186774A JP2314000A JP31400090A JPH04186774A JP H04186774 A JPH04186774 A JP H04186774A JP 2314000 A JP2314000 A JP 2314000A JP 31400090 A JP31400090 A JP 31400090A JP H04186774 A JPH04186774 A JP H04186774A
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- layer
- conductivity type
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 139
- 239000000758 substrate Substances 0.000 abstract description 15
- 238000005452 bending Methods 0.000 abstract description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＭＯＳトランジスタを半導体基板内に有する
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a MOS transistor in a semiconductor substrate.
従来、ＭＯＳ）−ランジスタ構造としてはセミコンダク
ター・デバイシズーフィジックス アンドテクノロジー
（Ｓ、Ｍ、Ｓ’ｚ ｅ著、１９８５）の図３４に示され
ているような構造、すなわち第２図に示すような構造が
最も基本的な構造としてよく知られていた。Traditionally, the MOS)-transistor structure is as shown in Figure 34 of Semiconductor Devices, Physics and Technology (S, M, S'ze, 1985), that is, as shown in Figure 2. The structure was well known as the most basic structure.
第２図はｎチャネルＭＯＳトランジスタの断面構造であ
り、ここで２１はｐ型Ｓｉ基板、２２はフィールド酸化
膜、２３．２４はソース、ドレイン不純物層、２５はポ
リＳｉゲート電極、２６はゲート酸化膜である。Figure 2 shows the cross-sectional structure of an n-channel MOS transistor, where 21 is a p-type Si substrate, 22 is a field oxide film, 23 and 24 are source and drain impurity layers, 25 is a poly-Si gate electrode, and 26 is a gate oxide film. It is a membrane.
この第２図の単純構造では、デバイス寸法を微細化した
時、パンチスルーを防止するためには基板不純物濃度を
増加する必要があり、これにより電気伝導度の低下とし
きい値電圧増加を生じると言う問題がある。In the simple structure shown in Figure 2, when the device size is miniaturized, it is necessary to increase the substrate impurity concentration to prevent punch-through, which causes a decrease in electrical conductivity and an increase in threshold voltage. I have a problem to say.
この基本構造よりもチャネルの電気伝導度と動作電流を
増加できるＭＯＳトランジスタ構造としては、特開昭６
１−３２４６２号公報、特開昭６３−１６９０６５号公
報、特開昭６３−１７７４７０号公報にて論じられてい
るようにＳｉ表面のチャネル部を低不純物濃度にした構
造があり、その断面構造を第３図に示す。As a MOS transistor structure that can increase the electrical conductivity of the channel and the operating current compared to this basic structure,
As discussed in JP-A No. 1-32462, JP-A-63-169065, and JP-A-63-177470, there is a structure in which the channel portion of the Si surface has a low impurity concentration, and its cross-sectional structure is It is shown in Figure 3.
第３図においては、３１はｐ型Ｓ１基板（またはウェル
）、３２はフィールド酸化膜、３３は３１よりも一桁以
上、不純物濃度の低いｐ型Ｓｉ層でありチャネル部とな
る。３４．３５はソース。In FIG. 3, 31 is a p-type S1 substrate (or well), 32 is a field oxide film, and 33 is a p-type Si layer whose impurity concentration is one order of magnitude lower than that of 31, and serves as a channel portion. 34.35 is the sauce.
ドレインとなるｎ型高不純物濃度領域で、３６はポリＳ
ｉ電極、３７はゲート酸化膜である。36 is an n-type high impurity concentration region that becomes a drain.
The i-electrode 37 is a gate oxide film.
第３図において、ｐ型Ｓｉ基板３１の不純物濃度を比較
的に高い値に設定することによって、ドレイン３５から
ソース３４への空乏層の伸びが抑制されるので、パンチ
スルーを防止することが可能となる６また、Ｐ型Ｓｉ基
板３１の高不純物濃度にもかかわらず、ゲート酸化膜３
７で被覆されたＳｉ表面の不純物濃度は低不純物濃度チ
ャネル部３３によって比較的低い値に設定されているの
で、チャネル部で高い表面移動度を得ることが可能とな
る。In FIG. 3, by setting the impurity concentration of the p-type Si substrate 31 to a relatively high value, the extension of the depletion layer from the drain 35 to the source 34 is suppressed, making it possible to prevent punch-through. 6 Also, despite the high impurity concentration of the P-type Si substrate 31, the gate oxide film 3
Since the impurity concentration on the Si surface covered with 7 is set to a relatively low value by the low impurity concentration channel portion 33, it is possible to obtain high surface mobility in the channel portion.
尚、第３図に示すように、従来、低不純物濃度チャネル
部３３がソース、ドレインｎ型高不純物濃度領域３４．
３５より浅く形成されているが、ソース、ドレイン領域
３４，３５より低不純物濃度チャネル部３３を深く形成
すると、この深く形成された低不純物濃度チャネル部３
３の内部でドレイン３５からソース３４へ空乏層の伸び
てしまい、パンチスルーを防止することができなくなる
と当業者が考えていたものと推定される。As shown in FIG. 3, conventionally, the low impurity concentration channel portion 33 is the source and drain n-type high impurity concentration regions 34.
However, if the low impurity concentration channel part 33 is formed deeper than the source and drain regions 34 and 35, this deeply formed low impurity concentration channel part 3
It is presumed that those skilled in the art thought that the depletion layer would extend from the drain 35 to the source 34 inside the transistor 3, making it impossible to prevent punch-through.
上述したように第３図のＭＯ５構造によって、パンチス
ルー防止とチャネル部でのキャリアの高移動度を一応達
成することが可能であるが、チャネル部でのキャリアの
高移動度化は充分なものではないことが本発明者等の検
討により明らかとされた。As mentioned above, with the MO5 structure shown in Figure 3, it is possible to prevent punch-through and achieve high carrier mobility in the channel part, but the high carrier mobility in the channel part is not sufficient. It has become clear through studies by the inventors that this is not the case.
すなわち、第２図に示した従来の単純なＭＯＳトランジ
スタ構造でパンチスルーを防止する場合と比較して、第
３図に示した従来のＭＯＳトランジスタ構造では低不純
物濃度チャネル層３３によってＳｉ表面の電界が緩和さ
れ、またＳｉ表面のエネルギーバンドの曲がり緩やかと
なり、電気伝導度が向上し高速に動作する。That is, compared to the conventional simple MOS transistor structure shown in FIG. 2 in which punch-through is prevented, in the conventional MOS transistor structure shown in FIG. is relaxed, and the energy band on the Si surface curves gently, improving electrical conductivity and allowing high-speed operation.
第４図は、第２図および第３図のＭＯ８構造のＳｉ表面
のエネルギーバンドの曲がりを示したものであり、第３
図のＭＯ８構造の方がチャネル表面でキャリアが移動可
能なｎ型反転層の幅が拡大されており、キャリア移動化
が改善される。Figure 4 shows the bending of the energy band of the Si surface of the MO8 structure in Figures 2 and 3.
In the MO8 structure shown in the figure, the width of the n-type inversion layer in which carriers can move on the channel surface is expanded, and carrier movement is improved.
しかしながら、第４図に示したように第３図の場合のキ
ャリアが移動可能なｎ型反転層の幅も充分なものではな
く、キャリア移動度の改善に余地のあることが明らかと
されたものである。However, as shown in FIG. 4, the width of the n-type inversion layer in which carriers can move in the case of FIG. 3 is not sufficient, and it is clear that there is room for improvement in carrier mobility. It is.
従って、本発明の目的はデバイス寸法が微細化されたＭ
ＯＳトランジスタ構造において、パンチスルーを防止す
るとともに、Ｓｉ表面のキャリア移動度を更に改善する
ことにある。Therefore, an object of the present invention is to
The object of the present invention is to prevent punch-through and further improve carrier mobility on the Si surface in an OS transistor structure.
かくして、本発明の具体的な目的は、特にチャネル長１
μｍ以下の低不純物濃度チャネルトランジスタに関して
、パンチスルーを防止しながら従来よりも高速に動作で
きるデバイス構造を提供することである。Thus, a specific object of the present invention is that, in particular, the channel length 1
It is an object of the present invention to provide a device structure that can operate at higher speeds than conventional ones while preventing punch-through regarding a channel transistor with a low impurity concentration of .mu.m or less.
一方、第３図に示した低不純物濃度チャネル層３３を有
する従来のＭＯＳトランジスタ構造では、ソース、ドレ
イン高不純物濃度層３４．３５が低不純物濃度チャネル
層３３よりも深く形成されているため、ソース、ドレイ
ン高不純物濃度層３４゜３５の下面が直接、高不純物濃
度Ｓｉ基板３１に接していた。このため、ソース、ドレ
イン高不純物濃度層３４．３５と高不純物濃度Ｓｉ基板
３１との間のリーク電流が大きいと言う問題を有してい
た。On the other hand, in the conventional MOS transistor structure having the low impurity concentration channel layer 33 shown in FIG. The lower surfaces of the drain high impurity concentration layers 34 and 35 were in direct contact with the high impurity concentration Si substrate 31. Therefore, there was a problem in that the leakage current between the source/drain high impurity concentration layers 34 and 35 and the high impurity concentration Si substrate 31 was large.
従って、発明の他の目的は、ソース、ドレイン高不純物
濃度層のリーク電流を低減したＭＯＳトランジスタ構造
を提供することである。Therefore, another object of the invention is to provide a MOS transistor structure in which the leakage current of the source and drain high impurity concentration layers is reduced.
さらに、これまでの低不純物濃度チャネル層を有するＭ
ＯＳトランジスタ構造では、低不純物濃度チャネル層の
導電型がその下の高不純物濃度のＳｉ基板の導電型と同
一であるのに加え、この低不純物濃度チャネル層が少量
の反対導電型不純物を含む場合が多かった。そして、反
対導電型不純物が低不純物濃度チャネル層に含まれてい
るため、低温動作でＩ−Ｖ特性にキングが生じるとの問
題があった。Furthermore, M with a conventional low impurity concentration channel layer
In an OS transistor structure, when the conductivity type of the low impurity concentration channel layer is the same as that of the underlying high impurity concentration Si substrate, this low impurity concentration channel layer contains a small amount of impurity of the opposite conductivity type. There were many. Furthermore, since the opposite conductivity type impurity is contained in the low impurity concentration channel layer, there is a problem that a king occurs in the IV characteristic at low temperature operation.
従って、本発明の他の一つの目的は、低温動作でＩ−Ｖ
特性にキングが生じるのを防止し、低温特性の良好な低
不純物濃度チャネルを有するＭＯＳトランジスタを提供
することである。Therefore, another object of the present invention is to
It is an object of the present invention to provide a MOS transistor having a low impurity concentration channel that prevents the occurrence of a king in characteristics and has good low temperature characteristics.
上記目的を達成するために、本発明の代表的な実施例は
第１図に示すように、高不純物濃度の半導体基板領域（
またはウェル領域）１上に、ノンドープＳｉのエピタキ
シャル成長によって単結晶Ｓｉ層３を形成し、この成長
層３中の低不純物濃度層８の厚さをソース、ドレイン不
純物層４，５の深さより厚くしたものである。In order to achieve the above object, a typical embodiment of the present invention has a semiconductor substrate region with a high impurity concentration (
(or well region) 1, a single crystal Si layer 3 is formed by epitaxial growth of non-doped Si, and the thickness of the low impurity concentration layer 8 in this grown layer 3 is made thicker than the depth of the source and drain impurity layers 4 and 5. It is something.
またプロセス温度を下げ、しきい値電圧制御用のチャネ
ル・イオン打ち込みを行なわないようにすることで、エ
ピタキシャル成長層３中の表面低不純物濃度層８の濃度
は、その下側の高不純物濃度層９ （高不純物濃度の半
導体基板領域１とその上の不純物オートドープ領域とに
より形成される層）の不純物濃度の一桁以下に設定され
たものである。Furthermore, by lowering the process temperature and not performing channel ion implantation for threshold voltage control, the concentration of the surface low impurity concentration layer 8 in the epitaxial growth layer 3 can be reduced by lowering the concentration of the lower high impurity concentration layer 9. The impurity concentration is set to one digit or less of the impurity concentration (layer formed by the semiconductor substrate region 1 with high impurity concentration and the impurity autodoped region thereon).
さらにチャネル長１μｍ以下の微細化されたＭＯＳトラ
ンジスタにおいてそのパンチスルーをほぼ完全に抑止す
るため、ソース、ドレイン不純物層４．５の下面と表面
低不純物濃度層８の下面の間の距離ａをチャネル長りよ
り小さく設定する。Furthermore, in order to almost completely suppress punch-through in a miniaturized MOS transistor with a channel length of 1 μm or less, the distance a between the lower surface of the source/drain impurity layer 4.5 and the lower surface of the surface low impurity concentration layer 8 is Set it to be smaller than the length.
具体的な一例としては、この距離ａはチャネル長りの半
分以下とする。As a specific example, this distance a is less than half the channel length.
また、高不純物濃度層９の不純物濃度を１ｏ１＠Ｃ！Ｉ
＋””以上の十分高い値とすることにより、接合空乏層
の高不純物濃度層９への広がりを実質的にほとんど０に
することができる。Also, the impurity concentration of the high impurity concentration layer 9 is set to 1o1@C! I
By setting the value to a sufficiently high value of +"" or more, the spread of the junction depletion layer to the high impurity concentration layer 9 can be substantially reduced to almost zero.
また低温特性を良好とするために、表面低不純物濃度層
８の導電型をその下の高不純物濃度層９の導電型と同一
にし、表面低不純物濃度層８が反対導電型不純物を実質
的にほとんど含まないようにしたものである。In addition, in order to improve the low-temperature characteristics, the conductivity type of the surface low impurity concentration layer 8 is made the same as the conductivity type of the high impurity concentration layer 9 below, so that the surface low impurity concentration layer 8 substantially eliminates impurities of the opposite conductivity type. It is designed to contain almost no amount.
本発明の代表的な実施例によるＭＯＳトランジスタ構造
においては、第１図に示すように表面低不純物濃度層８
がソース、ドレイン不純物層４゜５の深さよりも深く形
成されている。In a MOS transistor structure according to a typical embodiment of the present invention, as shown in FIG.
is formed deeper than the depth of the source and drain impurity layers 4.5.
従って、第３図の従来のＭＯＳトランジスタ構造よりも
表面低不純物濃度層８が厚く形成されている。このため
、第３図の従来例よりも表面電界が緩和される。Therefore, the surface low impurity concentration layer 8 is formed thicker than in the conventional MOS transistor structure shown in FIG. Therefore, the surface electric field is more relaxed than in the conventional example shown in FIG.
従って、第４図に示すようにＳｉ表面でのバンドの曲が
りがより緩やかになり、チャネル表面でキャリアが移動
可能なｎ型反転層の幅が更に拡大されるので、表面散乱
が減少する結果、キャリア移動度をより大きくすること
ができる。この効果はフォノン散乱より表面散乱の強ま
る低温でより顕著である。Therefore, as shown in FIG. 4, the band bending at the Si surface becomes more gradual, and the width of the n-type inversion layer in which carriers can move on the channel surface is further expanded, resulting in a reduction in surface scattering. Carrier mobility can be further increased. This effect is more pronounced at low temperatures where surface scattering is stronger than phonon scattering.
第５図と第６図にデバイス特性測定結果を示したように
、動作電流、電気伝導度ともに従来より向上でき、また
低電圧動作に不可欠なより低いしきい値電圧が実現でき
た。As shown in FIG. 5 and FIG. 6, the device characteristic measurement results show that both the operating current and electrical conductivity were improved compared to the conventional device, and a lower threshold voltage, which is essential for low-voltage operation, was achieved.
また本発明の代表的な実施例では、ソース、ドレイン不
純物層４，５と高不純物濃度層９との直接接触が表面低
不純物濃度層８によって避けられているので、従来問題
であった不純物層４，５のリーク電流を大幅に低減する
ことができる。Further, in the typical embodiment of the present invention, direct contact between the source and drain impurity layers 4 and 5 and the high impurity concentration layer 9 is avoided by the surface low impurity concentration layer 8, so that the impurity layer 4 and 5 can be significantly reduced.
また本発明の代表的な実施例では、ソース、ドレイン不
純物層４，５の接合の空乏層の下側への伸びが高不純物
濃度層９によって妨げられ、空乏層の下側への伸びは高
々ａの長さになる。この下側への伸びの制限により、横
方向、すなわちチャネル方向への空乏層の伸びも高々ａ
の長さに抑えられる。具体的な実施例では距離ａはチャ
ネル長しの半分以下としているので、結局、ドレイン空
乏層とソース空乏層の接触が避けられ、パンチスルーが
防止できる。このようにしてチャネル長１μｍ以下の微
細化されたＭｏＳトランジスタにおいて正常動作が実現
できる。Further, in a typical embodiment of the present invention, the downward extension of the depletion layer at the junction of the source and drain impurity layers 4 and 5 is prevented by the high impurity concentration layer 9, and the downward extension of the depletion layer is at most It will be the length of a. Due to this restriction on downward extension, the depletion layer may extend in the lateral direction, that is, in the channel direction, at most a
The length can be kept to . In the specific embodiment, the distance a is set to less than half the channel length, so that contact between the drain depletion layer and the source depletion layer can be avoided, and punch-through can be prevented. In this way, normal operation can be achieved in a miniaturized MoS transistor with a channel length of 1 μm or less.
また本発明の代表的な実施例では、表面低不純物濃度チ
ャネル層８に反対導電型不純物が実質的に含まれないよ
うにしたので、ゲースレンらが“Ｔｅｍｐｅｒａｔｕｒ
ｅ ｄｅｐｅｎｄｅｎｔ ｔｈｒｅｓｈｏｌｄ ｂｅｈ
ａｖｉｏｒｏｆ ｄｅｐｌｅｔｉｏｎ ｔｒａｄｅ Ｍ
ＱＳＦＥＴｓ−Ｃｈａｒａｃｔｅｒｉｚａｔｉｏｎａｎ
ｄ ５１ｍ１ａｔｉｏｎ”と題する論文（Ｓｏｌｉｄ−
５ｔａｔｅ Ｅｌｅｃｔ、。Furthermore, in the representative embodiment of the present invention, since the surface low impurity concentration channel layer 8 is substantially free of impurities of opposite conductivity type, Goeslen et al.
e dependent threshold beh
avioof depletion trade M
QSFETs-Characterization
d 51m1ation” (Solid-
5tate Elect.
ｖｏｌ、 ２２． ｐ、 ４２３．１９７９）で論じて
いるような不純物イオンのフリーズアウトによる特性劣
化を避けることができる。vol, 22. It is possible to avoid characteristic deterioration due to freeze-out of impurity ions as discussed in J.P., 423.1979).
なお本発明のＭＯＳトランジスタ構造をイオン打ち込み
法などの従来法で実現しようとすると。Note that if one attempts to realize the MOS transistor structure of the present invention using a conventional method such as ion implantation.
イオン飛程の統計的ゆらぎと打ち込み後の熱処理による
イオン不純物のため不純物プロファイルがだれ、実現困
難である。本実施例の急俊なプロファイルは、本実施例
の製法、すなわちエピタキシャル成長法の適用により初
めて実現できる。This is difficult to achieve because the impurity profile is distorted due to statistical fluctuations in the ion range and ion impurities due to post-implant heat treatment. The sharp profile of this example can only be achieved by applying the manufacturing method of this example, that is, the epitaxial growth method.
本発明の第一の実施例を、第１図により説明する。 A first embodiment of the present invention will be described with reference to FIG.
第１図において１は不純物濃度５ Ｘ １０”Ｃ！１１
−’以上のｐ型高不純物濃度基板またはウェル領域であ
り、ボロンのイオンの打ち込みによって形成したもので
ある。３はｐ型高不純物濃度基板またはウェル１上に、
減圧エピタキシャル成長法で形成したＳｉ単結晶層であ
る。この成長ではノンドープＳｉを８５０℃から１００
０℃の温度で結晶成長させ、層厚を５０から２００ｎｍ
とした。In Figure 1, 1 is the impurity concentration 5 x 10”C!11
-' or higher p-type high impurity concentration substrate or well region, and is formed by boron ion implantation. 3 is on the p-type high impurity concentration substrate or well 1,
This is a Si single crystal layer formed by a low pressure epitaxial growth method. In this growth, non-doped Si was grown from 850°C to 100°C.
Crystal growth is performed at a temperature of 0°C, with a layer thickness of 50 to 200 nm.
And so.
エピタキシャル成長時とその後の工程での加熱のため高
不純物濃度ＮｌからＳｉ単結晶層３へ不純物が拡散し、
Ｓｉ表面の低不純物濃度層（高濃度層より一桁濃度が低
い）はエピタキシャル成長層３より狭くなり、８で示す
領域となる。一方、最終的な高不純物濃度層９は、当初
の高不純物濃度層１とその上のＳｉ単結晶層３中の不純
物拡散層とにより形成されることとなる。本実施例では
プロセス時の加熱量を極力おさえた結果、デバイス完成
時の低不純物濃度層８の表面濃度を１０１１０ｌ７”以
下に抑えることができた。このようなエピタキシャル成
長により、従来のイオン打ち込み法では困難な急俊なプ
ロファイルが実現できる。Due to heating during epitaxial growth and subsequent steps, impurities diffuse from the high impurity concentration Nl into the Si single crystal layer 3.
The low impurity concentration layer (concentration is one order of magnitude lower than the high concentration layer) on the Si surface is narrower than the epitaxial growth layer 3, and becomes a region indicated by 8. On the other hand, the final high impurity concentration layer 9 is formed by the initial high impurity concentration layer 1 and the impurity diffusion layer in the Si single crystal layer 3 above it. In this example, as a result of suppressing the amount of heat during the process as much as possible, the surface concentration of the low impurity concentration layer 8 when the device was completed was able to be suppressed to 10110l7" or less. Due to this epitaxial growth, it was possible to Difficult and rapid profiles can be achieved.
エピタキシャル成長後は、ＬＯＣＯ５法により高圧酸化
を特に行なってフィールド酸化膜２を形成した。次いで
、ゲート酸化膜７とポリＳｉゲート層６を形成し、ＥＢ
リソグラフィー技術によって約０．１μｍのゲート長に
微細加工した。このゲート電極をマスクとして砒素イオ
ンを打ち込んで、ソース、ドレインとなるｎ＋不純物層
４，５を形成した。イオン活性化の熱処理はＲＴＡ（Ｒ
ａｐｉｄ Ｔｈｅｒｍａｌ Ａｎｎｅａｌｉｎｇ）法に
よって行ない、深さ３０〜５０ｎｍの浅い接合を形成し
た。そしてｐ型表面低不純物濃度層８の厚さがソース、
ドレイン不純物層４，５の接合深さよりも厚くなるよう
にし、表面低不純物濃度層８の下面とソース。After the epitaxial growth, field oxide film 2 was formed by particularly performing high-pressure oxidation using the LOCO5 method. Next, a gate oxide film 7 and a poly-Si gate layer 6 are formed, and an EB
The gate length was microfabricated to approximately 0.1 μm using lithography technology. Using this gate electrode as a mask, arsenic ions were implanted to form n+ impurity layers 4 and 5 that would become sources and drains. Heat treatment for ion activation is RTA (R
A shallow junction with a depth of 30 to 50 nm was formed using the apid thermal annealing method. The thickness of the p-type surface low impurity concentration layer 8 is the source,
It is made to be thicker than the junction depth of the drain impurity layers 4 and 5, and is connected to the lower surface of the surface low impurity concentration layer 8 and the source.
ドレイン不純物層４，５の下面の間の距離ａをチャネル
長りより小さく設定する。具体的な例としては、この距
離ａをチャネル長りの半分以下としてパンチスルーの発
生を防止した。The distance a between the lower surfaces of drain impurity layers 4 and 5 is set smaller than the channel length. As a specific example, the distance a was set to less than half the channel length to prevent punch-through.
以下、出来るかぎりプロセス温度を下げて、配線構造と
バッジベージ３ン膜を形成し、本実施例のＭＯＳトラン
ジスタを作成した。Thereafter, the process temperature was lowered as much as possible to form a wiring structure and a badge-base film, thereby producing the MOS transistor of this example.
本実施例によれば、表面低不純物濃度層８がン−ス、ド
レイン不純物Ｍ４，５ （深さ３０〜５０ｎｍ）よりも
厚いので、第４図に示すように従来よりも表面でのバン
ドの曲がりが緩やかになった。According to this embodiment, since the surface low impurity concentration layer 8 is thicker than the source and drain impurities M4,5 (depth 30 to 50 nm), the band width at the surface is more pronounced than in the conventional case, as shown in FIG. The curve has become gentler.
この結果、表面キャリア移動度が向上し、第５図に示す
ように７７にの低温動作時での動作電流は第２図の従来
型トランジスタの２．５倍、第３図の従来型の低不純物
濃度チャネルトランジスタの１．２５倍に増加した。第
６図に示すように、電気伝導度も大幅に向上し、しきい
値電圧の低減も図れた。７７にでのしきい値電圧は約０
．２Ｖ であり、ＣＭＯＳデバイスの７７に動作のほぼ
適正値である。As a result, the surface carrier mobility is improved, and as shown in Fig. 5, the operating current of the 77 at low temperature operation is 2.5 times that of the conventional transistor shown in Fig. 2, and lower than that of the conventional transistor shown in Fig. 3. The impurity concentration increased to 1.25 times that of the channel transistor. As shown in FIG. 6, the electrical conductivity was significantly improved and the threshold voltage was also reduced. The threshold voltage at 77 is approximately 0.
．． 2V, which is approximately the appropriate value for operation in a CMOS device 77.
また本実施例のゲート長りは約０．１μｍであり、この
トランジスタにドレイン電圧０．５Ｖ から１．５ｖを
印加したとき、接合空乏層の伸びは効果的に高不純物濃
度層９に妨げられる。不純物層接合と高濃度層の間には
長さａの表面低不純物濃度層８があり、距離ａはチャネ
ル長しの半分以下なので、ドレインとソースそれぞれの
空乏層の接触が避けられ、パンチスルーが防止できる。Furthermore, the gate length of this example is approximately 0.1 μm, and when a drain voltage of 0.5V to 1.5V is applied to this transistor, the expansion of the junction depletion layer is effectively prevented by the highly impurity concentration layer 9. . There is a surface low impurity concentration layer 8 with a length a between the impurity layer junction and the high concentration layer, and since the distance a is less than half of the channel length, contact between the depletion layers of the drain and source can be avoided, resulting in punch-through. can be prevented.
本実施例によればまた、ソース、ドレイン不純物層４，
５が高不純物濃度層８に直接接触していないので、ソー
ス、ドレイン不純物層４，５のリーク電流が低レベルに
抑えられる。According to this embodiment, source and drain impurity layers 4,
Since the impurity layer 5 is not in direct contact with the high impurity concentration layer 8, the leakage current of the source and drain impurity layers 4 and 5 can be suppressed to a low level.
また本実施例によれば、表面低不純物濃度チャネル８が
ｐ型不純物のボロンのみを含み、ｎ型不純物を実質的に
ほとんど含まないように作成したので、不純物イオンの
キャリアフリーズアウトに起因する低温特性不良も生じ
なかった。Furthermore, according to this embodiment, the surface low impurity concentration channel 8 is formed so as to contain only boron, which is a p-type impurity, and substantially no n-type impurity. No characteristic defects occurred.
上記の実施例ではｎチャネルＭＯ５）−ランジスタの実
施結果を述べたが、ｐチャネルＭＯＳトランジスタの場
合にも同様にして本発明が実現できることは勿論である
。In the above embodiments, the results of implementing an n-channel MO5)-transistor have been described, but it goes without saying that the present invention can be similarly implemented in the case of a p-channel MOS transistor.
本発明の第二の実施例を第７図に示す。これは本発明に
よるＣＭＯＳデバイスである。ここで９１はＳｉ基！、
９３ ［：鈍物濃度５ Ｘ １０”ａ＋１−３以上の高
不純物濃度ｐウェルであり、９４は不純物濃度５ Ｘ
１０”Ｑｌ−３以上のｎウェルである。A second embodiment of the invention is shown in FIG. This is a CMOS device according to the invention. Here 91 is Si group! ,
93 [: A p-well with a high impurity concentration of 5×10”a+1-3 or higher, and 94 has an impurity concentration of 5×
It is an n-well of 10"Ql-3 or more.
これらのウェル形成後、Ｓｉ表面にノンドープＳｉの減
圧エビタキシャルタキシャル成長を行なって形成した単
結晶薄膜が９０７である。エピタキシャル温度は８５０
〜１０００℃、膜厚は５０〜２００ｎｍであり、その表
面濃度を１０１７０−３以下の低濃度とした。ここでＳ
ｉの成長温度とその後のプロセス温度をできる限りおさ
えて、下側の高濃度層からの不純物拡散を防いでいる。After forming these wells, a single crystal thin film 907 was formed by performing low-pressure epitaxial growth of non-doped Si on the Si surface. Epitaxial temperature is 850
The temperature was 1000° C., the film thickness was 50 to 200 nm, and the surface concentration was as low as 10170-3 or less. Here S
The growth temperature of i and the subsequent process temperature are kept as low as possible to prevent impurity diffusion from the lower high concentration layer.
９２はＬＯＣＯ８法により高圧酸化で形成したフィール
ド酸化膜である。９９はゲート酸化膜、９８は燐を高濃
度にドープしたポリシリコンゲート、９０６はボロンを
高濃度にドープしたポリシリコンゲートであり、ＥＢク
リソラフィーの適用により、それぞれ約０．１μｍのゲ
ート長に加工されている。９０１はサイドウオール酸化
物、９６．９７はｎ中不純物層、９０４，９０５はｐ＋
不純物層であり、ＲＴＡの適用でそれぞれ３０〜５０ｎ
ｍ、および５０〜１００ ｎ ｍの深さに浅く形成され
ている。この結果、ｐ型表面低不純物濃度層９０３はｐ
＋不純物層９０４，９０５より厚くなり、ｎ型表面低不
純物濃度層９５はｎ÷不純物層９６．９７より厚くなっ
た。そして表面低不純物層の下面とソース、ドレイン不
純物層の下面の間の距離をチャネル長以下、具体的には
その半分以下としてパンチスルーを防止した。９０２は
不純物層およびポリシリコンゲート上に形成したＴｉＳ
ｉ２層である。すなわち本実施例はサリサイド構造を採
用している。92 is a field oxide film formed by high pressure oxidation using the LOCO8 method. 99 is a gate oxide film, 98 is a polysilicon gate doped with a high concentration of phosphorous, and 906 is a polysilicon gate doped with a high concentration of boron, each of which has a gate length of approximately 0.1 μm by application of EB chrysography. Processed. 901 is a sidewall oxide, 96.97 is an n-type impurity layer, 904 and 905 are p+
impurity layer, and by applying RTA, each layer is 30 to 50n.
m, and shallowly formed at a depth of 50 to 100 nm. As a result, the p-type surface low impurity concentration layer 903
+ impurity layers 904 and 905, and n-type surface low impurity concentration layer 95 was thicker than n÷ impurity layer 96.97. Punch-through was prevented by setting the distance between the bottom surface of the surface low impurity layer and the bottom surface of the source and drain impurity layers to be less than or equal to the channel length, specifically, less than half of the channel length. 902 is TiS formed on the impurity layer and the polysilicon gate.
This is the i2 layer. That is, this embodiment employs a salicide structure.
本実施例によれば、ｎチャネルＭＯＳトランジスタのチ
ャネル部にｐ型の表面低不純物濃度層を、ＰチャネルＭ
ＯＳトランジスタのチャネル部にｎ型の表面低不純物濃
度層を形成し、この表面低不純物濃度層の厚さをソース
、ドレイン不純物層深さより厚くしたので、第一の実施
例と同様に表面でのバンドの曲がりを緩和し、表面ポテ
ンシャルの低下と表面電界の緩和が図れた。この結果、
ｐｎｎチャネルＭＯＳトランジスタキャリア移動度が向
上し電気伝導度の大幅な向上が実現し、従来よりもずっ
と高速のＣＭＯＳデバイスが実現できた。この高速化と
同時にしきい値も低下し、ｐｎ両チャネルＭＯＳ）−ラ
ンジスタの７７にでのしきい値は約０．２ｖという適正
値を示した。According to this embodiment, a p-type surface low impurity concentration layer is formed in the channel part of an n-channel MOS transistor,
An n-type surface low impurity concentration layer is formed in the channel portion of the OS transistor, and the thickness of this surface low impurity concentration layer is made thicker than the depth of the source and drain impurity layers, so that the surface impurity concentration is reduced as in the first embodiment. The bending of the band was relaxed, the surface potential was lowered, and the surface electric field was relaxed. As a result,
PNN channel MOS transistor carrier mobility has been improved and electrical conductivity has been significantly improved, making it possible to realize CMOS devices that are much faster than conventional ones. At the same time as this increase in speed, the threshold value was also lowered, and the threshold value at 77 of the pn dual channel MOS transistor showed an appropriate value of about 0.2V.
第−の実施例と同様にして、不純物層リークと低温特性
不良も防止できた。このように本発明により、従来より
も高速かつ高性能のＣＭＯＳデバイスが実現できる。In the same manner as in the second embodiment, impurity layer leakage and poor low-temperature characteristics were also prevented. As described above, according to the present invention, a CMOS device that is faster and has higher performance than the conventional one can be realized.
本発明によれば、デバイス寸法が微細化されたＭＯＳ）
−ランジスタ構造において、パンチスルーを防止すると
ともに、Ｓｉ表面のキャリア移動度を更に改善すること
ができる。According to the present invention, a MOS with miniaturized device dimensions)
- In the transistor structure, punch-through can be prevented and carrier mobility on the Si surface can be further improved.
本発明によれば、ソース、ドレイン高不純物濃度層のリ
ーク電流を低減したＭＯＳトランジスタ構造を提供する
ことができる。According to the present invention, it is possible to provide a MOS transistor structure in which leakage current in the source and drain high impurity concentration layers is reduced.
本発明によれば、低温動作でＩ−Ｖ特性にキンクが生じ
るのを防止し、低温特性の良好な低不純物濃度チャネル
を有するＭＯＳ）−ランジスタを提供することができる
。According to the present invention, it is possible to provide a MOS transistor which prevents a kink from occurring in the IV characteristics during low temperature operation and has a low impurity concentration channel with good low temperature characteristics.
第１図は本発明の第一の実施例によるＭＯＳトランジス
タの構造図を示す図。
第２図および第３図は従来のＭＯＳトランジスタの構造
図を示す図、
第４図は第１図、第２図、第３図のＭＯＳトランジスタ
のＳｉ表面のバンド構造を示す図、第５図は第１図、第
２図、第３図のＭＯＳトランジスタの動作電流性能を示
す図。
第６図は第１図、第２図、第３図のＭＯＳトランジスタ
の電気伝導度改善効果を示す図、第７図は本発明の第二
の実施例によるＣＭＯＳデバイスを示す図である。
１・・・高不純物濃度基板、２・・フィールド酸化膜、
３・・・エビタキシャルタキシャル成長した単結晶Ｓｉ
薄膜、４・・・ソース不純物層、５・・・ドレイン不第
１図
第２図
第３図
Ｍ４図
！Δ）へｗ厖
ｘ ｗ厭滋披郵FIG. 1 is a diagram showing a structural diagram of a MOS transistor according to a first embodiment of the present invention. Figures 2 and 3 are diagrams showing the structure of conventional MOS transistors, Figure 4 is a diagram showing the band structure of the Si surface of the MOS transistors in Figures 1, 2, and 3, and Figure 5 is a diagram showing the structure of a conventional MOS transistor. 3 is a diagram showing the operating current performance of the MOS transistors shown in FIGS. 1, 2, and 3. FIG. FIG. 6 is a diagram showing the electrical conductivity improvement effect of the MOS transistors shown in FIGS. 1, 2, and 3, and FIG. 7 is a diagram showing a CMOS device according to a second embodiment of the present invention. 1...High impurity concentration substrate, 2...Field oxide film,
3...Ebitaxially grown single crystal Si
Thin film, 4... Source impurity layer, 5... Drain impurity Figure 1 Figure 2 Figure 3 Figure M4! Δ) to
Claims (1)
電型の高不純物濃度半導体領域上に形成された第一導電
型の表面低不純物濃度層と、該第一導電型の表面低不純
物濃度層中に成形された第二導電型のソース、ドレイン
不純物層と、 該第二導電型のソース、ドレイン不純物層の間の上記表
面低不純物濃度層の表面上に形成された絶縁ゲートとを
具備してなり、 上記第一導電型の上記表面低不純物濃度層の不純物濃度
が上記第一導電型の上記高不純物濃度半導体領域の不純
物濃度より一桁以上小さく設定され、 上記第一導電型の上記表面低不純物濃度層は上記第二導
電型の上記ソース、ドレイン不純物層より深く形成され
、 上記第二導電型の上記ソース、ドレイン不純物層の下面
と上記第一導電型の上記表面低不純物濃度層の下面との
間の距離が上記第二導電型の上記ソース、ドレイン不純
物層の間のチャネル長より小さく設定されてなることを
特徴とする半導体装置。 ２、上記チャネル長が１μｍ以下であることを特徴とす
る請求項１記載の半導体装置。 ３、上記距離は上記チャネル長の半分以下に設定されて
いることを特徴とする請求項１乃至２のいずれかに記載
の半導体装置。 ４、上記第一導電型の上記表面低不純物濃度層は第二導
電型不純物を実質的に含まないことを特徴とする請求項
１乃至３のいずれかに記載の半導体装置。 ５、上記第一導電型の上記表面低不純物濃度層は上記第
一導電型の上記高不純物濃度半導体領域上のエピタキシ
ャル成長により形成されてなることを特徴とする請求項
４記載の半導体装置。[Claims] 1. A high impurity concentration semiconductor region of a first conductivity type, a surface low impurity concentration layer of a first conductivity type formed on the high impurity concentration semiconductor region of the first conductivity type, and the first conductivity type high impurity concentration semiconductor region; A source/drain impurity layer of a second conductivity type formed in a surface low impurity concentration layer of one conductivity type, and a surface of the low surface impurity concentration layer between the source/drain impurity layers of the second conductivity type. an insulated gate formed, and the impurity concentration of the surface low impurity concentration layer of the first conductivity type is set to be at least one order of magnitude lower than the impurity concentration of the high impurity concentration semiconductor region of the first conductivity type. , the surface low impurity concentration layer of the first conductivity type is formed deeper than the source and drain impurity layers of the second conductivity type, and the lower surface of the source and drain impurity layers of the second conductivity type and the first conductivity A semiconductor device characterized in that a distance between the lower surface of the surface low impurity concentration layer of the mold is set smaller than a channel length between the source and drain impurity layers of the second conductivity type. 2. The semiconductor device according to claim 1, wherein the channel length is 1 μm or less. 3. The semiconductor device according to claim 1, wherein the distance is set to less than half the channel length. 4. The semiconductor device according to claim 1, wherein the surface low impurity concentration layer of the first conductivity type does not substantially contain impurities of the second conductivity type. 5. The semiconductor device according to claim 4, wherein the surface low impurity concentration layer of the first conductivity type is formed by epitaxial growth on the high impurity concentration semiconductor region of the first conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314000A JPH04186774A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314000A JPH04186774A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04186774A true JPH04186774A (en) | 1992-07-03 |
Family
ID=18048012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2314000A Pending JPH04186774A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04186774A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011103314A1 (en) * | 2010-02-18 | 2011-08-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
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