JPH04180675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04180675A JPH04180675A JP2309437A JP30943790A JPH04180675A JP H04180675 A JPH04180675 A JP H04180675A JP 2309437 A JP2309437 A JP 2309437A JP 30943790 A JP30943790 A JP 30943790A JP H04180675 A JPH04180675 A JP H04180675A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- silicon substrate
- silicon
- device layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000011344 liquid material Substances 0.000 claims abstract 4
- 239000011521 glass Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 34
- 229910052710 silicon Inorganic materials 0.000 abstract description 34
- 239000010703 silicon Substances 0.000 abstract description 34
- 238000000034 method Methods 0.000 abstract description 18
- 229910001415 sodium ion Inorganic materials 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 36
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000002411 adverse Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
第２図（ａｌ〜ｔａ＋の工程断面図により従来技術を説
明する。The prior art will be explained with reference to FIG. 2 (process sectional views from al to ta+).
第２図（ＪＩ）は、半導体シリコンを使った通常のＬＳ
Ｉプロセスにより作製されたシリコン半導体の断面図を
示す、２１は半導体シリコン基板、２２はトランジスタ
、抵抗、コンデンサー等が形成されているデバイス層、
２３は素子分離として使用しているＳｉ０ｇ層を示す。Figure 2 (JI) shows a normal LS using semiconductor silicon.
21 is a semiconductor silicon substrate, 22 is a device layer in which transistors, resistors, capacitors, etc. are formed;
23 indicates a Si0g layer used as element isolation.
次に、第１ｇ（ｂｌに示すように、エポキシ樹脂２４を
用いて、厚いシリコン基板２５に接着する。Next, as shown in the first g (bl), it is bonded to a thick silicon substrate 25 using an epoxy resin 24.
次に、第２図（ｃｌに示すように、デバイス層２２、Ｓ
ｔｏｗ層２３を残すように、シリコン基板２１を研磨す
る。ここで、デバイス層２２と５ｉｆｔ層２３をを含む
薄膜層２６が残る。Next, as shown in FIG.
The silicon substrate 21 is polished so that the tow layer 23 remains. Here, a thin film layer 26 including a device layer 22 and a 5ift layer 23 remains.
次に、第２図（ｄｌに示すように、シリコンデバイス層
２２が形成されている側と反対側２７（第２図（Ｃ）参
照）に、シリコン基板２９をエポキシ樹脂２８により接
着する。最後に、第２図（Ｉｌｌに示すように、上側の
シリコン基板２５を研磨により取り去る。エポキシ樹ｊ
１２８がこの時の研磨のストッパーとして使われる。更
に酸素プラズマにより、エポキシ樹１１２４が取り去ら
れる。Next, as shown in FIG. 2 (dl), a silicon substrate 29 is bonded with epoxy resin 28 to the side 27 opposite to the side on which the silicon device layer 22 is formed (see FIG. 2 (C)). Then, as shown in FIG. 2, the upper silicon substrate 25 is removed by polishing.
128 is used as a polishing stopper at this time. Furthermore, the epoxy tree 1124 is removed by oxygen plasma.
従来技術においては、第２図＋６１の図面において、接
着剤２８としてエポキシ樹脂を使用している。In the prior art, epoxy resin is used as the adhesive 28 in the drawing of FIG. 2+61.
デバイス２２とこのエポキシ樹脂２８は掻く近傍に存在
しているため、エポキシ樹脂より発止するナトリウムイ
オン（以後、Ｎａイオンと略す）がデバイス層２２に簡
単に侵入する。このＮａイオンがデバイス特性に悪影響
を与える１例えば、ＭＯＳ）ランジスタにおいて、ゲー
ト電圧を加えていない時に流れるリーク電流が、通常の
バルクシリコン上に作製したＭＯＳ）ランジスタのそれ
より数オーダー高いという現象が生しる。Since the device 22 and the epoxy resin 28 are located close to each other, sodium ions (hereinafter abbreviated as Na ions) emitted from the epoxy resin easily invade the device layer 22. These Na ions adversely affect device characteristics.1 For example, in a MOS transistor, the leakage current that flows when no gate voltage is applied is several orders of magnitude higher than that of a MOS transistor fabricated on normal bulk silicon. Live.
本発明は、上記した従来技術の欠点を解決するために半
導体デバイス層と基板の接着を、スピンオングラス法（
以後ＳＯＧ法と略す）による５ｉ０８層によって行うこ
とを特徴とする。In order to solve the above-mentioned drawbacks of the prior art, the present invention has developed a method for bonding a semiconductor device layer and a substrate using a spin-on glass method.
It is characterized in that it is performed using a 5i08 layer using the SOG method (hereinafter abbreviated as SOG method).
本発明はシリコンデバイス層のある薄膜層と基板の間に
ＳＯＧ法によりＳｉＯ□層を接着剤として設けると、５
ｊＯｚ中にはＮａイオン等のデバイス特性に悪影響を及
ぼす不純物は存在しないため、このＳ ｉＯｚの接着剤
と極（近傍の半導体シリコンデバイス層にＮａイオン等
の不純物は侵入しない。In the present invention, when a SiO□ layer is provided as an adhesive between a thin film layer with a silicon device layer and a substrate by the SOG method, 5
Since impurities such as Na ions that adversely affect device characteristics do not exist in the SiOz, impurities such as Na ions do not invade the semiconductor silicon device layer in the vicinity of the SiOz adhesive and the electrode.
第１図（ａｌ〜ｔｅｌの工程断面図により本発明の詳細
な説明する。The present invention will be explained in detail with reference to FIG. 1 (process sectional views from al to tel).
第１図（ａｌは、半導体シリコンを使った通常のＬＳＩ
プロセスにより作製されたシリコン半導体の断面図を示
す、１１は半導体シリコン基板、１２はデバイス層、１
３は素子分離用のＳｉ０１層を示す。Figure 1 (al is a normal LSI using semiconductor silicon
11 is a semiconductor silicon substrate, 12 is a device layer, 1 is a cross-sectional view of a silicon semiconductor manufactured by the process.
3 shows a Si01 layer for element isolation.
次に第１図世）に示すように、ＳＯＧ法を用いたＳ ｉ
Ｏｚ ）１１４を接着剤としてシリコン基板１１と他
のシリコン基板１５を接着する。液状の５ＯＧ１４をシ
リコン基板１１に塗布し、シリコン基板１５を乗せ、そ
の後約１５０℃程で熱することによって接着する。Next, as shown in Figure 1), S i using the SOG method
The silicon substrate 11 and another silicon substrate 15 are bonded using an adhesive (Oz) 114. Liquid 5OG14 is applied to the silicon substrate 11, the silicon substrate 15 is placed on it, and the silicon substrate 15 is then heated at about 150° C. to bond it.
次に第１図ｔｅｌに示すように、デバイス層１２とＳ
ｉ Ｏを層１３を含む＊＊層１６が残るように、シリコ
ン基板１１を研磨する。Next, as shown in FIG. 1, the device layer 12 and S
The silicon substrate 11 is polished so that the layer 16 containing the iO layer 13 remains.
次に第２図＋６１に示すように、シリコンデバイス層１
２が形成されている側と反対側１７ （第１図（Ｃ１参
照）に、シリコン基板１９をＳＯＧ法を使った３ｉ０ｘ
層１８により接着する。最後に第１図ｔａ＋に示すよう
に、上側のシリコン基板１５を研磨により取り去る。こ
れ以降、接着剤として使用したＳｔｏｗ層１８層数８去
っても良いし、残しておいても良い。Next, as shown in FIG. 2+61, the silicon device layer 1
2 is formed on the opposite side 17 (see Figure 1 (see C1)), the silicon substrate 19 is
Bonded by layer 18. Finally, as shown in FIG. 1 ta+, the upper silicon substrate 15 is removed by polishing. After this, the 18 Stow layers used as adhesives may be removed or may be left in place.
第３図（ａ）〜（Ｃ）の工程断面図により、本発明の他
の実施例を示す。Another embodiment of the present invention is shown by process cross-sectional views of FIGS. 3(a) to 3(C).
第３図（ａ）において、３１は通常のＬＳＩプロセスを
経てトランジスタ、抵抗、容量等が形成されたデバイス
層、３２はＳｉ０１層、３３は裏面シリコン層を示す、
このウニ／”％は３２のＳ ｉ ０１層が酸素イオン注
入により形成された５ｏｌ（ＳｉＯｎ Ｉｎ５ｕｌａ
ｔｏｒ）ウェハでも良し、裏面シリコンを熱酸化して他
のシリコン基板と高温で張り合わせたＳＯＩウェハでも
良い。In FIG. 3(a), 31 is a device layer in which transistors, resistors, capacitors, etc. are formed through a normal LSI process, 32 is a Si01 layer, and 33 is a backside silicon layer.
This percentage is 5ol (SiOn In5ula) in which 32 Si01 layers are formed by oxygen ion implantation.
tor) wafer, or an SOI wafer in which the back side silicon is thermally oxidized and bonded to another silicon substrate at high temperature.
第３図（ｂｌにおいて、このウェハをＳＯＧ法を用いた
Ｓｉ０１層を接着剤として利用して絶縁基板３５を張り
合わせる０次に、第３図ｔｅｌにおいて、例えば９０層
程度のＫＯＨ液にこのウェハを入れて、裏面シリコンを
エンチングする。ここで、注意すべきは接着剤として使
用した５ｉｎｔ層３４はデバイスが形成されているシリ
コンデバイス層３１のデバイスが形成されている側にあ
ることである。In Figure 3 (bl), this wafer is bonded to an insulating substrate 35 using a Si01 layer as an adhesive using the SOG method. Next, in Figure 3 (tel), this wafer is immersed in, for example, about 90 layers of KOH liquid. Here, it should be noted that the 5-int layer 34 used as an adhesive is on the side where the device is formed of the silicon device layer 31 where the device is formed.
〔発明の効果〕
以上、詳細に説明したように、本発明の半導体装置及び
その製造方法は、薄いシリコンデバイス層と半導体シリ
コン基板又は絶縁基板をＳＯＧ法を用いて形成したＳｉ
０１層を接着剤として利用し張り合わせた事により、接
着剤のＳｉＯ□層とデバイス層が掻く近傍にあっても、
？！′転性の高いＳｔｏ、層のため、Ｎａイオン等の不
純物によりデバイス特性が悪影響を受けることもなく、
安定なデバイス特性が得られる大きな利点を持っている
。[Effects of the Invention] As described above in detail, the semiconductor device and the method for manufacturing the same of the present invention provide a silicon device layer and a semiconductor silicon substrate or an insulating substrate formed using the SOG method.
By using the 01 layer as an adhesive and pasting them together, even if the adhesive SiO□ layer and the device layer are in close proximity to each other,
? ! 'Due to the highly conductive Sto layer, device characteristics are not adversely affected by impurities such as Na ions.
It has the great advantage of providing stable device characteristics.
第１図（ａｌ〜１８）は本発明の実施例を示す工程断面
図、第２図１８１〜ｔｅｌは従来技術の実施例を示す工
程断面図、第３図ｔａ＋〜（Ｃ１は本発明の他の実施例
を示す工程断面図である。
１１．１９・・・シリコン基板
１２．３２・・・シリコンデバイス層
１４．１８．３４・・・Ｓ ｉ Ｏｚ接着剤層３５・・
・・・・絶縁基板
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 林 敬 之 肋
木発明の半導体装ｌの製遁工程断面図
第３図FIG. 1 (al~18) is a process sectional view showing an embodiment of the present invention, FIG. 11.19...Silicon substrate 12.32...Silicon device layer 14.18.34...S i Oz adhesive layer 35...
・・・Insulating substrates and above Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent attorney: Takayuki Hayashi Figure 3: Cross-sectional view of the manufacturing process of the semiconductor device l of the invention
Claims (3)
薄い半導体基板層と厚い基板の間にガラス化液体材料の
固化した材料があることを特徴とする半導体装置。(1) A semiconductor device characterized in that a solidified vitrified liquid material is present between a thin semiconductor substrate layer on which a device layer including a transistor is formed and a thick substrate.
薄い半導体基板層の内、電子素子が形成されている側と
厚い基板の間にガラス化液体材料の固化した材料がある
ことを特徴とする半導体装置。(2) A semiconductor characterized by having a solidified vitrified liquid material between the thin semiconductor substrate layer on which the device layer including the transistor is formed and the side where the electronic elements are formed and the thick substrate. Device.
であることを特徴とする請求項１または２に記載の半導
体装置。(3) The vitrified liquid material is SOG (spin-on glass)
The semiconductor device according to claim 1 or 2, characterized in that:
Priority Applications (15)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02309437A JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
| US07/791,912 US5347154A (en) | 1990-11-15 | 1991-11-13 | Light valve device using semiconductive composite substrate |
| KR1019910020276A KR100292974B1 (en) | 1990-11-15 | 1991-11-14 | Semiconductor device and manufacturing method |
| DE69133628T DE69133628D1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| DE69133440T DE69133440T2 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| EP91310565A EP0486318B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| EP00200828A EP1026733B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| DE69133483T DE69133483T2 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve and its method of manufacture |
| EP98204180A EP0915503B1 (en) | 1990-11-15 | 1991-11-15 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| US08/264,635 US5486708A (en) | 1990-11-15 | 1994-06-23 | Light valve device using semiconductive composite substrate |
| US08/460,538 US5572045A (en) | 1990-11-15 | 1995-06-02 | Light valve device using semiconductive composite substrate |
| US08/460,536 US5728591A (en) | 1990-11-15 | 1995-06-02 | Process for manufacturing light valve device using semiconductive composite substrate |
| US08/459,834 US5618739A (en) | 1990-11-15 | 1995-06-02 | Method of making light valve device using semiconductive composite substrate |
| KR1019990044494A KR100311340B1 (en) | 1990-11-15 | 1999-10-14 | light valve device, method of manufacturing the device, and image projection system using the device |
| HK99105064.2A HK1020801A1 (en) | 1990-11-15 | 1999-11-05 | Semiconductor device for use in a light valve device, and process for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02309437A JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04180675A true JPH04180675A (en) | 1992-06-26 |
| JP3086958B2 JP3086958B2 (en) | 2000-09-11 |
Family
ID=17992991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02309437A Expired - Lifetime JP3086958B2 (en) | 1990-11-15 | 1990-11-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3086958B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
-
1990
- 1990-11-15 JP JP02309437A patent/JP3086958B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
| US6570221B1 (en) | 1993-07-27 | 2003-05-27 | Hyundai Electronics America | Bonding of silicon wafers |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3086958B2 (en) | 2000-09-11 |
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