JPH04180670A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04180670A JPH04180670A JP30973890A JP30973890A JPH04180670A JP H04180670 A JPH04180670 A JP H04180670A JP 30973890 A JP30973890 A JP 30973890A JP 30973890 A JP30973890 A JP 30973890A JP H04180670 A JPH04180670 A JP H04180670A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- polycrystalline silicon
- silicon
- transistor
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- -1 hydrogen ions Chemical class 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に抵抗内蔵モノリシック
トランジスタ、更に詳しくは耐湿性の点で極めて高信頼
度を達成できる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a monolithic transistor with a built-in resistor, and more particularly to a semiconductor device that can achieve extremely high reliability in terms of moisture resistance.
従来、この種の半導体装置は、第３図の如く、減圧気相
成長法にて成長させた一層のシリコン窒化膜５によって
、エミッタ３あるいはベース２という能動素子領域を外
部からのイオンや水分から守るために被覆し、また同時
に多結晶シリコン抵抗７の抵抗値が水素イオン等によっ
て変化するのを防ぐ目的で、多結晶シリコン抵抗を前記
シリコン窒化膜によって被覆した構造となっていた。Conventionally, in this type of semiconductor device, as shown in FIG. 3, an active element region called an emitter 3 or a base 2 is protected from external ions and moisture by a single layer of silicon nitride film 5 grown by low pressure vapor phase growth. The structure is such that the polycrystalline silicon resistor 7 is coated with the silicon nitride film to protect the resistor 7 and to prevent the resistance value of the polycrystalline silicon resistor 7 from changing due to hydrogen ions or the like.
上述した従来の半導体装置は、第３図に示した構造上多
結晶シリコン抵抗を形成し、パターニングしたあとでな
ければシリコン窒化膜によって被覆することができない
、このため、最も大切なエミッタあるいはベースという
能動素子領域を多結晶シリコンを形成するまでの間、外
部からのイオン等の汚染源から保護することができない
という欠点がある。Due to the structure shown in Figure 3, the conventional semiconductor device described above forms a polycrystalline silicon resistor and can only be covered with a silicon nitride film after patterning.For this reason, the most important emitter or base is A drawback is that the active element region cannot be protected from external contamination sources such as ions until the polycrystalline silicon is formed.
本発明の目的は、多結晶シリコン抵抗やツェナーダイオ
ードを内蔵するトランジスタにおいて、付加素子を形成
するまでの間に先に形成した重要な領域を汚染源から守
ることができ、かつ付加素子の保護もでき、信頼性の向
上した半導体装置を提供することにある。An object of the present invention is to protect an important region formed before forming an additional element from a source of contamination in a transistor incorporating a polycrystalline silicon resistor or a Zener diode, and also to protect the additional element. The object of the present invention is to provide a semiconductor device with improved reliability.
本発明の半導体装置は、エミッタやベースなどの能動素
子部分を被覆するための第１のシリコン窒化膜と、多結
晶シリコンを用いた抵抗やツェナーダイオード等の付加
素子部分を被覆するための第２のシリコン窒化膜とを有
している。The semiconductor device of the present invention includes a first silicon nitride film for covering active element parts such as an emitter and a base, and a second silicon nitride film for covering additional element parts such as resistors and Zener diodes using polycrystalline silicon. It has a silicon nitride film.
次に、本発明について図面を参照して説明する。第１図
は本発明の一実施例の縦断面図である。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
第１図に示すように、コレクタ１．ベース２゜エミッタ
３のトランジスタ構造の上に形成された第１のシリコン
酸化膜の全面を約１０００Ａの厚さの減圧気相成長法に
より形成した第１のシリコン窒化膜５によって被覆する
。さらに、トランジスタのベース領域の外側に約５００
０Ａの第２のシリコン酸化膜を形成し、その上に約４０
０ＯＡの多結晶シリコン膜を形成し、通常のイオン注入
法によりホウ素を注入し、しかるのち通常のりソグラフ
ィ法によって多結晶シリコン抵抗７を形成する。さらに
、その多結晶シリコン抵抗７を熱処理によって酸化した
のち、再び減圧気相成長法により約１０００Ａの第２の
シリコン窒化膜８によって多結晶シリコン抵抗７を被覆
する。その後、外部と電気的導通をとるためのコンタク
ト孔を開け、アルミニウム膜９によって電極を形成する
。As shown in FIG. The entire surface of the first silicon oxide film formed on the base 2° emitter 3 transistor structure is covered with a first silicon nitride film 5 having a thickness of about 1000 Å formed by low pressure vapor phase epitaxy. In addition, approximately 500 mm outside the base region of the transistor
A second silicon oxide film of 0A is formed, and a thickness of about 40A is formed on it.
A polycrystalline silicon film of 0OA is formed, boron is implanted by a normal ion implantation method, and then a polycrystalline silicon resistor 7 is formed by a normal lamination lithography method. Furthermore, after the polycrystalline silicon resistor 7 is oxidized by heat treatment, the polycrystalline silicon resistor 7 is again covered with a second silicon nitride film 8 of approximately 1000A by low pressure vapor phase growth. Thereafter, a contact hole is made for establishing electrical continuity with the outside, and an electrode is formed using the aluminum film 9.
最後に、プラズマ気相成長法によって形成した、約５０
００Ａの第３のシリコン窒化膜１０を被覆し、表面を保
護する構造としている。Finally, about 50
A third silicon nitride film 10 of 00A is coated to protect the surface.
本構造によって、トランジスタの最重要領域であるエミ
ッタ３やベース２などの能動素子部表面を、それらを形
成した直後に、第１のシリコン９化膜５によって保護す
ることができ、重要部分を外部の汚染源から守ることが
できる。また、第２のシリコン窒化膜によって、多結晶
シリコン抵抗がプラズマ気相成長中に発生する水素イオ
ン等によって抵抗値が変動するのを防止することができ
る。With this structure, the surfaces of active elements such as the emitter 3 and base 2, which are the most important regions of the transistor, can be protected by the first silicon 9ide film 5 immediately after they are formed, and important parts can be protected from the outside. can be protected from sources of pollution. Furthermore, the second silicon nitride film can prevent the resistance value of the polycrystalline silicon resistor from varying due to hydrogen ions and the like generated during plasma vapor deposition.
第２図は本発明の他の実施例の縦断面図である０本実施
例では、多結晶シリ°コンによるツェナーダイオード１
１を第２のシリコン窒化膜８によって被覆した構造であ
る。この実施例では、ツェナーダイオードの耐圧値の変
動を防止できる利点がある。FIG. 2 is a vertical cross-sectional view of another embodiment of the present invention. In this embodiment, a Zener diode 1 made of polycrystalline silicon is used.
1 is covered with a second silicon nitride film 8. This embodiment has the advantage of being able to prevent variations in the withstand voltage value of the Zener diode.
以上説明したように本発明は、トランジスタの信頼性上
量も重要なエミッタやベース領域を、それらを形成した
直後に、第１のシリコン窒化膜によって被覆するため、
その後に多結晶シリコン抵抗やツェナーダイオードなど
の付加素子を形成するまでの間に外部から浸入するイオ
ンなどの汚染源から守ることができ、半導体装置の信頼
性を向上できる効果がある。As explained above, the present invention covers the emitter and base regions, which are important in terms of transistor reliability, with the first silicon nitride film immediately after forming them.
Until additional elements such as polycrystalline silicon resistors and Zener diodes are subsequently formed, it is possible to protect the semiconductor device from contamination sources such as ions that enter from the outside, thereby improving the reliability of the semiconductor device.
家な、多結晶シリコン抵抗や多結晶シリコンによるツェ
ナーダイオードを第２のシリコン窒化膜で被覆すること
により、第３のシリコン窒化膜をプラズマ気相成長法で
形成する際の多量の水素イオンから保護し、抵抗値の変
動やツェナーダイオードの耐圧の変動を防止できる効果
がある。By covering a polycrystalline silicon resistor or a Zener diode made of polycrystalline silicon with a second silicon nitride film, it is protected from a large amount of hydrogen ions when the third silicon nitride film is formed by plasma vapor deposition. However, it has the effect of preventing fluctuations in resistance value and fluctuations in breakdown voltage of the Zener diode.
第１図は本発明の一実施例の縦断面図、第２図は本発明
の他の実施例の縦断面図、第３図は従来の抵抗内蔵トラ
ンジスタの一例の縦断面図である。
１・・・コレクタ、２・・・ベース、３・・・エミッタ
、４・・・第１のシリコン酸化膜、５・・・第１のシリ
コン窒化膜、６・・・第２のシリコン酸化膜、７・・・
多結晶シリコン抵抗、８・・・第２のシリコン窒化膜、
９・・・アルミニウム膜、１０・・・第３のシリコン窒
化膜、１１・・・多結晶シリコンによるツェナーダイオ
ード。FIG. 1 is a vertical cross-sectional view of one embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of another embodiment of the present invention, and FIG. 3 is a vertical cross-sectional view of an example of a conventional transistor with a built-in resistor. DESCRIPTION OF SYMBOLS 1... Collector, 2... Base, 3... Emitter, 4... First silicon oxide film, 5... First silicon nitride film, 6... Second silicon oxide film ,7...
Polycrystalline silicon resistor, 8... second silicon nitride film,
9... Aluminum film, 10... Third silicon nitride film, 11... Zener diode made of polycrystalline silicon.
Claims (1)
ェナーダイオードを内蔵するモノリシックシリコントラ
ンジスタにおいて、トランジスタの少なくともエミッタ
およびベース領域の表面を被覆する第１のシリコン窒化
膜と、それらの上に形成した多結晶シリコン抵抗や多結
晶シリコンによるツェナーダイオードを被覆する第２の
シリコン窒化膜とを有することを特徴とする半導体装置
。A monolithic silicon transistor incorporating a polycrystalline silicon resistor or a Zener diode made of polycrystalline silicon includes a first silicon nitride film covering at least the surfaces of the emitter and base regions of the transistor, and a polycrystalline silicon resistor or a polycrystalline silicon resistor formed thereon. A semiconductor device comprising: a second silicon nitride film covering a Zener diode made of polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30973890A JPH04180670A (en) | 1990-11-15 | 1990-11-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30973890A JPH04180670A (en) | 1990-11-15 | 1990-11-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04180670A true JPH04180670A (en) | 1992-06-26 |
Family
ID=17996708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30973890A Pending JPH04180670A (en) | 1990-11-15 | 1990-11-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04180670A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127167A (en) * | 1999-10-28 | 2001-05-11 | Mitsumi Electric Co Ltd | Semiconductor device |
| JP2006108543A (en) * | 2004-10-08 | 2006-04-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1990
- 1990-11-15 JP JP30973890A patent/JPH04180670A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127167A (en) * | 1999-10-28 | 2001-05-11 | Mitsumi Electric Co Ltd | Semiconductor device |
| JP2006108543A (en) * | 2004-10-08 | 2006-04-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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